The global imperative to transition towards sustainable energy sources has placed solar photovoltaic (PV) systems at the forefront of power generation technology. As the core component of a PV system, the on-grid inverter is responsible for the crucial conversion of direct current (DC) from solar panels into grid-compliant alternating current (AC). The performance, efficiency, and reliability of the entire PV installation hinge on the design and operation of this device.
Among various topologies, non-isolated on-grid inverters, which forego the use of low-frequency or high-frequency transformers, offer significant advantages in terms of cost, size, weight, and overall efficiency. However, the absence of galvanic isolation introduces a critical challenge: the generation of common-mode voltage (CMV). This CMV, stemming from the rapid switching of power semiconductor devices, drives common-mode currents through the parasitic capacitances between the PV array and the ground. These currents can lead to electromagnetic interference (EMI), increased losses, potential safety hazards, and accelerated component degradation, thereby compromising the system’s stability and lifespan. Consequently, the effective suppression of CMV is a paramount research focus in the development of advanced non-isolated on-grid inverters.
This paper addresses this challenge by proposing a novel three-phase non-isolated on-grid inverter topology integrated with a dedicated controllable switch. The central thesis is that by strategically controlling a single additional switch in the DC link, the formation of high-magnitude CMV states can be prevented. The proposed system employs Space Vector Pulse Width Modulation (SVPWM) to coordinate the switching states, effectively eliminating the zero vectors that produce the highest CMV. A comprehensive analysis, including parameter design, CMV modeling, modulation strategy implementation, and simulation verification, is presented to validate the efficacy of the proposed approach.
System Topology and Parameter Design of the Proposed On-Grid Inverter
The proposed controllable-switch non-isolated on-grid inverter topology is derived from the conventional three-phase two-level voltage source inverter (VSI). The key modification is the introduction of a controllable switch, denoted as S7, placed in series with the positive terminal of the DC bus. The system comprises the DC-link capacitor (Cdc), the three-phase inverter bridge with switches S1 to S6, the output LC filter (La, Lb, Lc and associated capacitors), and the parasitic capacitances (Ca, Cb, Cc) from the PV array to ground. The control logic, implemented typically on a platform like an STM32 microcontroller, generates gate signals for all seven switches based on SVPWM strategy and feedback from voltage and current sensors.
The operational principle is intuitive yet powerful: during active vector states (which are necessary for power conversion), switch S7 remains closed, and the inverter functions identically to a standard VSI. However, during the zero vector states (where all upper or all lower switches are on, causing a short-circuit across the load), the control algorithm opens switch S7. This action breaks the path for common-mode current flow during these specific intervals, thereby suppressing the CMV peaks associated with the standard zero states.
Critical Parameter Design
Proper design of component parameters is essential for the stable and efficient operation of the on-grid inverter. The design process for key components is outlined below.
1. IGBT Selection and DC-Link Voltage: For a system rated at 20 kW operating with a three-phase 220 Vrms (line-to-neutral) grid, the phase current effective value is approximately:
$$I_{\text{rms}} = \frac{P}{\sqrt{3} \times V_{\text{line-line}}} = \frac{20000}{\sqrt{3} \times 380} \approx 30.4 \text{ A}$$
Considering a safety margin of 1.5, the peak current could reach about 64.5 A. Therefore, an IGBT module with a rated current of 65 A or higher is selected. The required DC-link voltage (Udc) must be greater than the peak line-to-line AC voltage. For a 220 Vrms phase voltage, the peak line-to-line voltage is $\sqrt{2} \times \sqrt{3} \times 220 \approx 538 \text{ V}$. Accounting for voltage drops across switches and filters, a DC-link voltage of 700 V is chosen, necessitating IGBTs with a voltage rating (e.g., 1200 V) that provides sufficient headroom.
2. DC-Link Capacitor (Cdc): The DC-link capacitor stabilizes the input voltage. Its value is determined based on the allowable voltage ripple (ΔUdc), typically around 5-10% of Udc. Assuming a 10% ripple (70 V) at double the grid frequency for a three-phase system, the capacitance is calculated as:
$$C_{dc} = \frac{P}{2 \pi f \cdot U_{dc} \cdot \Delta U_{dc}}$$
Where $f$ is the grid frequency (50 Hz). Substituting the values:
$$C_{dc} = \frac{20000}{2 \pi \times 50 \times 700 \times 70} \approx 398 \text{ μF}$$
A standard value of 1000 μF per capacitor (often used in series pairs for voltage sharing) is selected.
3. AC-Side LC Filter: The output filter attenuates switching harmonics. The inductor (L) and capacitor (C) values are designed to meet harmonic standards (e.g., IEEE 1547) while avoiding resonance near the switching frequency. A common design rule is to set the filter’s resonant frequency (fLC) between one decade above the fundamental frequency and one decade below the switching frequency (fsw):
$$10 f_{\text{grid}} < f_{LC} < 0.1 f_{sw}$$
If fsw = 15 kHz, then $500 \text{ Hz} < f_{LC} < 1500 \text{ Hz}$. Choosing fLC ≈ 1000 Hz, and using the relation:
$$f_{LC} = \frac{1}{2\pi\sqrt{LC}}$$
The product LC is:
$$LC = \frac{1}{(2\pi f_{LC})^2} = \frac{1}{(2\pi \times 1000)^2} \approx 2.53 \times 10^{-8} \text{ s}^2$$
Selecting an inductor L = 3 mH (0.003 H) to limit current ripple, the required capacitor is:
$$C = \frac{2.53 \times 10^{-8}}{0.003} \approx 8.43 \text{ μF}$$
Standard values of L = 3 mH and C = 8.2 μF are therefore suitable for this on-grid inverter.
Analysis and Modeling of Common-Mode Voltage
To understand the suppression mechanism, a quantitative analysis of CMV in a standard three-phase VSI is necessary. The CMV (UCM) is defined as the average of the voltages from the three inverter phase terminals (A, B, C) to the DC-bus negative point N’ (or ground reference N in a balanced system).
$$U_{CM} = \frac{U_{AN’} + U_{BN’} + U_{CN’}}{3}$$
The voltages UAN’, UBN’, UCN’ are determined by the switching states. Defining the switching function Sx (where x = a, b, c) such that Sx=1 when the upper switch is ON and the lower switch is OFF, and Sx=0 for the opposite state, the terminal voltage relative to N’ is UxN’ = Sx ⋅ Udc.
A standard three-phase VSI has eight possible switching states, producing six active vectors (V1-V6) and two zero vectors (V0, V7). The corresponding CMV for each state can be calculated, as summarized in the table below.
| Vector | Switching State (Sa, Sb, Sc) | UAN’ | UBN’ | UCN’ | Common-Mode Voltage (UCM) |
|---|---|---|---|---|---|
| V0 | (0,0,0) | 0 | 0 | 0 | 0 |
| V1 | (0,0,1) | 0 | 0 | Udc | Udc/3 |
| V2 | (0,1,0) | 0 | Udc | 0 | Udc/3 |
| V3 | (0,1,1) | 0 | Udc | Udc | 2Udc/3 |
| V4 | (1,0,0) | Udc | 0 | 0 | Udc/3 |
| V5 | (1,0,1) | Udc | 0 | Udc | 2Udc/3 |
| V6 | (1,1,0) | Udc | Udc | 0 | 2Udc/3 |
| V7 | (1,1,1) | Udc | Udc | Udc | Udc |
The table reveals that the CMV in a conventional on-grid inverter alternates among four discrete levels: 0, Udc/3, 2Udc/3, and Udc. The zero vector V7 produces the maximum CMV (Udc), which is the primary source of high-frequency common-mode noise.
Suppression Principle: The proposed topology intervenes precisely at state V7. During the implementation of SVPWM, when the algorithm requires the application of the zero vector V7 (state 111), the controller simultaneously opens the controllable switch S7. This action disconnects the DC source from the inverter bridge. Although the bridge points A, B, C are still shorted together through the upper switches, the potential UAN’, UBN’, UCN’ becomes undefined/floating relative to N’, effectively preventing the establishment of the Udc CMV level. The other zero vector V0 (state 000) naturally produces 0 V CMV and does not require S7 to open. Therefore, the effective CMV levels in the proposed controllable-switch on-grid inverter are reduced to only two: Udc/3 and 2Udc/3. This significant reduction in the CMV magnitude and its rate of change (dv/dt) directly leads to a substantial decrease in the amplitude of the driven common-mode current.
Implementation of the SVPWM Modulation Strategy
The Space Vector Pulse Width Modulation (SVPWM) technique is employed for its superior DC-bus utilization and output harmonic performance. Its implementation for the proposed on-grid inverter involves sector identification, dwell time calculation, and the crucial integration of the S7 switching command.
Sector Identification
The target reference voltage vector Vref is represented in the αβ stationary frame (Vα, Vβ). The six active vectors divide the plane into six sectors. Sector identification is efficiently performed using the following intermediate variables:
$$
\begin{aligned}
V_{\text{ref1}} &= V_\beta \\
V_{\text{ref2}} &= \sqrt{3} V_\alpha – V_\beta \\
V_{\text{ref3}} &= -\sqrt{3} V_\alpha – V_\beta
\end{aligned}
$$
By evaluating the signs of these three variables, a sector number N can be derived as shown in the table below, which is optimal for digital implementation.
| Sector | Condition | Value (N) |
|---|---|---|
| I | Vref1 > 0 and Vref2 < 0 and Vref3 < 0 | 1 |
| II | Vref1 > 0 and Vref2 > 0 and Vref3 < 0 | 2 |
| III | V<sub{ref1< 0="" <="" and="" sub}="" vref2 > 0 and Vref3 < 0</sub{ref1 | 3 |
| IV | V<sub{ref1< 0="" <="" and="" sub}="" vref2 > 0 and Vref3 > 0</sub{ref1 | 4 |
| V | V<sub{ref1< 0="" <="" and="" sub}="" vref2 < 0 and Vref3 > 0</sub{ref1 | 5 |
| VI | V<sub{ref1 0 and Vref2 < 0 and Vref3 > 0</sub{ref1 | 6 |
Dwell Time Calculation
Once the sector is known, the reference vector is synthesized using the two adjacent active vectors (Vn, Vn+1) and the zero vectors (V0, V7). The dwell times Tn and Tn+1 for the active vectors within a switching period Ts are calculated using the volt-second balance principle. For Sector I (0 ≤ θ ≤ 60°), the times are:
$$
\begin{aligned}
T_1 &= \frac{\sqrt{3} T_s}{U_{dc}} \left( V_\alpha \sin(60^\circ – \theta) \right) \quad \text{(for V1, 001)} \\
T_2 &= \frac{\sqrt{3} T_s}{U_{dc}} \left( V_\alpha \sin(\theta) \right) \quad \text{(for V2, 010)} \\
T_0 = T_7 &= \frac{T_s – T_1 – T_2}{2}
\end{aligned}
$$
Where $V_\alpha$ and $V_\beta$ are the components of Vref, and $\theta = \arctan(V_\beta / V_\alpha)$. Similar geometric calculations yield formulas for all six sectors, often implemented via pre-calculated intermediate variables (X, Y, Z) in practical controllers to reduce computational burden.
Determination of Switching Sequences and S7 Control
A standard SVPWM sequence in a sector follows a symmetric pattern, e.g., for Sector I: V0 -> V1 -> V2 -> V7 -> V2 -> V1 -> V0. The key modification for the proposed on-grid inverter is the state of S7 during the application of V7. The control algorithm is designed as follows:
- During the time intervals allocated to active vectors (V1-V6) and the zero vector V0, the controllable switch S7 is kept CLOSED (conducting).
- During the time interval allocated to the zero vector V7, the controllable switch S7 is commanded to OPEN (non-conducting). The gate signals for S1, S3, S5 are still generated as per the V7 state, but with S7 open, the high CMV path is broken.
The timing for opening and closing S7 must be synchronized precisely with the PWM transitions to avoid shoot-through or voltage spikes. A small dead time may be necessary between the opening of S7 and the change of bridge states to ensure safe operation.
Simulation Verification and Results
To validate the theoretical analysis and the effectiveness of the proposed CMV suppression method, a simulation model of the controllable-switch non-isolated on-grid inverter was developed in MATLAB/Simulink. The system parameters were set as follows: DC-link voltage Udc = 700 V, output power P = 20 kW, grid voltage = 220 Vrms/50 Hz, switching frequency fsw = 15 kHz, DC-link capacitor Cdc = 1000 μF, filter inductor L = 3 mH, filter capacitor C = 8.2 μF, and PV parasitic capacitance to ground Cp = 1 μF.
Two critical simulation tests were performed:
- Baseline Case (S7 always ON): The controllable switch S7 was permanently closed, reducing the system to a conventional non-isolated on-grid inverter.
- Proposed Method Case (S7 controlled): The SVPWM algorithm with integrated S7 control was implemented, opening S7 during the V7 state intervals.
The simulation results focused on the waveform and harmonic spectrum of the common-mode voltage (UCM) and the resulting common-mode current (iCM) flowing through the parasitic capacitance.
Results for Baseline Case (S7 always ON): The measured CMV exhibited the characteristic four-level waveform, switching between 0, 233 V, 467 V, and 700 V (i.e., 0, Udc/3, 2Udc/3, Udc). The high-frequency transitions, especially the jumps to 700 V, generated a significant common-mode current. The RMS value of the common-mode current was measured to be approximately 0.796 A.
Results for Proposed Method Case (S7 controlled): The CMV waveform showed a marked improvement. The highest level (700 V corresponding to state V7) was effectively eliminated. The CMV now switched primarily between the two levels of 233 V and 467 V (Udc/3 and 2Udc/3). Consequently, the amplitude and the high-frequency content of the common-mode current were substantially reduced. The RMS value of the common-mode current dropped to approximately 0.382 A.
Comparative Analysis: The simulation data provides clear quantitative evidence. The proposed method achieved a reduction of over 50% in the RMS common-mode current (from 0.796 A to 0.382 A). This reduction directly translates to lower electromagnetic emissions, reduced stress on insulation, and improved overall system reliability. The output current quality and grid synchronization remained excellent in both cases, confirming that the modification does not adversely affect the primary power conversion function of the on-grid inverter.
Conclusion
This paper has presented a detailed research study on a novel controllable-switch non-isolated on-grid inverter topology for photovoltaic applications. The core innovation lies in the strategic placement and control of a single additional switch in the DC link, coordinated with an SVPWM modulation strategy. Theoretical analysis derived the common-mode voltage characteristics of standard inverters, identifying the zero vector V7 as the primary culprit for high-magnitude CMV. The proposed system disrupts the common-mode path precisely during this state, thereby suppressing the most harmful CMV component.
A comprehensive design procedure for the on-grid inverter parameters was outlined. The implementation of the SVPWM algorithm, including sector identification, dwell time calculation, and the integration of the S7 control signal, was explained in detail. Finally, simulation results provided unequivocal validation. The proposed topology demonstrated a greater than 50% reduction in the RMS common-mode current compared to the conventional topology, while maintaining excellent grid-tied performance.
The proposed solution offers a compelling balance between performance enhancement and circuit complexity. It adds only one controllable switch and minimal control logic to a standard inverter, making it a cost-effective and practical approach for mitigating common-mode issues in non-isolated on-grid inverters. This research contributes to the development of safer, more reliable, and electromagnetically cleaner photovoltaic power conversion systems, supporting the broader integration of solar energy into the modern grid.