With the steady advancement of new-type power systems, the source–grid–load highly power-electronic architecture has become a critical trend in modern electrical networks. Among various types of solar inverters, the LC-type inverter is extensively adopted as the interface between distributed generation units and the utility grid due to its superior high-order switching harmonic attenuation and reduced total inductance. However, the interaction between the LC filter and the grid impedance inevitably gives rise to an LCL resonance, which threatens system stability. Active damping based on state feedback provides a lossless way to suppress this resonance by emulating a virtual resistor in the filter. Nevertheless, in digital control implementations, the inherent 1.5 sample-period delay (one computation delay plus half a zero-order hold delay) degrades the damping performance, especially when the grid impedance varies. To address this issue, we propose a robust active damping method that employs double-sampling of the point-of-common-coupling (PCC) voltage to compensate the control delay. The novel approach utilizes both the carrier peak and trough sampling instants within the same switching cycle to construct a 1.5-step ahead signal, thereby extending the positive damping region of the PCC voltage feedforward to near the Nyquist frequency. This technique requires no additional parameter tuning and features a simple, plug-and-play logic. Experimental results demonstrate that the proposed method ensures stable operation of LC-type grid-connected inverters under various grid impedance conditions.
In this work, we focus specifically on the types of solar inverters that adopt an LC filter topology and are commonly employed in photovoltaic and energy storage applications. The proposed control method is validated through hardware-in-the-loop tests, confirming its effectiveness in damping the LCL resonance and enhancing robustness against grid impedance variations. The remainder of the paper is organized as follows: Section I presents the system model of the LC-type grid-connected inverter. Section II analyzes the inherent damping limitations caused by digital delay. Section III introduces the double-sampling delay compensation scheme. Section IV provides frequency-domain stability analysis. Section V reports experimental results, and Section VI concludes the work.
System Model of LC-Type Grid-Connected Inverter
The topology of the LC-type three-phase grid-connected inverter is shown schematically in Fig. 1 (omitted in text). The main parameters include the bridge-side inductor \(L_1\), the filter capacitor \(C_{\text{fil}}\), and the grid inductor \(L_{\text{grid}}\) representing the equivalent grid impedance. The inverter-side voltage \(v_{\text{inv}}\), PCC voltage \(v_{\text{pcc}}\), and grid voltage \(v_{\text{grid}}\) are measured. The control system employs a synchronous rotating frame using a phase-locked loop (PLL) to extract the phase \(\theta\) of \(v_{\text{pcc}}\). A proportional-integral (PI) current controller in the \(dq\)-frame regulates the bridge-side current \(i_1\). Additionally, a unity feedforward of the PCC voltage is applied to limit the inrush current during synchronization. The space vector pulse width modulation (SVPWM) generates the switching signals.
The continuous-domain transfer function of the PI controller is:
$$
H_{\text{con}}^i(s) = K_P + \frac{K_I}{s}
$$
where \(K_P\) is the proportional gain and \(K_I\) the integral gain. The digital delay transfer function under synchronous sampling is:
$$
H_{\text{del}}(s) = e^{-1.5 s T_{\text{sw}}}
$$
with \(T_{\text{sw}}\) being the switching period. The parameters of a 60 kW prototype are listed in Table 1.
| Parameter | Value |
|---|---|
| Grid voltage (line-to-line rms) | 380 V |
| DC-link voltage \(v_{\text{dc}}\) | 640 V |
| Bridge-side inductor \(L_1\) | 341 μH |
| Filter capacitor \(C_{\text{fil}}\) | 20 μF |
| Proportional gain \(K_P\) | 1.65 |
| Integral gain \(K_I\) | 794 |
| Grid frequency \(f_{\text{grid}}\) | 50 Hz |
| Switching frequency \(f_{\text{sw}}\) | 19.2 kHz |
Analysis of Inherent Damping and Stability Problem
To understand the impact of the 1.5-sample delay on active damping, we derive the equivalent virtual admittance models for both capacitor current feedback and PCC voltage feedforward. The equivalent control block diagram (Fig. 3 in original, omitted here) yields the following virtual parallel admittances:
For capacitor current feedback:
$$
Y_{\text{eq1}}(s) = \frac{K_P C_{\text{fil}}}{L_1} e^{-1.5 s T_{\text{sw}}}
$$
For PCC voltage feedforward:
$$
Y_{\text{eq2}}(s) = -\frac{1}{sL_1} e^{-1.5 s T_{\text{sw}}}
$$
Substituting \(s=j\omega\) gives the frequency-domain conductance and susceptance. The equivalent conductance of the PCC voltage feedforward (without compensation) is:
$$
G_{\text{eq2}}(\omega) = \Re\left\{-\frac{1}{j\omega L_1} e^{-1.5 j\omega T_{\text{sw}}}\right\} = \frac{\sin(1.5\omega T_{\text{sw}})}{\omega L_1}
$$
This function becomes negative for frequencies where \(\sin(1.5\omega T_{\text{sw}})<0\), i.e., \(\omega > \frac{\pi}{1.5T_{\text{sw}}}\)? Actually, the first zero crossing occurs at \(\omega = 2\pi f_{\text{sw}}/3\)? Let’s examine: The conductance sign is determined by the sine term. The positive damping region exists when \(\sin(1.5\omega T_{\text{sw}}) > 0\), which corresponds to \(\omega < \frac{2\pi}{3} f_{\text{sw}}\)? Since \(T_{\text{sw}}=1/f_{\text{sw}}\), the condition \(1.5\omega T_{\text{sw}} < \pi\) gives \(\omega < \frac{2\pi}{3} \cdot \frac{1}{T_{\text{sw}}} = \frac{2\pi}{3} f_{\text{sw}}\). Thus the positive damping frequency range is \(f < f_{\text{sw}}/3\). For capacitor current feedback, a similar analysis shows its positive damping range is \(f < f_{\text{sw}}/6\). Therefore, the combined positive damping region is narrower than \(f_{\text{sw}}/3\). When the LCL resonance frequency \(f_r\) exceeds this limit, the virtual conductance becomes negative, leading to open-loop right-half-plane (RHP) poles and instability. The resonance frequency is:
$$
\omega_r = \sqrt{\frac{L_1+L_{\text{grid}}}{L_1 L_{\text{grid}} C_{\text{fil}}}}, \qquad f_r = \frac{\omega_r}{2\pi}
$$
For the 60 kW system, when \(L_{\text{grid}}=25\ \mu\text{H}\), \(f_r\) reaches approximately 7.2 kHz (greater than \(f_{\text{sw}}/3=6.4\ \text{kHz}\)), causing instability. This confirms that the digital delay severely restricts the robustness of standard PCC voltage feedforward damping across different types of solar inverters.
Proposed Double-Sampling Delay Compensation Method
To extend the positive damping region, we propose a double-sampling technique for the PCC voltage. The core idea is to sample \(v_{\text{pcc}}\) at both the trough (AD1) and the peak (AD2) of the triangular carrier within the same switching cycle. The two samples, denoted \(v_{\text{pcc}}\) and \(v’_{\text{pcc}}\), are used to construct a 1.5-step ahead prediction of the PCC voltage. The computation delays of AD1 and AD2 are minimal and do not degrade the real-time performance. The modulation signal after compensation is:
$$
u’_m = u_m + (v_{\text{pcc}} + 3 \times (v’_{\text{pcc}} – v_{\text{pcc}}))
$$
where \(u_m\) is the initial modulation signal from the current controller. In the \(s\)-domain, this operation approximates a first-order predictor:
$$
v_{\text{pcc}}(s) + 3\left(v’_{\text{pcc}}(s)-v_{\text{pcc}}(s)\right) \approx (1 + 1.5 s T_{\text{sw}}) v_{\text{pcc}}(s)
$$
Hence, the compensated feedforward effectively cancels the 1.5-sample delay, because the original feedforward path introduces a factor \(e^{-1.5 s T_{\text{sw}}}\). The resulting equivalent virtual admittance after compensation becomes:
$$
Y^{\text{c}}_{\text{eq2}}(s) = -\frac{1 + 1.5 s T_{\text{sw}}}{s L_1} e^{-1.5 s T_{\text{sw}}}
$$
The corresponding conductance is:
$$
G^{\text{c}}_{\text{eq2}}(\omega) = \frac{\sin(1.5\omega T_{\text{sw}}) + 1.5\omega T_{\text{sw}} \cos(1.5\omega T_{\text{sw}})}{\omega L_1}
$$
The zero crossing of this function occurs at approximately \(0.48 f_{\text{sw}}\), as derived from numerical calculation. Thus the positive damping region of the PCC voltage feedforward is widened to nearly half the switching frequency. Even when combined with the capacitor current feedback (which has negative conductance above \(f_{\text{sw}}/6\)), the total equivalent conductance remains positive up to about \(0.46 f_{\text{sw}}\). This significantly improves the robustness against grid impedance variations. Moreover, the timing constraints for the digital processor are relaxed because the feedforward computation can be performed after the peak sampling, with a duration budget increased by \(5T_{\text{sw}}/12 – t_{\text{AD2}}\) compared to conventional real-time methods. No complex parameter tuning is required, making the scheme suitable for various types of solar inverters with different power ratings.
Stability Analysis after Compensation
The inner-loop gain after compensation is given by:
$$
T^{\text{com}}_{\text{in}}(s) = H_{\text{del}}(s) H_{v_{\text{inv}}-i_2}(s) \left( K_P s C_{\text{fil}} – \frac{1.5 s T_{\text{sw}} + 1}{L_{\text{grid}} s} \right)
$$
where \(H_{v_{\text{inv}}-i_2}(s) = 1/[L_1 L_{\text{grid}} C_{\text{fil}} s (s^2 + \omega_r^2)]\). The outer-loop gain is:
$$
T^{\text{com}}_{\text{out}}(s) = \frac{H_{\text{con}}^i(s) H_{\text{del}}(s) H_{v_{\text{inv}}-i_2}(s)}{1 + T^{\text{com}}_{\text{in}}(s)}
$$
Bode plots for three grid inductance values (25 μH, 100 μH, 180 μH) were examined (plots not shown in text). With compensation, the system remains minimum-phase for all cases; no RHP poles exist. The minimum gain margin is 2.3 dB and the minimum phase margin is 58°, both well above acceptable limits. In contrast, without compensation and with \(L_{\text{grid}}=25\) μH, the system exhibits non-minimum-phase behavior and becomes unstable. The frequency-domain analysis confirms that the proposed method guarantees closed-loop stability regardless of whether the LCL resonance frequency lies above or below \(f_{\text{sw}}/3\), thereby delivering robust performance for a wide range of types of solar inverters operating under weak grid conditions.
Experimental Verification
The proposed double-sampling delay compensation method was validated using a Typhoon HIL604 hardware-in-the-loop platform with a TMS320F28377D digital signal processor. The system parameters are identical to Table 1. Steady-state waveforms for three grid inductance values (180 μH, 100 μH, and 25 μH) were recorded. Without compensation, the inverter operates stably for \(L_{\text{grid}}=180\) μH and 100 μH, but exhibits severe high-frequency oscillations in the PCC voltage and grid current when \(L_{\text{grid}}=25\) μH. After enabling the double-sampling compensation, all three cases show clean sinusoidal waveforms with no oscillations. The grid-side current total harmonic distortion (THD) was measured and summarized in Table 2.
| Grid inductance \(L_{\text{grid}}\) | Without compensation | With compensation |
|---|---|---|
| 180 μH | 2.1% | 1.9% |
| 100 μH | 2.3% | 2.0% |
| 25 μH | 52.06% (LCL resonance) | 2.2% |
The frequency spectrum of the phase-A grid current reveals that the LCL resonant component (around 7.2 kHz) is suppressed from 52% to below 0.3% when the compensation is active. Dynamic tests were performed by switching from full load to half load. In all three grid inductance scenarios, the grid current recovers within 4 ms with overshoot less than 10%. These results confirm that the proposed method effectively damps the LCL resonance and improves the transient response across different types of solar inverters.
Conclusion
We have presented a robust active damping control method for LC-type grid-connected inverters based on double-sampling of the PCC voltage to compensate the 1.5-sample digital delay. By using the carrier peak and trough samples within a single switching cycle, a first-order predictor is constructed that extends the positive damping region of the PCC voltage feedforward to \(0.48 f_{\text{sw}}\). The method is free from complex parameter tuning, features a simple computational logic, and can be directly integrated into existing digital controllers. Experimental results demonstrate that the proposed technique stabilizes the inverter even when the LCL resonance frequency exceeds one-third of the switching frequency, which is a common limitation in standard active damping schemes. The work offers an effective solution for improving the grid impedance robustness of various types of solar inverters used in modern distributed generation systems.