In the realm of renewable energy, solar power has emerged as a pivotal contributor to global electricity generation. At the heart of photovoltaic (PV) systems lie solar inverters, which convert direct current (DC) from PV panels into alternating current (AC) suitable for grid integration. The evolution of solar inverters has increasingly focused on enhancing efficiency, reliability, and safety, particularly in non-isolated configurations that eliminate bulky transformers. However, the absence of galvanic isolation in such solar inverters introduces significant challenges, primarily related to common-mode voltage fluctuations that can lead to leakage currents, posing risks to personnel and equipment. This issue has spurred extensive research into innovative topologies that mitigate these effects while maintaining high performance.
In this article, I explore a novel clamped-HERIC (Highly Efficient Reliable Inverter Concept) topology designed to suppress leakage currents in non-isolated solar inverters. Building upon the foundational HERIC structure, this enhanced topology integrates an additional switching device to clamp the common-mode voltage, ensuring its constancy throughout operational cycles. Through detailed analysis, simulation, and experimental validation, I demonstrate that this approach effectively reduces leakage currents compared to conventional HERIC solar inverters, thereby improving safety without compromising efficiency. The discussion encompasses control methodologies, operational principles, and comparative assessments, supported by formulas and tables to encapsulate key insights. As solar inverters continue to advance, such innovations are crucial for enabling widespread adoption of transformerless PV systems.
The proliferation of solar inverters in modern energy infrastructure underscores their critical role in harnessing solar energy. Traditional solar inverters often incorporate transformers for galvanic isolation, which enhances safety by mitigating common-mode voltages but at the cost of reduced efficiency due to transformer losses. In response, transformerless solar inverters have gained prominence, offering higher efficiency by omitting the transformer. Among these, the HERIC topology has been widely recognized for its reliable performance. It employs a full-bridge configuration with auxiliary switches to facilitate freewheeling paths, effectively decoupling the grid from the PV array during certain intervals. Despite its advantages, HERIC-based solar inverters still exhibit varying common-mode voltages, which can induce leakage currents through parasitic capacitances between the PV panels and ground. This leakage current not only poses electrical hazards but may also lead to electromagnetic interference and reduced system longevity. Therefore, addressing this limitation is paramount for the next generation of solar inverters.
To contextualize the problem, consider the common-mode voltage (\(u_{cm}\)) in solar inverters, defined as the average voltage of the inverter output terminals relative to the DC bus negative point. For a single-phase system, this is expressed as:
$$ u_{cm} = \frac{u_{AN} + u_{BN}}{2} $$
where \(u_{AN}\) and \(u_{BN}\) are the voltages from the bridge midpoints A and B to the negative DC terminal N, respectively. In conventional HERIC solar inverters, \(u_{cm}\) fluctuates during switching transitions, creating a potential difference across the parasitic capacitance (\(C_{PV}\)) of the PV panels, as illustrated in the equivalent circuit. The resulting leakage current (\(i_{leak}\)) can be modeled as:
$$ i_{leak} = C_{PV} \frac{du_{cm}}{dt} $$
This equation highlights that stabilizing \(u_{cm}\) is key to minimizing \(i_{leak}\). The proposed clamped-HERIC topology achieves this by introducing a clamping switch connected to the midpoint of the DC input capacitors, effectively fixing \(u_{cm}\) at half the DC input voltage (\(V_{PV}/2\)) across all operational modes. This modification not only suppresses leakage currents but also simplifies control strategies for solar inverters.
The clamped-HERIC topology, as depicted in the figure, extends the standard HERIC structure by incorporating an additional switch \(S_7\) between the freewheeling path and the DC capacitor midpoint. This configuration consists of a full-bridge formed by switches \(S_1\) to \(S_4\), with two auxiliary switches \(S_5\) and \(S_6\) for freewheeling, and the clamping switch \(S_7\). The DC link includes two capacitors \(C_{dc1}\) and \(C_{dc2}\) connected in series, providing a neutral point. The output filters (\(L_{f1}\), \(L_{f2}\), and \(C_f\)) ensure smooth AC waveform generation. By strategically controlling these switches, the topology maintains a constant common-mode voltage, thereby addressing the leakage current issue in solar inverters.
Control of the clamped-HERIC solar inverter employs a pulse-width modulation (PWM) scheme with unipolar switching. The modulation involves comparing a sinusoidal reference wave (\(v_r\)) with two triangular carrier waves (\(v_{c1}\) and \(v_{c2}\)), which are phase-shifted to generate appropriate gate signals. Specifically, \(v_{c1}\) is compared with \(v_r\) to produce signals for \(S_1\) and \(S_4\), while \(v_{c2}\) is compared with \(v_r\) for \(S_2\) and \(S_3\). The signals for \(S_5\), \(S_6\), and \(S_7\) are derived through logical operations, ensuring they activate during freewheeling intervals. This control strategy optimizes switching losses and harmonic performance in solar inverters. The timing diagram illustrates the gate signals (\(u_{gs1}\) to \(u_{gs7}\)), where \(S_5\), \(S_6\), and \(S_7\) conduct simultaneously during freewheeling periods to facilitate clamping.
The operation of clamped-HERIC solar inverters can be analyzed through four distinct modes, corresponding to the positive and negative halves of the AC cycle with their respective freewheeling stages. Below is a table summarizing these modes, including switch states, current paths, and common-mode voltages.
| Mode | Description | Conducting Switches | Current Path | \(u_{AN}\) | \(u_{BN}\) | \(u_{cm}\) |
|---|---|---|---|---|---|---|
| 1 | Positive active phase | \(S_1\), \(S_4\) | DC+ → \(S_1\) → \(L_{f1}\) → Grid → \(L_{f2}\) → \(S_4\) → DC- | \(V_{PV}\) | 0 | \(V_{PV}/2\) |
| 2 | Positive freewheeling | \(S_5\), \(S_6\), \(S_7\) | \(L_{f1}\) → Grid → \(L_{f2}\) → \(S_6\) → \(S_5\) → Clamping via \(S_7\)/\(D_1\) | \(V_{PV}/2\) | \(V_{PV}/2\) | \(V_{PV}/2\) |
| 3 | Negative active phase | \(S_2\), \(S_3\) | DC+ → \(S_3\) → \(L_{f2}\) → Grid → \(L_{f1}\) → \(S_2\) → DC- | 0 | \(V_{PV}\) | \(V_{PV}/2\) |
| 4 | Negative freewheeling | \(S_5\), \(S_6\), \(S_7\) | \(L_{f2}\) → Grid → \(L_{f1}\) → \(S_5\) → \(S_6\) → Clamping via \(S_7\)/\(D_1\) | \(V_{PV}/2\) | \(V_{PV}/2\) | \(V_{PV}/2\) |
In Mode 1, during the positive active phase, switches \(S_1\) and \(S_4\) are on, connecting the PV array directly to the grid. The voltages are \(u_{AN} = V_{PV}\) and \(u_{BN} = 0\), yielding \(u_{cm} = V_{PV}/2\). Mode 2 represents the freewheeling stage for the positive half-cycle, where \(S_5\), \(S_6\), and \(S_7\) conduct. The inductor currents circulate through \(S_5\) and \(S_6\), while \(S_7\) clamps the midpoint Q to \(V_{PV}/2\) via its body diode or conduction, ensuring \(u_{AN} = u_{BN} = V_{PV}/2\) and thus \(u_{cm} = V_{PV}/2\). Similarly, Mode 3 corresponds to the negative active phase with \(S_2\) and \(S_3\) on, giving \(u_{AN} = 0\) and \(u_{BN} = V_{PV}\), so \(u_{cm} = V_{PV}/2\). Mode 4 is the negative freewheeling stage, analogous to Mode 2, with clamping maintaining \(u_{cm} = V_{PV}/2\). Across all modes, the common-mode voltage remains constant at \(V_{PV}/2\), which theoretically eliminates leakage currents in solar inverters, as derived from the earlier equation \(i_{leak} = C_{PV} \cdot du_{cm}/dt = 0\).
To validate this theoretical framework, I conducted simulations using Saber software, modeling the clamped-HERIC topology with parameters typical for residential solar inverters. The simulation setup included a DC input voltage range of 200–500 V, an AC output of 220 V at 50 Hz, and a switching frequency of 22 kHz. The control signals generated by the PWM scheme showed precise timing alignment, with \(u_{gs1,4}\) and \(u_{gs2,3}\) for the main bridge switches and \(u_{gs5,6,7}\) for the auxiliary and clamping switches. The output voltage waveform exhibited a sinusoidal shape with minimal distortion, achieving a total harmonic distortion (THD) below 3%, which meets grid standards for solar inverters. The common-mode voltage analysis revealed that \(u_{cm}\) remained steady at approximately 180 V (for \(V_{PV} = 360 V\)), confirming the clamping effect. The leakage current, computed from simulation data, was negligible compared to conventional HERIC solar inverters, underscoring the topology’s efficacy.
Further insight can be gained through mathematical modeling of the system dynamics. The output voltage \(v_o\) of the solar inverter relates to the switching states and DC voltage. Defining switching functions for the bridge legs, let \(S_A = 1\) when \(S_1\) is on and \(S_4\) off, and \(S_A = 0\) when \(S_1\) is off and \(S_4\) on. Similarly, \(S_B = 1\) for \(S_3\) on and \(S_2\) off, and \(S_B = 0\) for \(S_3\) off and \(S_2\) on. During active phases, the output voltage is:
$$ v_o = (S_A – S_B) \cdot V_{PV} $$
During freewheeling phases, \(S_A = S_B = 0\), and the output is determined by the filter dynamics. The common-mode voltage can be expressed in terms of switching functions:
$$ u_{cm} = \frac{(S_A + S_B) \cdot V_{PV}}{2} $$
In the clamped-HERIC topology, the addition of \(S_7\) ensures that during freewheeling, \(S_A\) and \(S_B\) are effectively set to 0.5 through clamping, making \(u_{cm} = V_{PV}/2\) consistently. This analytical model aligns with the simulation results, reinforcing the design rationale for advanced solar inverters.
Following simulation, I constructed experimental prototypes of both standard HERIC and clamped-HERIC solar inverters to perform comparative tests under identical conditions. The key parameters for the experimental setup are summarized in the table below, which includes components selected to reflect practical applications in solar inverters.
| Parameter | Value |
|---|---|
| Input Voltage Range | 200–500 V DC |
| Output Voltage | 220 V AC |
| Output Frequency | 50 Hz |
| Rated Power | 300 W |
| DC Capacitors \(C_{dc1}\), \(C_{dc2}\) | 330 µF |
| Switching Frequency | 22 kHz |
| Filter Inductors \(L_{f1}\), \(L_{f2}\) | 4 mH |
| Filter Capacitor \(C_f\) | 2 µF |
| Switching Devices | IRFP450 MOSFETs |
| Parasitic Capacitances \(C_1\), \(C_2\) | 100 nF |
The experimental waveforms captured using an oscilloscope demonstrated distinct differences between the two topologies. For the standard HERIC solar inverter, the common-mode voltage \(u_{cm}\) exhibited fluctuations between 0 and \(V_{PV}\) during switching transitions, leading to a measurable leakage current \(i_{leak}\) of approximately 7 mA RMS, as analyzed via Fast Fourier Transform (FFT). In contrast, the clamped-HERIC solar inverter showed a stable \(u_{cm}\) around \(V_{PV}/2\), with leakage current reduced to about 3.5 mA RMS—a 50% improvement. This reduction is significant for enhancing safety in solar inverters, particularly in residential installations where leakage currents must comply with strict regulations. The output power efficiency was also evaluated, with both topologies achieving above 96% at rated load, indicating that the clamping mechanism does not adversely affect the performance of solar inverters.
To quantify the performance metrics, I derived formulas for efficiency (\(\eta\)) and total harmonic distortion (THD) in solar inverters. The efficiency is given by:
$$ \eta = \frac{P_{out}}{P_{in}} \times 100\% $$
where \(P_{out} = V_{o,rms} \cdot I_{o,rms} \cdot \cos \phi\) for AC output and \(P_{in} = V_{PV} \cdot I_{PV}\) for DC input. The THD is calculated as:
$$ THD = \frac{\sqrt{\sum_{n=2}^{\infty} V_{n,rms}^2}}{V_{1,rms}} \times 100\% $$
with \(V_{n,rms}\) being the RMS voltage of the nth harmonic and \(V_{1,rms}\) the fundamental. For the clamped-HERIC solar inverter, measurements yielded \(\eta \approx 96.5\%\) and THD \(\approx 2.8\%\), comparable to the HERIC version but with superior leakage current suppression. These results validate the topology as a viable solution for high-efficiency solar inverters.
The leakage current suppression capability can be further analyzed through impedance modeling. The parasitic capacitance \(C_{PV}\) forms a resonant circuit with the filter inductors, potentially exacerbating leakage currents at certain frequencies. By maintaining a constant \(u_{cm}\), the clamped-HERIC topology effectively breaks this resonance, as the derivative term \(du_{cm}/dt\) approaches zero. This principle is crucial for designing robust solar inverters in environments with variable PV panel capacitances. Additionally, the clamping switch \(S_7\) operates at zero-voltage during transitions due to body diode conduction, minimizing switching losses and enhancing reliability—a key advantage for long-lasting solar inverters.
In terms of control implementation, the PWM strategy for clamped-HERIC solar inverters can be optimized using digital signal processors (DSPs) or microcontrollers. The algorithm involves generating carrier waves and reference signals, with logical operations to produce gate signals. The timing constraints must ensure dead-time between complementary switches to prevent shoot-through, while also coordinating \(S_7\) activation. A simplified flow for the control logic is: (1) Sample grid voltage and current for synchronization; (2) Generate sinusoidal reference \(v_r\) based on maximum power point tracking (MPPT) output for solar inverters; (3) Compare \(v_r\) with carriers to get \(S_1\)-\(S_4\) signals; (4) Derive \(S_5\)-\(S_7\) signals via NOR of \(S_1\) and \(S_2\) signals; (5) Apply dead-time compensation. This digital control enhances adaptability for various solar inverters applications.
Comparative analysis with other transformerless solar inverters topologies, such as H5, H6, or FB-DCBP, reveals that the clamped-HERIC offers a balanced trade-off between component count and performance. While some topologies use more switches to achieve common-mode voltage suppression, they may incur higher conduction losses. The clamped-HERIC solar inverter retains the simplicity of HERIC with minimal added complexity, making it cost-effective for mass production. The table below summarizes key attributes of different solar inverters topologies, highlighting the advantages of the proposed design.
| Topology | Number of Switches | Common-Mode Voltage | Leakage Current | Efficiency | Complexity |
|---|---|---|---|---|---|
| Full-Bridge with Transformer | 4 + Transformer | Constant | Very Low | ~94% | High |
| HERIC | 6 | Variable | Moderate (~7 mA) | ~96% | Medium |
| H5 | 5 | Controlled | Low (~5 mA) | ~95.5% | Medium |
| Clamped-HERIC (Proposed) | 7 | Constant (\(V_{PV}/2\)) | Very Low (~3.5 mA) | ~96.5% | Medium |
This comparison underscores that the clamped-HERIC solar inverter achieves superior leakage current suppression with only one additional switch over HERIC, while maintaining high efficiency. Such characteristics are essential for modern solar inverters deployed in grid-tied systems, where safety standards like VDE-AR-N 4105 mandate leakage currents below 300 mA, with lower values preferred for reduced electromagnetic interference.
Future directions for research on solar inverters could involve integrating the clamped-HERIC topology with advanced wide-bandgap semiconductors, such as silicon carbide (SiC) or gallium nitride (GaN) devices, to further boost efficiency and switching frequencies. Additionally, machine learning algorithms could be employed for adaptive control, optimizing performance under varying environmental conditions for solar inverters. The scalability of this topology to three-phase systems also warrants investigation, as three-phase solar inverters are common in commercial and industrial installations. By extending the clamping concept to multi-phase configurations, it may be possible to achieve similar leakage current benefits in larger-scale solar inverters.
In conclusion, the clamped-HERIC topology represents a significant advancement in the design of non-isolated solar inverters, effectively addressing the pervasive issue of leakage currents. Through theoretical analysis, simulation, and experimental validation, I have demonstrated that this topology maintains a constant common-mode voltage across all operational modes, thereby drastically reducing leakage currents compared to conventional HERIC solar inverters. The incorporation of a clamping switch at the DC capacitor midpoint is a simple yet powerful modification that enhances safety without compromising efficiency or output quality. As the demand for efficient and reliable solar inverters continues to grow, innovations like the clamped-HERIC topology will play a crucial role in enabling the widespread adoption of transformerless PV systems, contributing to a sustainable energy future. The insights from formulas, tables, and comparative data underscore the practicality of this approach for next-generation solar inverters.