With the increasing installed capacity of solar inverters, grid requirements have become more stringent, mandating that solar inverters possess fault ride-through capabilities. This means that during external grid faults, solar inverters must remain connected to the grid for a specified duration and provide reactive current during low-voltage ride-through to support grid voltage stability. The three-level neutral point clamped (NPC) solar inverter is widely used in photovoltaic grid-connected systems due to its advantages, such as reduced voltage stress on devices, high output waveform quality, and low switching losses. However, a inherent issue in three-level solar inverters is the balance of the midpoint potential, which has been extensively studied.
The midpoint potential control methods for three-level solar inverters can be categorized into four types: increasing DC capacitor capacity, using multiple independent DC power sources, employing additional power circuits to inject current into the midpoint, and improving modulation strategies. The fourth method is economically favorable and has yielded numerous research results. These include superimposing zero-sequence components during sinusoidal modulation and adjusting the action time of small vectors during space vector modulation. From a unified modulation theory perspective, these two basic methods are equivalent, and their analysis results can be referenced mutually. However, when applied to fault ride-through conditions, these basic methods have limitations, leading to various improved schemes.
For instance, some studies propose modulation methods that discard medium vectors, using two adjacent large vectors to synthesize medium vectors, thereby eliminating the impact of medium vectors on the midpoint potential. This approach selects switching vector sequences through a predictive model of the bus capacitor voltage difference, suppressing midpoint voltage fluctuations. However, it can cause direct switching between positive and negative buses and is only applicable to T-type three-level solar inverters, as it cannot achieve dynamic voltage sharing in diode-clamped three-level series connections. Another study introduces a modulation strategy that switches between space vector pulse width modulation (SVPWM) and virtual space vector modulation. Virtual space vector modulation redefines virtual small vectors and virtual medium vectors, ensuring that the average current flowing into the midpoint is zero over each carrier cycle, thus achieving full controllability of the midpoint potential across the entire modulation index and power factor range. However, virtual space vector modulation increases switching frequency, leading to significantly higher switching losses.
This paper addresses the midpoint potential balance issue in three-level solar inverters during fault ride-through. Based on existing pulse width modulation and midpoint balance methods, we propose a novel deep carrier overlapping PWM (DCO-PWM) method. By maximizing the overlap depth of the upper and lower carriers, the influence of medium vectors on the midpoint potential is weakened, enabling controllable midpoint potential balance and grid-connected current under fault impact and high reactive current conditions. To mitigate the increased switching frequency of power devices caused by DCO-PWM, we develop a phase-switching method for the modulation strategy. Only when the midpoint potential difference exceeds a set threshold is the intermediate phase of the modulation wave switched to DCO-PWM, while the conventional carrier phase disposition PWM (CPD-PWM) is retained for other states, thereby reducing the harmonic content of grid-connected current and device switching losses. Experimental results verify that this method effectively enhances control over grid-connected current and midpoint voltage during low-voltage fault ride-through in three-level solar inverters, ensuring safe and reliable fault state ride-through.
The topology of three-level solar inverters can be divided into diode-clamped three-level (NPC1), T-type three-level (NPC2), and active neutral point clamped three-level (ANPC). The choice of topology depends on the DC voltage: 1000 V photovoltaic systems typically select NPC2 due to lower losses, while 1500 V systems opt for NPC1 or ANPC for higher voltage tolerance. ANPC involves more switching devices per bridge arm and more complex control, so it is not discussed here. NPC1 and NPC2 have identical output levels and switching sequences, making them the focus of this paper. The NPC1-type solar inverter topology is shown in the figure above. Each phase leg of the inverter consists of four switching devices, four freewheeling diodes, and two clamping diodes. Photovoltaic panels are connected in series and parallel to form the DC voltage $U_d$, and two DC balancing capacitors $C_1$ and $C_2$ divide the DC voltage into two halves, each at $U_d/2$. The AC grid has a certain system impedance and is connected to the inverter via a step-down transformer. The grid connection point voltages are $U_a$, $U_b$, and $U_c$. Since the output voltage of the three-level bridge arm is a PWM waveform containing numerous high-order harmonics, a connection inductor $L_s$ and filter capacitor $C_s$ form a second-order filter to prevent high-order harmonics from being injected into the AC grid.
Taking phase B as an example, the working principle of the three-level solar inverter is analyzed: When $T_{1b}$ and $T_{2b}$ are turned on, point p is connected to the AC side; when $T_{2b}$ and $T_{3b}$ are turned on, due to the clamping diode, point o is connected to the AC side; when $T_{3b}$ and $T_{4b}$ are turned on, point n is connected to the AC side. Using point o as the zero-level reference, the AC side outputs three levels: $U_d/2$, 0, and $-U_d/2$. Each phase outputs p, o, n levels, resulting in 27 possible combinations.
Assuming the three-phase AC voltage output by the solar inverter is given by:
$$U_{sa} = U_m \cos(\omega t)$$
$$U_{sb} = U_m \cos(\omega t – 2\pi/3)$$
$$U_{sc} = U_m \cos(\omega t + 2\pi/3)$$
where $U_m$ is the amplitude of the AC voltage, $\omega$ is the angular frequency, and $t$ is time. The voltage reference vector $\vec{V}_{ref}$ is defined as:
$$\vec{V}_{ref} = \frac{2}{3} \left( U_{sa} + U_{sb} e^{j2\pi/3} + U_{sc} e^{j4\pi/3} \right)$$
The 27 switching states of the inverter correspond to basic voltage vectors, which can be classified into 3 zero vectors, 12 small vectors with magnitude $U_d/3$, 6 medium vectors with magnitude $\sqrt{3}U_d/3$, and 6 large vectors with magnitude $2U_d/3$. The space vector diagram is shown in the figure above, and the vector types are summarized in Table 1.
| Vector Type | Vector Magnitude | Quantity | Switching States |
|---|---|---|---|
| Zero Vector | 0 | 3 | ppp, ooo, nnn |
| Small Vector | $U_d/3$ | 12 | [poo, onn], [ppo, oon], [opo, non], [opp, noo], [oop, nno], [pop, ono] |
| Medium Vector | $\sqrt{3}U_d/3$ | 6 | pon, opn, npo, nop, onp, pno |
| Large Vector | $2U_d/3$ | 6 | pnn, ppn, npn, npp, nnp, pnp |
Fault ride-through performance is essential for ensuring the safe and stable operation of power systems with large-scale renewable energy integration and has become a mandatory requirement for grid-connected solar inverters. Fault ride-through includes low-voltage ride-through and high-voltage ride-through, with low-voltage ride-through further divided into symmetric and asymmetric ride-through. The active power requirements are: during low-voltage ride-through, within the inverter’s overcurrent range, appropriate active current should be maintained; after low-voltage ride-through, from the moment the fault is cleared, the power should smoothly recover to the pre-fault value at a rate of at least 30% of rated power per second; during high-voltage ride-through, the output active power should remain the same as before the fault. The dynamic reactive power requirements are: from the moment of AC side voltage abnormality, the response time of dynamic reactive current should not exceed 60 ms, with a maximum overshoot not exceeding 20%; the output dynamic reactive current of the solar inverter should track the grid connection point voltage in real time and satisfy:
$$I_T = K_1 \times (0.9 – U_T) \times I_N$$
$$I_T = K_2 \times (U_T – 1.1) \times I_N$$
where $I_T$ is the RMS value of the output dynamic reactive current, $U_T$ is the per-unit value of the grid connection point voltage, $I_N$ is the rated output current of the solar inverter, and $K_1$, $K_2$ are the proportional values of reactive current to voltage change. The values of $K_1$ and $K_2$ should be综合考虑 based on the short-circuit ratio at the grid connection point and the configuration of the station’s static var generator (SVG). Typically, $K_1$ ranges from 1.5 to 2.5, and $K_2$ ranges from 0 to 1.5. During symmetric faults, $I_T$ should not exceed $1.05I_N$ (to prevent exceeding the overcurrent limit of the solar inverter’s switching devices), and during asymmetric faults, $I_T$ should not exceed $0.4I_N$ (to prevent reactive current from raising the non-fault voltage too high).
Under normal operating conditions, solar inverters operate in pure active power generation, where CPD-PWM with superimposed zero-sequence components can effectively control the midpoint potential with low switching losses. However, fault ride-through conditions for solar inverters are more complex. As per the grid requirements, during high-voltage ride-through, the grid voltage can be as high as 1.3 p.u., and the absorbed reactive current can be up to $0.3I_N$. Both factors increase the midpoint potential fluctuation in CPD-PWM. During low-voltage ride-through, the grid voltage can be as low as 0 p.u., and the emitted reactive current can be up to $1.05I_N$, resulting in pure reactive power generation. Additionally, sudden voltage dips and recoveries can distort the grid current, disrupting the symmetry of the midpoint current injection from each phase and making the midpoint potential more prone to loss of control.
In summary, under fault ride-through conditions with high modulation indices or large reactive currents, the influence of medium vectors on the midpoint current becomes significant, which is the main reason for the loss of control in three-level solar inverters. Both small vectors and medium vectors affect the midpoint potential: the positive and negative states of small vector pairs have opposite effects on the midpoint potential, allowing the selection of small vectors beneficial for midpoint control. However, medium vectors lack redundant states for cancellation. Therefore, in sector 1, the influence of the medium vector pon must be weakened. The relationship between the midpoint potential offset and the injected midpoint current is given by:
$$\Delta U_0 = \frac{1}{2C} \int I_{np} dt$$
where $\Delta U_0$ is the midpoint potential offset, $C$ is the DC capacitor capacity, and $I_{np}$ is the current injected into the midpoint.
Analyzing the current injected into the midpoint when the medium vector acts, the connection state of pon and the solar inverter currents $I_{sa}$, $I_{sb}$, $I_{sc}$ (defined as positive when flowing out of the solar inverter) are shown in the figure above. When $U_{c1} > U_{c2}$, a negative $I_{sb}$ causes $U_{c2}$ to rise, so the medium vector pon is beneficial for midpoint balance and should be retained; when $U_{c1} < U_{c2}$, a negative $I_{sb}$ still causes $U_{c2}$ to rise, so pon is detrimental and should be replaced. For positive current, the opposite occurs: when $U_{c1} > U_{c2}$, a positive $I_{sb}$ causes $U_{c2}$ to fall, so pon is detrimental and should be replaced; when $U_{c1} < U_{c2}$, a positive $I_{sb}$ causes $U_{c2}$ to fall, so pon is beneficial and should be retained.
Some studies use large vectors ppn and pnn to synthesize the medium vector pon, each acting for half the time, effectively switching phase B to two-level modulation. This prevents current $I_b$ from injecting into the midpoint and avoids midpoint potential changes. However, this method is only applicable to NPC2-type solar inverters and not NPC1. Here, we improve it using the deep carrier overlapping PWM method.
Due to the symmetry of space vectors, the same approach applies to different medium vectors. The unfavorable directions of the six medium vectors for midpoint potential balance are summarized in Table 2. When the direction of the midpoint current and the midpoint potential difference are the same, the medium vector is detrimental to midpoint balance, and DCO-PWM should be used to generate the trigger pulses for the intermediate phase.
| Medium Vector | Midpoint Current Direction | Midpoint Potential Direction |
|---|---|---|
| pon | $I_{sb} < 0$ | $U_{c1} < U_{c2}$ |
| pon | $I_{sb} > 0$ | $U_{c1} > U_{c2}$ |
| opn | $I_{sa} < 0$ | $U_{c1} < U_{c2}$ |
| opn | $I_{sa} > 0$ | $U_{c1} > U_{c2}$ |
| npo | $I_{sc} < 0$ | $U_{c1} < U_{c2}$ |
| npo | $I_{sc} > 0$ | $U_{c1} > U_{c2}$ |
| nop | $I_{sb} < 0$ | $U_{c1} < U_{c2}$ |
| nop | $I_{sb} > 0$ | $U_{c1} > U_{c2}$ |
| onp | $I_{sa} < 0$ | $U_{c1} < U_{c2}$ |
| onp | $I_{sa} > 0$ | $U_{c1} > U_{c2}$ |
| pno | $I_{sc} < 0$ | $U_{c1} < U_{c2}$ |
| pno | $I_{sc} > 0$ | $U_{c1} > U_{c2}$ |
Three-level pulse width modulation methods mainly include carrier modulation, SVPWM, and selective harmonic elimination. Carrier modulation is the most studied. Four carrier modulation methods are compared: carrier phase disposition, carrier phase opposition disposition, carrier phase overlap, and carrier phase opposition overlap. Among them, carrier phase disposition has low line voltage harmonics, and carrier phase overlap has small midpoint voltage fluctuations. The general method of carrier overlap modulation is to add vertical offsets to two carriers, causing them to overlap. This is a modulation strategy that considers both carrier phase and offset. However, in normal carrier overlap modulation, the average output voltage waveform at different modulation indices is not linear, causing significant distortion in the solar inverter output voltage and current. This is because the gain slope in the overlap region differs from that in the non-overlap region. Although some studies propose a method to correct the carriers so that the gain is the same at the overlap point, it still cannot eliminate the difference in gain slopes between the two regions.
This paper proposes a deep carrier overlapping PWM method for the intermediate phase of the modulation wave. As shown in the figure above, $t_s$ is the carrier period, and $h$ is the overlap depth of the upper and lower carriers. When the modulation wave $u_b$ is greater than the upper carrier $c_{w1}$, the output is p level; when it is less than the lower carrier $c_{w2}$, the output is n level; and when it is between the two carriers, the output is o level. The trigger pulses for the four switching devices of phase B are $T_1$ to $T_4$. By maximizing $h$, the intermediate phase modulation operates entirely in the overlap region, avoiding the impact of gain突变 between overlap and non-overlap regions. Deep carrier overlap reduces the action time of the medium vector pon and eliminates the drawback of phase B switching between positive and negative buses.
The modulation wave gain in the overlap region is given by:
$$k_u = 2(1 + h)$$
The carrier cycle proportion of zero level is:
$$k_z = (1 – h) / (1 + h)$$
where $k_u$ is the modulation wave gain in the overlap region, and $k_z$ is the carrier cycle proportion of zero level.
When the midpoint balance is unfavorable, DCO-PWM is used for pulse width modulation of the intermediate phase modulation wave. Since $h$ is very large, the output o level time is very short, close to two-level modulation, which increases grid current harmonics and cannot be used as a normal modulation method, only during fault ride-through.
In summary, the performance of deep carrier overlap modulation, carrier phase disposition modulation, the method discarding medium vectors, and virtual space vector modulation during fault ride-through is compared in Table 3. DCO-PWM has moderate switching frequency, good midpoint control capability, is applicable to both NPC1 and NPC2 topologies, and does not require complex space vector calculations, making it a well-rounded fault ride-through modulation scheme for solar inverters.
| Modulation Method | CPD-PWM | Literature [11] | Literature [13] | DCO-PWM |
|---|---|---|---|---|
| Midpoint Control Capability | Worst | Good | Best | Good |
| Switching Frequency | Lowest | Lowest | Highest | Moderate |
| Applicable Topologies | NPC1, NPC2 | NPC2 | NPC1, NPC2 | NPC1, NPC2 |
The selection of carrier overlap depth must satisfy two conditions: 1) The zero-level time must be greater than four times the power device turn-off time, which determines the maximum overlap depth; 2) The intermediate phase modulation wave must be in the overlap region at the maximum modulation index, which determines the minimum overlap depth.
For high-power switching devices, the fall turn-off time is about 1 μs, and with a carrier frequency of 3.5 kHz, the maximum overlap depth is 0.97 according to the equation. The maximum modulation index occurs during high-voltage ride-through. To improve DC voltage utilization, the original modulation wave is subtracted from the over-modulation component to achieve 1.15 times over-modulation. The over-modulation component $z_{OVM}$ is given by:
$$z_{OVM} = (m_{abc.max} + m_{abc.min}) / 2$$
where $m_{abc.max}$ is the maximum value of the original modulation wave, and $m_{abc.min}$ is the minimum value of the original modulation wave.
After subtracting the over-modulation component, the shape of the modulation wave becomes saddle-shaped, as shown in the figure above. Clearly, the overlap depth $h$ must be greater than the intersection of $v_a$ and $v_b$ to ensure the intermediate phase is in the carrier overlap region. Thus, the minimum overlap depth is 0.866. From the above analysis, a larger overlap depth results in better midpoint balance but leaves less time for power device turn-off. Here, we set $h = 0.9$, so $k_u = 1.05$, slightly higher than the 1.0 gain of CPD-PWM, and $k_z = 5.26\%$.
DCO-PWM only replaces medium vectors that affect the midpoint potential for short durations. For sector 1, the reference vector must fall into small partitions 3–6 to use the medium vector pon. However, determining small partitions in the space vector diagram requires trigonometric functions, which are difficult to implement on microcontrollers. This paper provides a method to determine the medium vector interval from CPD-PWM, avoiding trigonometric calculations. The modulation sequence of CPD-PWM in small sector 5 is shown in the figure above. The modulation waves for phases A, B, and C are $u_a$, $u_b$, and $u_c$, respectively, and remain constant within the carrier period using symmetric regular sampling. From the relationship between the three-phase modulation waves, the pon state occurs when $u_a – u_c > 1$. This relationship holds for other partitions as well, so the criterion for medium vector action is:
$$u_{abc.max} – u_{abc.min} > 1$$
where $u_{abc.max}$ is the maximum value of the three-phase modulation waves, and $u_{abc.min}$ is the minimum value of the three-phase modulation waves.
To meet the different modulation requirements of normal operation and fault ride-through states, the overall modulation scheme for three-level solar inverters needs to switch between CPD-PWM and DCO-PWM. The specific process is shown in the figure above, divided into three modules: over-modulation, zero-sequence injection, and modulation switching.
The lines labeled 3 represent phases A, B, and C, and the lines labeled 12 represent 12 trigger pulses, corresponding to 4 pulses per phase for a total of 12 trigger pulses for the solar inverter. The DCO module is used to modify the medium vector pulses generated by the original CPD module, switching only when the midpoint potential difference exceeds the threshold and the direction of the midpoint-connected phase current is the same. The 12G is a phase-separated pulse selection module. For each phase, there are 4 trigger pulses $T_1$ to $T_4$. When the pulses generated by CPD use medium vectors and the phase selection signal $3S$ for phase A (or B, C) is 1, the 4 pulses for phase A (or B, C) of 12G are provided by the DCO module, while the other two phases’ 8 pulses are still provided by the CPD module.
1) Over-modulation: This module subtracts the over-modulation component from the original modulation wave $m_{abc}$ to meet high-voltage ride-through requirements. The over-modulation component is given by the equation above, and after subtraction, the modulation wave becomes $v_{abc}$.
2) Zero-sequence injection: This module outputs a zero-sequence component $z_u$. The modulation wave $v_{abc}$ is superimposed with the zero-sequence component to become $u_{abc}$, which can effectively balance the midpoint potential when the power factor is high (essentially adjusting the action time proportion of redundant small vector pairs). The midpoint potential $u_{np}$ is obtained by subtracting $U_{c2}$ from $U_{c1}$. LPF is a low-pass filter used to remove high-frequency components of the midpoint potential, and PI is a proportional-integral controller. The DIR module calculates the direction of the small vector dominant current, determined by the original modulation wave $m_{abc}$ and the solar inverter current $I_{cnv}$. When the dominant current is greater than 0, it outputs +1; when less than 0, it outputs -1. The output of the PI controller is multiplied by the DIR direction to obtain the zero-sequence component $z_u$.
3) Modulation switching: Under normal grid-connected generation, the modulation wave $u_{abc}$ is sent to the carrier phase disposition element CPD for comparison, outputting three-phase 12 trigger pulses $12G$. When the midpoint potential $u_{np}$ exceeds the threshold of ±4%, it indicates that zero-sequence injection cannot effectively balance the midpoint. At this time, the direction of the solar inverter current $I_{cnv}$ is determined phase by phase. When the phase current and midpoint potential direction are the same, and the pulses generated by CPD use medium vectors, the modulation wave of that phase is compared by the deep carrier overlap element DCO to generate pulses, while the pulses of the other two phases are still generated by the CPD module. The VEC module determines whether the pulses generated by CPD use medium vectors, using the criterion above. The gain module G compensates for the gain change of deep carrier overlap. When $h = 0.9$, the gain is $1/1.05$. $3S$ is the switching signal for the three-phase pulses.
Since modulation switching is performed phase by phase and only when the midpoint potential exceeds ±4%, after switching, the switching frequency of that phase increases from 1 to 2 times. Compared to the literature [13] scheme, the midpoint potential fluctuation increases slightly, but switching frequency is reduced, lowering switching losses for solar inverters.
Experimental verification was conducted on a new energy fault ride-through test platform as shown in the figure above. The tested solar inverter has a DC voltage of ±700 V, AC line voltage of 690 V, positive and negative DC capacitors of 3.8 mF each, connection inductance of 0.36 mH, filter capacitance of 55 μF, rated capacity of 500 kW, and carrier frequency of 3.5 kHz. The upper-level control is a vector current control that meets fault ride-through requirements with positive and negative sequence decomposition, and the underlying modulation strategy follows the aforementioned switching scheme.
The waveforms of asymmetric low-voltage ride-through without DCO-PWM are shown in the figure above, and with DCO-PWM in the figure above; the recovery waveforms of symmetric low-voltage ride-through without DCO-PWM are shown in the figure above, and with DCO-PWM in the figure above; the waveforms of high-voltage ride-through without DCO-PWM are shown in the figure above, and with DCO-PWM in the figure above. In the figures, $U_a$, $U_b$, $U_c$ are the grid connection point voltages; $I_a$, $I_b$, $I_c$ are the grid connection point currents; $S_{3a}$, $S_{3b}$, $S_{3c}$ are the pulse switching signals for phases A, B, and C, respectively.
In the asymmetric low-voltage ride-through without DCO-PWM, phase A voltage drops to 0 p.u. at 0.3 s, positive-sequence voltage drops to 0.55 p.u., reactive current rises to 0.4 p.u., and active current drops to 0.1 p.u. Due to increased reactive current and current waveform distortion, CPD-PWM struggles to control midpoint potential stability. In the first cycle, $U_{c1}$ rises to 785.5 V, with a convergence time of 20.5 ms; after three cycles, the peak voltage is 751.2 V, and the grid current shows low-frequency distortion. With DCO-PWM under the same conditions, the fault phase switches to DCO-PWM. In the first cycle, $U_{c1}$ only rises to 732.8 V, with a convergence time of 10.3 ms; after three cycles, the peak voltage is 713.9 V, and the grid current returns to sinusoidal by the second cycle.
In symmetric low-voltage ride-through recovery without DCO-PWM, the grid voltage begins to normalize at 0.4 s. Since phases B and C recover first and phase A recovers later, the grid current is significantly distorted, making it difficult to maintain midpoint voltage balance based on real-time grid current. In the first cycle, $U_{c2}$ rises to 858.1 V, with a convergence time of 27.9 ms; after three cycles, the peak voltage of $U_{c1}$ is 713.5 V. With DCO-PWM under the same conditions, phase-separated short-term switching to DCO-PWM quickly pulls the midpoint potential deviation back. In the first cycle, $U_{c2}$ only rises to 726.4 V, with a convergence time of 3.2 ms; after three cycles, the peak voltage of $U_{c1}$ is 704 V.
In high-voltage ride-through without DCO-PWM, the grid voltage rises to 1.3 p.u. at 0.2 s, reactive current rises to 0.3 p.u., and active current drops to 0.77 p.u. Due to increased reactive current, CPD-PWM’s midpoint control capability slightly decreases, with $U_{c1}$ rising to 718.5 V and a steady-state peak of 714.2 V. With DCO-PWM under the same conditions, phase-separated short-term switching to DCO-PWM results in $U_{c1}$ rising to 714.6 V in the first cycle and a steady-state peak of 713.9 V. The improvement is not significant because the active current proportion is relatively large, and CPD-PWM still has strong midpoint control capability. The improvement effects of DCO-PWM on midpoint potential control are summarized in Table 4.
| Improvement Effect | Reduction in $U_c$ Maximum Value (V) | Reduction in $U_c$ Steady-State Peak (V) | Reduction in Convergence Time (ms) |
|---|---|---|---|
| Asymmetric Low-Voltage Ride-Through | 52.7 | 37.3 | 10.2 |
| Symmetric Low-Voltage Ride-Through Recovery | 131.7 | 9.5 | 24.7 |
| High-Voltage Ride-Through | 3.9 | 0.3 | 0 |
In conclusion, addressing the midpoint potential balance issue in three-level solar inverters during fault ride-through, this paper proposes a novel DCO-PWM improved modulation method based on existing pulse width modulation and midpoint balance methods, according to the grid connection requirements for solar inverters during fault ride-through. From the voltage state space vector level, the influence of medium vectors on the midpoint potential is analyzed. By increasing the depth of carrier phase overlap, a new DCO-PWM improvement modulation method is proposed. Simultaneously, to avoid the increased switching frequency of power devices caused by DCO-PWM, a phase-separated switching method is developed that switches the intermediate phase modulation wave to DCO-PWM when the midpoint potential difference exceeds a set threshold, while CPD-PWM is used for other states. Experimental results verify that this scheme effectively enhances control of grid-connected current and midpoint voltage during low-voltage fault ride-through in three-level solar inverters, ensuring safe and reliable fault state ride-through, with good engineering practical value.