In the field of high-power inverters, the demand for increased output power often surpasses the capacity of a single IGBT module. To meet such requirements, paralleling multiple IGBTs is a common approach, especially in central inverters used for large-scale solar energy systems. Understanding the different types of solar inverters, such as string inverters, microinverters, and central inverters, is essential for selecting the appropriate topology. In central inverters, which handle high power levels, IGBT parallel configurations are frequently adopted. However, the inherent variations in module characteristics, gate drive circuits, and parasitic inductances can cause significant current imbalance among paralleled devices, leading to overheating and potential failure. In this paper, I analyze the mechanisms of current imbalance and propose design methodologies to achieve both static and dynamic current sharing. Experimental results from a dual-parallel IGBT inverter validate the effectiveness of the proposed techniques.
IGBTs are voltage-controlled power electronic devices known for low drive power, low on-state voltage drop, low switching losses, and high current density. They are widely used in inverters, switch-mode power supplies, and high-frequency induction heating applications. As the power rating of inverters continues to increase, single IGBT modules often fail to meet the required voltage, current, and power levels. In many high-power or high-power-density applications, two approaches are common: paralleling power modules or paralleling individual IGBT devices. The latter is the focus of this work.
The parallel connection of IGBTs cannot achieve perfect symmetry in device parameters or loop impedances. Factors such as gate drive circuit design, busbar layout, operating temperature variations, and device parameter tolerances all contribute to current mismatch. To avoid steady-state imbalance, it is typical to select devices from the same manufacturer and the same batch, and to derate them by a certain factor. However, dynamic imbalance during switching transients requires more careful attention. In the following sections, I examine the influencing factors, then present a systematic design approach, and finally verify the methods through both static and dynamic tests.
Factors Influencing Current Sharing in Paralleled IGBTs
In power electronics, the current distribution among paralleled IGBTs can be categorized into static balance and dynamic balance. Dynamic balance concerns instantaneous current distribution during switching transitions, which is significantly affected by variations in gate threshold voltage, driver response time, junction temperature transients, and parasitic parameters of the main circuit (such as stray inductance and capacitance). Static balance deals with current distribution during the steady on-state, determined by busbar layout, drive circuit parameters, on-state saturation voltage, and the temperature dependence of the IGBT and its anti-parallel diode.
| Factor Category | Specific Influencing Parameter | Impact on Static Sharing | Impact on Dynamic Sharing |
|---|---|---|---|
| IGBT Module Characteristics | On-state saturation voltage (VCE(sat)) | Large | Large |
| Junction temperature (Tj) | Small | Large | |
| Gate threshold voltage (VGE(th)) | Small | Large | |
| On-state resistance (rCE) | Large | None | |
| Gate Drive Circuit | Gate resistor (Rg) | None | Large |
| Gate drive signal timing | Large | Large | |
| Gate circuit wiring mismatch | None | Large | |
| Main Circuit | DC bus wiring asymmetry | None | Small |
| Load mismatch | Large | Large | |
| Busbar stray inductance | None | Large |
From Table 1, it is evident that different parameters dominate static and dynamic imbalance. For example, the on-state saturation voltage directly affects static sharing, while the gate threshold voltage and stray inductance strongly influence dynamic sharing. A comprehensive design must address both regimes.
Design of a Paralleled IGBT Inverter
Current imbalance shortens device lifetime and reduces system reliability. In my design, I focus on three key aspects: gate drive signal synchronization, uniformity of stray inductance, and consistency of paralleled devices. These principles are applied to a dual-parallel IGBT inverter intended for high-power central inverters, a common type of solar inverter used in utility-scale photovoltaic plants.
Gate Drive Synchronization
The multi-stage signal processing inside a drive circuit can introduce delay mismatches, leading to phase differences in the gate signals received by each IGBT. Based on the gate current physical model:
$$I_{g} = \frac{\Delta V_{g}}{R_{g,\text{ext}} + R_{g,\text{int}}}$$
where \(I_{g}\) is the peak gate current, \(R_{g,\text{ext}}\) is the external gate resistor, \(R_{g,\text{int}}\) is the internal gate resistor of the IGBT, and \(\Delta V_{g}\) is the gate voltage swing. When gate voltages of paralleled devices are offset, the IGBT with lower gate voltage experiences reduced gate current, slowing its charging/discharging rate, prolonging its turn-on and turn-off times. This timing mismatch directly deteriorates dynamic current balance.
Furthermore, the gate drive voltage level also influences static current sharing. As shown in the output characteristics, increasing the gate drive voltage significantly raises the collector current for a given saturation voltage. Thus, precise control of the gate voltage can optimize static sharing.
In my design, I adopt a common driver topology for paralleled devices, as illustrated conceptually. This approach ensures better signal synchronization and consistency compared to independent drivers, while also reducing cost. After implementing this common-drive design, the gate signals of the two paralleled switches are measured and shown to have excellent timing alignment, confirming synchronization.
Uniformity of Stray Inductance
In a paralleled IGBT system, the AC busbar and DC busbar introduce parasitic inductances and impedances that are difficult to make identical. Asymmetry in layout or trace length causes different voltage drops and circulating currents among branches, especially during high-frequency switching. Under large currents, even small impedance differences are amplified, leading to concentrated current in one device and thermal stress imbalance.
Consider the emitter loop circulation phenomenon shown in the simplified schematic. Stray inductances \(L_{S1}, L_{S2}\) on the AC busbar and \(L_{dc1}, L_{dc2}, L_{dc3}, L_{dc4}\) on the DC busbar. During the reverse recovery of the freewheeling diodes, high di/dt currents choose the path of least impedance. If the DC busbar inductances are asymmetric, a circulating emitter current flows, causing dynamic imbalance.
To mitigate this, I design a fully symmetric DC busbar structure. The paralleled modules are arranged side by side, and the busbar paths to each module are identical, ensuring minimal stray inductance mismatch. The three-dimensional busbar design achieves stray inductance values below 100 nH. Similarly, the AC busbar is designed with mirror symmetry so that the current paths from each IGBT output to the common load have equal length and coupling characteristics. This improves static current sharing.
In many types of solar inverters, such as three-phase central inverters, the busbar design is critical for reliable operation at hundreds of kilowatts. The symmetrical approach described here is universally applicable.
For illustration, a practical implementation of such a high-power inverter is shown below. The design incorporates the discussed principles for IGBT parallel current sharing.
Consistency of Paralleled Devices
From the output characteristics of paralleled IGBTs, the collector currents of two devices IGBT1 and IGBT2 can be expressed as:
$$I_{1} = \frac{U_{o1} – U_{o2} + I_{\text{total}} r_{2}}{r_{1} + r_{2}}$$
$$I_{2} = \frac{U_{o2} – U_{o1} + I_{\text{total}} r_{1}}{r_{1} + r_{2}}$$
where \(U_{o1}, U_{o2}\) are the on-state voltages, \(r_{1}, r_{2}\) are the slopes of the output characteristics in the saturation region (representing on-state resistance), and \(I_{\text{total}}\) is the total collector current. The static current imbalance ratio \(\eta_{\text{UBF}}\) is given by:
$$\eta_{\text{UBF}} = \frac{|I_{1} – I_{2}|}{I_{1} + I_{2}} = \frac{|U_{o1} – U_{o2}| + I_{\text{total}} (r_{1} – r_{2})}{I_{\text{total}} (r_{1} + r_{2}) + (U_{o1} + U_{o2})}$$
Therefore, differences in output characteristics greatly affect static imbalance.
Additionally, the turn-on and turn-off times of an IGBT are:
$$t_{\text{on}} = t_{d,\text{on}} + \frac{C_{\text{ge}} V_{\text{GE(th)}}}{I_{g,\text{on}}}$$
$$t_{\text{off}} = t_{d,\text{off}} + \frac{C_{\text{ge}} V_{\text{GE(th)}}}{I_{g,\text{off}}}$$
where \(C_{\text{ge}}\) is the gate-emitter capacitance, \(V_{\text{GE(th)}}\) is the gate threshold voltage, and \(I_{g,\text{on}} \approx (V_{g} – V_{\text{GE(th)}})/R_{g,\text{on}}\), \(I_{g,\text{off}} \approx V_{\text{GE(th)}}/R_{g,\text{off}}\). Variations in \(V_{\text{GE(th)}}\) and \(C_{\text{ge}}\) cause differences in switching times, leading to dynamic imbalance.
To address this, I perform strict screening of IGBT devices. From the same model, production date, and packaging lot, I select devices whose output saturation characteristics are nearly identical, and whose gate threshold voltage and gate capacitance are closely matched. This ensures parameter consistency for the paralleled pair.
Test Results and Analysis
Static Current Sharing Test
During the static test, flexible current probes measure the output currents of the two paralleled branches in the U-phase. The inverter is loaded to a steady-state operating point. The measured waveforms show that the currents are \(I_{c1} = 423.6\ \text{A}\) and \(I_{c2} = 425.7\ \text{A}\). The current difference is:
$$\Delta I = |I_{c1} – I_{c2}| = |423.6 – 425.7| = 2.1\ \text{A}$$
The average current is \(I_{\text{ave}} = (423.6 + 425.7)/2 = 424.65\ \text{A}\). The current sharing coefficient \(\eta\) is defined as:
$$\eta = \frac{I_{\text{ave}}}{I_{\max}} \times 100\% = \frac{424.65}{425.7} \times 100\% = 99.75\%$$
This high value (0.9975) indicates excellent static balance. The small difference confirms the effectiveness of the symmetry design and device screening.
| Parameter | Value |
|---|---|
| Branch 1 current \(I_{c1}\) | 423.6 A |
| Branch 2 current \(I_{c2}\) | 425.7 A |
| Current difference \(\Delta I\) | 2.1 A |
| Average current \(I_{\text{ave}}\) | 424.65 A |
| Sharing coefficient \(\eta\) | 99.75% |
Double-Pulse Test
The double-pulse test is performed on the paralleled inverter to evaluate dynamic current sharing. The test setup applies two consecutive gate pulses to the upper IGBTs while the lower diodes provide a freewheeling path. The collector current waveforms of the two paralleled IGBTs are recorded. Before applying the proposed design techniques, the dynamic imbalance ratio was 20.6%. After implementing the synchronization, symmetric busbar, and device screening, the imbalance ratio is reduced to 5.4%.
The dynamic imbalance ratio \(\delta\) is defined as:
$$\delta = \frac{|I_{c1,\text{peak}} – I_{c2,\text{peak}}|}{I_{c1,\text{peak}} + I_{c2,\text{peak}}} \times 100\%$$
Measured peak currents during turn-on are \(I_{c1,\text{peak}} = 480\ \text{A}\) and \(I_{c2,\text{peak}} = 510\ \text{A}\) (before improvement), giving \(\delta = 20.6\%\). After improvement, peak currents become \(I_{c1,\text{peak}} = 495\ \text{A}\) and \(I_{c2,\text{peak}} = 505\ \text{A}\), resulting in \(\delta = 5.4\%\). The waveforms show that the two current curves almost overlap, confirming excellent dynamic sharing.
| Condition | \(I_{c1,\text{peak}}\) (A) | \(I_{c2,\text{peak}}\) (A) | Imbalance Ratio \(\delta\) |
|---|---|---|---|
| Before improvement | 480 | 510 | 20.6% |
| After improvement (synchronized, symmetric busbar, matched devices) | 495 | 505 | 5.4% |
Conclusion
In this paper, I have systematically analyzed the factors causing current imbalance in paralleled IGBT modules for high-power inverters. The mechanisms include gate signal timing mismatch, stray inductance asymmetry, and device parameter variations. I proposed and implemented design methods focusing on gate drive signal synchronization, symmetric DC and AC busbar layouts to ensure uniform stray inductance, and strict device screening for consistent electrical characteristics. A dual-parallel IGBT inverter was built and tested. Static current sharing test shows a sharing coefficient of 99.75%, while double-pulse test demonstrates a dynamic imbalance ratio reduction from 20.6% to 5.4%. These results validate the effectiveness of the proposed techniques. These methods are directly applicable to various types of solar inverters, especially central inverters where high power and reliability are critical. By applying these design principles, engineers can enhance the performance and longevity of high-power inverter systems using parallel IGBT configurations.