The evolution of energy storage systems is increasingly driven by demands for higher capacity and power density. In this context, liquid-cooled solutions have emerged as a dominant trend, offering superior cooling efficiency, reduced energy consumption, and more compact footprints compared to traditional air-cooled systems. However, the liquid-cooling paradigm introduces significant engineering challenges. Liquid-cooled battery packs (PACKs) integrate a substantially larger number of energy storage cells within a single module, leading to higher system voltages and greater complexity in monitoring and control. This places elevated demands on the Battery Management System (BMS), which must ensure precise data acquisition from every individual energy storage cell, execute coordinated system-wide control, and facilitate straightforward operational maintenance. This article presents the design and implementation of a hierarchical BMS specifically engineered for a liquid-cooling integrated energy storage system. The system architecture, communication network, and hardware design of its key management units are detailed. A particular focus is placed on the critical challenge of cell balancing within high-density PACKs, where a comparative analysis of passive equalization topologies is conducted. The implemented solution, featuring an external MOSFET-based passive equalizer, effectively mitigates cell voltage divergence, thereby reducing manual maintenance interventions and prolonging the operational life of the energy storage cells. The practical deployment and successful operational data from a real-world application validate the system’s design and functionality.
System Architecture and Communication Design
The proposed liquid-cooling integrated energy storage system is designed as a self-contained unit, consolidating key components into a single, manageable enclosure. As illustrated in the system block diagram, the core assembly integrates the Power Conversion System (PCS), a high-voltage control box, the liquid cooling system, the fire protection system, and eight liquid-cooled battery PACKs. Each PACK is equipped with a dedicated PACK Management Unit (PMU), while the high-voltage control box hosts the central Control Unit (CU), which acts as the system’s supervisory brain.
The communication architecture of the BMS is structured as a two-layer network, essential for managing the vast amount of data from the multitude of energy storage cells. The foundational layer connects all PMUs to the CU. The PMUs are daisy-chained using Ethernet cabling to form a redundant dual-ring network. This robust topology ensures communication reliability; the first and last PMU nodes in the chain are directly connected to the CU, completing the ring and providing a backup path in case of a single link failure. This network is responsible for aggregating all cell-level data—voltages and temperatures of each energy storage cell—and transmitting them to the CU.
The second, supervisory layer involves the CU’s communication with external subsystems. The CU interfaces directly with the PCS via a high-speed GOOSE (Generic Object Oriented Substation Event) link for fast, synchronized control commands. Communication with the fire protection system is established through a CAN bus interface, enabling rapid alarm reception and response. The liquid cooling system is managed via an RS-485 serial link, allowing the CU to send temperature setpoints and receive operational status. For system access and maintenance, the CU provides both a standard Ethernet port for client software (e.g., SCADA systems) and a Bluetooth interface for direct mobile application connectivity, offering technicians a versatile tool for monitoring and diagnostics. This layered approach ensures segregated, reliable data flow from individual energy storage cells to the central controller and onward to peripheral systems.
Hardware Design of Management Units
The hardware realization of the BMS is built upon the two-tiered architecture, comprising the PACK Management Units at the cell level and the central Control Unit at the system level.
PACK Management Unit (PMU)
A single liquid-cooled PACK houses a significantly greater quantity of energy storage cells (e.g., 52 cells) compared to typical air-cooled modules. Consequently, each PMU is designed as a high-channel-count data acquisition and balancing node. Its primary functions include:
- Cell Voltage Monitoring: Simultaneous sampling of the voltage across every individual energy storage cell within the PACK.
- Temperature Monitoring: Distributed temperature sensing across multiple points on the energy storage cells and within the module to enable precise thermal management.
- Passive Cell Balancing: Implementing controlled discharge paths for cells with higher state-of-charge to improve pack uniformity.
A key design philosophy for the PMU is its role as a “dumb” slave unit. It contains no high-level application logic or requires individual address configuration. All its operational parameters, sampling routines, and balancing commands are dictated by the central Control Unit. This simplifies deployment and maintenance, as PMUs are interchangeable, and firmware updates or configuration changes are centralized at the CU level.
Control Unit (CU)
The Control Unit is the computational and coordination hub. It performs several critical functions:
- Data Aggregation & State Estimation: It receives raw data from all PMUs, calculates Pack State-of-Charge (SOC), State-of-Health (SOH), and monitors for any abnormalities at the cell or module level.
- System-Level Monitoring: It directly measures total system voltage, string current (via a shunt in the high-voltage box), and overall pack voltages.
- Subsystem Coordination: Based on the aggregated temperature data from the energy storage cells, it sends control signals to the liquid cooling system. It processes alarms from the fire protection system and can command the PCS to shut down in an emergency.
- Human-Machine Interface (HMI): It hosts communication interfaces (Ethernet, Bluetooth) for external access, providing a gateway for system data visualization and parameter setting.
High-Voltage Control Box Integration
The high-voltage control box physically and electrically integrates the system. Its power circuit connects the battery string to the PCS, protected by high-current fuses on both the positive and negative busbars. The shunt for current measurement is located here. The box also houses the CU, an Ethernet switch for network communication, cooling fans, and a power supply for the electronics. This integrated design ensures a clean separation between power and control circuits while keeping all critical control hardware in a single, accessible location.
Implementation of Key Function: Cell Equalization Management
Maintaining uniformity among a large population of energy storage cells is paramount for maximizing the usable capacity, longevity, and safety of the battery system. In a liquid-cooled PACK with over 50 cells in series, the overall pack capacity is constrained by the weakest energy storage cell. Without equalization, diverging cell voltages lead to under-utilization (early termination of charge/discharge) and can necessitate frequent, labor-intensive manual maintenance to rebalance individual cells.
Equalization strategies are broadly categorized into passive (dissipative) and active (non-dissipative) methods. While active balancing transfers energy from higher-charged to lower-charged cells, it involves complex circuitry, higher cost, and potential reliability concerns due to the increased number of components. Given the scale and cost-sensitivity of grid-scale energy storage, a robust and cost-effective passive balancing solution is often preferred.
Passive equalization works by selectively dissipating excess energy from higher-voltage energy storage cells through resistive paths until all cells reach a similar voltage level. The design of the balancing circuit is crucial for its effectiveness and reliability. The following analysis compares common topologies, primarily distinguished by the placement of the switching element (MOSFET).
Analysis of Passive Equalization Topologies
Common integrated circuit (Analog Front-End or AFE) solutions for cell monitoring offer built-in balancing options with inherent trade-offs.
| Topology | Schematic Principle | Balancing Current (Ib) | Key Characteristics & Limitations |
|---|---|---|---|
| Built-in MOSFET – Type 1 (e.g., ADI LTC681x) |
Cell → Internal MOSFET → Internal Resistor (Rsi) → Filter Resistor (Rci) → Cell | $$I_b = \frac{V_c}{R_{si} + R_{ci}}$$ | Balancing current flows through the filter resistor Rci. A large Rci (for noise immunity) severely limits Ib, resulting in slow, inefficient balancing. |
| Built-in MOSFET – Type 2 (e.g., NXP MC3377x) |
Cell → Internal MOSFET → Internal Resistor (Rsi) → Cell | $$I_b = \frac{V_c}{R_{si}}$$ | Current path avoids the filter network. However, the full balancing current flows through the IC’s silicon, leading to significant internal heating which is difficult to dissipate, potentially limiting the sustainable balancing current and affecting measurement accuracy. |
| Built-in MOSFET – Type 3 (e.g., TI BQ7961x) |
Cell → Internal MOSFET → Internal Resistor (Rsi) → Adjacent Channel’s Resistor (Rsi) → Adjacent Cell | $$I_b = \frac{V_c}{2R_{si}}$$ | Requires coordinated switching of adjacent even/odd channel pairs. Can lead to very high current through the internal MOSFETs when adjacent channels are balanced simultaneously, exacerbating internal heating issues and imposing complex control sequencing. |
| External MOSFET Topology (Proposed Design) |
Cell → External MOSFET → External Resistor (Rse) → Cell | $$I_b = \frac{V_c}{R_{se}}$$ | The balancing switch and power dissipation are moved entirely outside the sensitive AFE chip. The balancing current is independent of the filter network. Design parameters (Rse, MOSFET) can be freely selected for the desired balancing current and thermal management. The filter resistor Rce can be optimized for noise rejection without impacting balancing performance. |
Design Choice: External MOSFET-Based Equalizer
To overcome the limitations of integrated balancing solutions—particularly thermal stress on the AFE IC and constrained balancing current—the proposed BMS employs an external MOSFET topology. In this design, the AFE chip’s balancing output pin is used to drive the gate of an external, discrete N-channel MOSFET via a current-limiting resistor Re. When activated, a controlled discharge path is created from the higher-voltage energy storage cell through this external MOSFET and a power resistor Rse.
The advantages are significant:
- Thermal Management: The heat generated by the balancing current (Ib2Rse) is dissipated in the external power resistor, which can be physically sized and placed for effective cooling, preventing heat from affecting the precision measurement circuitry of the AFE.
- Flexibility and Performance: The value of Rse and the selection of the MOSFET can be tailored to achieve an optimal balancing current (e.g., 100-300 mA), balancing speed against power dissipation.
- Improved Robustness: The sensitive analog measurement paths are decoupled from the power dissipation paths, allowing for stronger filtering (Rce, Ce) against electromagnetic interference without compromising equalizer functionality.
The control logic, executed by the CU, continuously monitors the voltage of each energy storage cell. If the voltage of a particular cell exceeds the average pack voltage by a set threshold, the CU commands the corresponding PMU to activate its external MOSFET balancing circuit for that cell. This process continues until cell voltages converge, thereby maximizing the usable capacity of the entire string of energy storage cells and eliminating the need for routine manual rebalancing.
System Application and Operational Validation
The designed liquid-cooling integrated energy storage system with its advanced BMS has been successfully deployed in an industrial peak-shaving application. The system charges during periods of low grid electricity demand (valley hours) and discharges during high-demand, high-cost peak hours, providing significant economic savings for the facility.
During operation, the BMS reliably manages the charge and discharge cycles. The CU is configured with voltage limits for the energy storage cells, such as an upper charge limit of 3.65 V and a lower discharge limit of 2.9 V per cell. Data logs from a complete cycle—comprising full charge, rest, full discharge, and another rest period—were extracted from the system’s memory.
The following formula governs the fundamental relationship during balancing for our chosen topology, as implemented on each energy storage cell channel:
$$I_{b} = \frac{V_{cell}}{R_{se}}$$
Where \(I_{b}\) is the balancing current, \(V_{cell}\) is the voltage of the specific energy storage cell being balanced, and \(R_{se}\) is the value of the external balancing resistor.
Analysis of the voltage data from one representative PACK (containing 52 energy storage cells) over a full cycle demonstrates excellent performance. The voltage trajectories of all 52 cells show tight tracking and consistent behavior throughout the charge and discharge phases. The minimal divergence between cell voltages is a direct result of the effective operation of the passive equalization system. This validation confirms that the BMS design successfully maintains the health and performance of the dense population of energy storage cells within the liquid-cooled PACK, ensuring reliable and efficient system operation in a real-world scenario. The integration of the robust external MOSFET balancing circuit has proven essential in managing the consistency of such a large series-connected string of energy storage cells.
Conclusion
This article has detailed the design of a comprehensive battery management system for a liquid-cooling integrated energy storage platform. The system addresses the core challenges of managing high-density battery packs through a hierarchical two-layer architecture comprising intelligent PACK Management Units and a central Control Unit. A sophisticated communication network ensures reliable data flow and system coordination. The hardware design emphasizes simplicity at the node level and intelligence at the system level, facilitating easier maintenance. A critical contribution is the in-depth analysis and implementation of a passive cell equalization strategy. By opting for an external MOSFET-based topology over common integrated solutions, the design achieves an optimal balance of performance, thermal management, reliability, and cost—a crucial consideration for large-scale energy storage. The successful field deployment and the resulting operational data, showing well-regulated voltage profiles across all energy storage cells, conclusively validate the system’s design principles and its effectiveness in enhancing the performance and operational lifespan of liquid-cooled energy storage systems.