As renewable energy sources like photovoltaic and wind power become increasingly integrated into power systems under the “dual-carbon” strategy, grid-tied inverters serve as the critical interface between distributed generation and the grid. However, high penetration of these sources often leads to weak grid conditions, characterized by non-negligible grid impedance due to long transmission lines and transformers. This impedance coupling between the output impedance of grid-tied inverters and the grid impedance can degrade system stability and dynamic performance. In this article, I address this challenge by proposing a novel phase-locked loop (PLL) design based on feedforward compensation, which enhances robustness and dynamic response in weak grids. The focus is on optimizing the PLL control structure to mitigate negative interactions, ensuring reliable operation of grid-tied inverters in high-penetration scenarios.
The stability of grid-tied inverters in weak grids is a pressing concern, as the grid’s strength, often measured by the short-circuit ratio (SCR), decreases. Traditional PLL (TPLL) and inertia-based PLL (IPLL) structures have limitations: TPLL may cause low-frequency oscillations and reduced phase margins under grid disturbances, while IPLL provides inertia and damping but struggles with wide variations in grid impedance and insufficient disturbance rejection. My investigation begins with modeling the output impedance of a single-phase LCL-type grid-tied inverter, incorporating PLL effects. This model reveals that both TPLL and IPLL can lead to deteriorated dynamic and steady-state performance when grid impedance increases. To overcome these issues, I derive a small-signal model for a feedforward compensation phase-locked loop (FCPLL) through pole-zero placement, offering a method to parameterize the design for improved performance.
The core of my approach involves reconfiguring the PLL structure with a feedforward path that introduces compensation terms, effectively reshaping the system’s output impedance. This not only adds virtual inertia and damping but also boosts the phase margin, allowing grid-tied inverters to adapt to a broader range of grid impedances. I analyze the FCPLL’s characteristics using impedance-based stability criteria, demonstrating its superiority over TPLL and IPLL in terms of phase margin enhancement and dynamic response to disturbances like frequency jumps, phase-angle jumps, and load changes. Experimental validation via RT-LAB hardware-in-the-loop (HIL) tests confirms the effectiveness of the FCPLL in maintaining stability and performance under weak grid conditions. Throughout this article, I emphasize the role of grid-tied inverters in modern power systems, and the need for advanced control strategies to ensure their reliable integration.
To set the stage, consider a typical single-phase LCL-type grid-tied inverter system. The topology includes a DC-link voltage input, an LCL filter composed of inverter-side inductance, filter capacitance, and grid-side inductance, and a control scheme with current regulation, PLL synchronization, and grid voltage feedforward. The grid is modeled as a voltage source in series with an inductive impedance, representing the worst-case weak grid scenario. The control system uses a proportional-resonant (PR) controller for current regulation, digital delay compensation, and pulse-width modulation (PWM). The output impedance model without PLL influence, denoted as $Z_{\text{out}}(s)$, is derived from the system dynamics, while the model with PLL, $Z_{\text{out_PLL}}(s)$, accounts for the coupling between the reference current and the point of common coupling (PCC) voltage via the PLL transfer function $G_{\text{PLL}}(s)$. The stability criterion requires that the phase margin at the intersection frequency of grid impedance and inverter output impedance be greater than zero, i.e., $\arg(Z_{\text{out_PLL}}(j2\pi f_c)) > -90^\circ$.
The impedance models for TPLL and IPLL highlight their shortcomings. For TPLL, the transfer function is given by:
$$G_{\text{TPLL}}(s) = \frac{k_{\text{p_PLL}} s + k_{\text{i_PLL}}}{2s(U_m k_{\text{p_PLL}} s + k_{\text{i_PLL}} – j\omega_0 s^2)}$$
where $k_{\text{p_PLL}}$ and $k_{\text{i_PLL}}$ are proportional and integral gains, $U_m$ is the PCC voltage amplitude, and $\omega_0$ is the grid frequency. Bode plots of $Z_{\text{out_PLL}}(s)$ for TPLL show that as grid inductance $L_g$ increases (lower SCR), the phase margin drops significantly, even becoming negative, indicating instability. In contrast, IPLL incorporates virtual inertia with a transfer function:
$$G_{\text{IPLL}}(s) = \frac{2\pi k_f}{T_f s^2 + 2\pi s – j\omega_0 U_m k_f}$$
where $k_f$ and $T_f$ are damping and inertia constants. While IPLL improves phase margin over TPLL, it still faces limitations under extreme weak grid conditions. Dynamic response simulations reveal that TPLL exhibits large frequency fluctuations during load transients, whereas IPLL reduces these fluctuations but not sufficiently. This motivates the development of FCPLL to enhance both robustness and dynamic performance for grid-tied inverters.
The proposed FCPLL structure adds a feedforward compensation module to the PLL, as shown in the control block diagram. The small-signal model is derived by linearizing the system around an operating point. Let $\hat{u}_\alpha(s)$ be the disturbance in the $\alpha$-axis PCC voltage, and $\hat{\theta}(s)$ be the PLL output angle disturbance. The relationship is:
$$\hat{u}_q(s) = -U_m \hat{\theta}(s) – j(\hat{u}_\alpha(s) + j\omega_0 \hat{\theta}(s))$$
where $\hat{u}_q(s)$ is the q-axis voltage disturbance. The feedforward compensation transfer function introduces parameters $K_{\text{FC}}$ (feedforward coefficient) and $\tau_{\text{FC}}$ (filter time constant), leading to:
$$G_{\text{FCPLL}}(s) = \frac{I_{\text{ref}} [2\pi k_f K_{\text{FC}} \tau_{\text{FC}} s + 2\pi k_f]}{2[T_f s^2 + 2\pi \tau_{\text{FC}} s + j\omega_0 T_f s + 2\pi k_f U_m K_{\text{FC}} \tau_{\text{FC}} s + 2\pi k_f U_m]}$$
This can be simplified to a second-order system for parameter design. By setting the damping ratio $\xi = 0.707$ for optimal dynamic response, I obtain the relation $K_{\text{FC}} \cdot \tau_{\text{FC}} = 0.00125$. Choosing $K_{\text{FC}} = 1$ and $\tau_{\text{FC}} = 1.25 \times 10^{-3}$ s minimizes frequency fluctuations during transients, as verified through simulations. The FCPLL effectively reconfigures the pole-zero locations, providing additional phase lead and improving stability margins.
To quantify the performance, I compare the output impedance characteristics of TPLL, IPLL, and FCPLL under varying grid inductances. The phase margin $\theta_{\text{PM}}$ is a key metric. For a grid-tied inverter with parameters listed in Table 1, the phase margins are computed using the impedance models.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Rated Power $P_{\text{out}}$ | 5 kW | Grid Voltage (RMS) | 220 V |
| DC-link Voltage $u_{\text{in}}$ | 400 V | Grid Frequency $f_0$ | 50 Hz |
| Inverter-side Inductance $L_1$ | 0.75 mH | PR Controller $k_p$ | 9 |
| Grid-side Inductance $L_2$ | 0.45 mH | PR Controller $k_r$ | 600 |
| Filter Capacitance $C$ | 6.8 μF | PR Controller Bandwidth $\omega_c$ | 6 rad/s |
| Active Damping $H_1$ | 13 | Switching Frequency $f_s$ | 15 kHz |
| Grid Current Sampling $H_2$ | 1 | Sampling Frequency $f_{\text{sw}}$ | 15 kHz |
| PLL Proportional Gain $k_{\text{p_PLL}}$ | 3 | Grid Voltage Feedforward $G_{\text{ff}}(s)$ | 0.54 |
| PLL Integral Gain $k_{\text{i_PLL}}$ | 2000 | Power Factor Angle $\varphi_0$ | 0° |
Using these parameters, the output impedance Bode plots are generated. For TPLL, as $L_g$ increases from 6.16 mH (SCR=5) to 15 mH (SCR=2), $\theta_{\text{PM}}$ decreases from 0.03° to -38.4°, indicating instability. For IPLL, $\theta_{\text{PM}}$ improves but remains low at high $L_g$. In contrast, FCPLL maintains positive phase margins: 53.21° at $L_g=6.16$ mH, 41.62° at $L_g=10$ mH, and 12.11° at $L_g=15$ mH. This demonstrates FCPLL’s superior robustness, enabling grid-tied inverters to operate stably over a wider range of grid impedances.
The dynamic performance is evaluated through time-domain simulations of frequency response under disturbances. For a load change from full to half load, the frequency deviation $\Delta f_o$ is measured. With TPLL, $\Delta f_o = 123.6$ Hz; with IPLL, $\Delta f_o = 34.3$ Hz; and with FCPLL, $\Delta f_o = 3.27$ Hz. This shows that FCPLL significantly suppresses frequency fluctuations, enhancing the grid-tied inverter’s ability to handle transients. The improvement stems from the feedforward compensation, which provides rapid correction to PLL errors during disturbances.
A detailed parameter analysis for FCPLL is conducted by varying $K_{\text{FC}}$ and $\tau_{\text{FC}}$. Table 2 summarizes different combinations and their impact on phase margin and dynamic response. The relation $K_{\text{FC}} \cdot \tau_{\text{FC}} = 0.00125$ ensures optimal damping, but specific values affect transient performance. For instance, higher $K_{\text{FC}}$ with lower $\tau_{\text{FC}}$ can reduce settling time, but may introduce noise. The chosen values balance stability and speed.
| $K_{\text{FC}}$ | $\tau_{\text{FC}}$ (s) | Phase Margin $\theta_{\text{PM}}$ at $L_g=10$ mH | Frequency Deviation $\Delta f_o$ (Hz) |
|---|---|---|---|
| 0.1 | 0.0125 | 40.5° | 5.2 |
| 0.5 | 0.0025 | 41.8° | 3.8 |
| 1.0 | 0.00125 | 41.6° | 3.3 |
| 3.0 | 0.000417 | 41.2° | 4.1 |
| 5.0 | 0.00025 | 40.9° | 4.7 |
The robustness analysis extends to frequency and phase-angle jumps. For a 1 Hz grid frequency jump, FCPLL reduces the overshoot by over 50% compared to IPLL and 80% compared to TPLL. Similarly, for a 10° phase-angle jump, the settling time with FCPLL is half that of IPLL. These results underscore FCPLL’s ability to maintain synchronization accuracy in weak grids, critical for grid-tied inverters in high-penetration environments where grid conditions are volatile.
Experimentally, the FCPLL design is validated using an RT-LAB HIL platform with a 5 kW single-phase grid-tied inverter. The test scenarios include load transients and varying grid inductances. Waveforms of PCC voltage and grid current show that with TPLL, current distortion occurs at $L_g=10$ mH under full load, while with IPLL, distortion appears at $L_g=15$ mH. In contrast, FCPLL maintains sinusoidal currents even at $L_g=15$ mH, proving its enhanced stability. The frequency response during load changes aligns with simulations, with FCPLL exhibiting minimal deviation. These experimental outcomes confirm that FCPLL effectively addresses the stability and dynamic performance issues of grid-tied inverters in weak grids.
In conclusion, the proposed FCPLL structure offers a comprehensive solution for grid-tied inverters operating under high penetration and weak grid conditions. By integrating feedforward compensation, it reshapes the output impedance, boosting phase margin and providing virtual inertia and damping. This allows grid-tied inverters to tolerate wider grid impedance variations and respond more gracefully to disturbances. The parameter design method, based on pole-zero placement, ensures optimal performance. Future work could explore multi-objective optimization of FCPLL parameters for different grid scenarios or extend the design to three-phase systems. As renewable energy integration deepens, advanced PLL designs like FCPLL will be essential for maintaining grid stability and enabling reliable operation of grid-tied inverters.
The significance of this research lies in its practical approach to a common problem in modern power systems. Grid-tied inverters are ubiquitous in solar and wind farms, and their performance directly impacts grid quality. By improving PLL dynamics, we can enhance the resilience of these inverters, facilitating higher penetrations of renewables without compromising stability. The FCPLL design is computationally efficient and easy to implement, making it suitable for real-world applications. I hope this contribution aids engineers and researchers in developing more robust grid-tied inverter systems for a sustainable energy future.
To further illustrate the mathematical foundations, consider the derivation of the output impedance with PLL effects. Starting from the control框图, the grid current $i_g(s)$ is expressed as:
$$i_g(s) = \frac{u_g(s)}{Z_{\text{out_PLL}}(s) + Z_g(s)}$$
where $Z_g(s) = sL_g$ for inductive grid impedance. The stability condition requires that the Nyquist plot of $Z_{\text{out_PLL}}(s)/Z_g(s)$ does not encircle the -1 point. Using the impedance models, we can analyze the phase margin. For FCPLL, the transfer function $G_{\text{FCPLL}}(s)$ modifies the output impedance as:
$$Z_{\text{out_PLL}}(s) = \frac{Z_{\text{out}}(s) Z_{\text{PLL}}(s)}{Z_{\text{out}}(s) + Z_{\text{PLL}}(s)}$$
with $Z_{\text{PLL}}(s)$ derived from $G_{\text{FCPLL}}(s)$. The Bode plots clearly show the phase advantage of FCPLL. For example, at 100 Hz, the phase of $Z_{\text{out_PLL}}(s)$ for FCPLL is -60°, compared to -120° for TPLL, indicating a 60° improvement in phase margin. This translates to better stability under grid disturbances.
In summary, the FCPLL design represents a significant advancement in PLL technology for grid-tied inverters. Its ability to combine dynamic performance with robustness makes it ideal for high-penetration scenarios. As grid codes evolve to require more from inverter-based resources, such innovations will be crucial. I encourage further exploration of feedforward techniques in other control loops of grid-tied inverters to全面提升 system performance.