In this article, I present an energy storage battery grouping topology that integrates multi-level AC output with dynamic active balancing. My starting point is a practical challenge: an energy storage battery pack outputs direct current, but many applications require alternating current. In a conventional solution, the energy storage battery pack must be connected to an independent inverter. This inverter increases cost, volume, switching losses, and control complexity. I propose a different approach. I use the dynamic series connection of the energy storage battery group itself to create a staircase voltage waveform. At the same time, I reuse the same power switches and inductors to implement active balancing. Therefore, the energy storage battery group can supply an AC load without a separate inverter.
Keywords: energy storage battery; multi-level AC output; dynamic series connection; active balancing; pulse width modulation.
Introduction
The energy storage battery has become a key component in renewable-energy integration, grid regulation, and industrial power backup. The energy storage battery is usually arranged as a series string to reach a high DC bus voltage. To supply an AC load, a DC-AC converter is normally inserted between the battery and the load. In large installations, the converter is often a modular multilevel converter because it can scale to high voltage and provide distributed energy storage. However, the modular multilevel converter requires many submodules, sensors, and communication links. The cost of such a system is significant. Another solution is a centralized multi-level inverter, but such an inverter often has capacitor-balancing problems. The energy storage battery itself may also need an additional equalization circuit. This leads to two separate control systems: one for AC output and one for balancing. The system becomes complicated and less efficient.
There is an interesting alternative called dynamic series connection. In this approach, the battery pack can be divided into subpacks. Power switches connect different numbers of subpacks in series at different times. In this way, the output voltage is a staircase approximation of a sine wave. The method uses pulse-amplitude-modulation logic. It can avoid the need for a dedicated inverter. However, it introduces a serious imbalance problem. Different subpacks are connected for different durations. The subpack that remains connected for the longest duration supplies more charge to the load. The subpack that is connected only near the peak supplies much less charge. As a result, the state of charge of each energy storage battery subpack diverges quickly. Traditional balancing methods are difficult to apply because the output voltage level changes during the grid cycle.
I therefore propose an energy storage battery grouping scheme in which the balancing action is synchronized with the output level. The key idea is to use the interval when a subpack is included in a staircase level to perform inductive charge transfer. The same switch that creates the output step is used to connect the balancing inductor. Thus, the AC output and active balancing are not two separate functions. They are two sides of the same switching logic. In the following sections, I explain the topology, derive the PWM duty requirement, compare the solution with a cascaded multi-level system, and verify the method with simulation and experiments.
Topology for Multi-Level AC Output
The proposed topology is based on a symmetrical grouping of the energy storage battery. I define \(N\) positive-side subpacks with voltages \(u_{1p}, u_{2p}, \ldots, u_{Np}\) and \(N\) negative-side subpacks with voltages \(u_{1n}, u_{2n}, \ldots, u_{Nn}\). The positive side is used to generate the positive half-cycle of the AC voltage. The negative side is used to generate the negative half-cycle. Each subpack is connected to a set of power switches and an inductor. The inductor stores energy during the balancing action and helps the output filter to smooth the current.
I define the AC output voltage as the difference between the positive terminal voltage \(u_P\) and the negative terminal voltage \(u_N\):
\[
u_{AC}=u_P-u_N
\]
During the positive half-cycle, the negative-side subpacks are bypassed. Therefore, \(u_N=0\), and the output voltage is equal to the voltage formed by the selected positive-side subpacks. The positive half-cycle is divided into angular intervals. Near the zero crossing, only one subpack is used. As the reference voltage increases, more subpacks are inserted in series. Near the peak, all \(N\) positive subpacks are in series.
I use a sinusoidal reference with amplitude \(U_{AC}\) and angular frequency \(\omega\). The duration of the interval that uses \(N-j+1\) subpacks in series is determined by the volt-second balance between the staircase step and the sine reference. For \(j=1,2,\ldots,N\), the \(j\)-th interval is:
\[
\Delta t_j =
\frac{\displaystyle\int_{(N-j)\pi/(2N)}^{(N-j+1)\pi/(2N)} U_{AC}\sin\theta\,d\theta}
{\displaystyle\sum_{i=j}^{N}u_{ip}}
\]
This expression can also be written in closed form:
\[
\Delta t_j =
\frac{U_{AC}}{\displaystyle\sum_{i=j}^{N}u_{ip}}
\left[
\cos\left(\frac{(N-j)\pi}{2N}\right)
–
\cos\left(\frac{(N-j+1)\pi}{2N}\right)
\right]
\]
In the first interval near the zero crossing, only \(u_{Np}\) is active. In the next interval, \(u_{N-1,p}+u_{Np}\) is active. At the peak, \(u_{1p}+u_{2p}+\cdots+u_{Np}\) is active. The sequence is reversed in the second quarter of the positive half-cycle. Therefore, the same \(\Delta t_j\) appears twice in every positive half-cycle. The negative half-cycle is produced by the negative-side subpacks in exactly the same way.
This staircase output is a form of pulse amplitude modulation. The number of output levels is \(2N\), because the AC voltage has \(N\) positive levels and \(N\) negative levels. The staircase voltage approximates a sine wave with small low-order harmonics. The harmonics can be reduced further by a small output filter or by increasing \(N\).
The main problem is that the subpacks have different conduction times. Table 1 summarizes the output voltage level, the corresponding angular interval, the duration, and the SOC decrease magnitude of each positive-side subpack in a quarter cycle.
| Output voltage level | Angle interval | Duration | SOC decrease magnitude |
|---|---|---|---|
| \(\sum_{i=1}^{N}u_{ip}\) | \([(N-1)\pi/(2N),\pi/2)\) | \(\Delta t_1\) | \(\Delta SOC_{u_1}\) |
| \(\sum_{i=2}^{N}u_{ip}\) | \([(N-2)\pi/(2N),(N-1)\pi/(2N))\) | \(\Delta t_2\) | \(\Delta SOC_{u_2}\) |
| \(\vdots\) | \(\vdots\) | \(\vdots\) | \(\vdots\) |
| \(\sum_{i=N-1}^{N}u_{ip}\) | \([\pi/(2N),\pi/N)\) | \(\Delta t_{N-1}\) | \(\Delta SOC_{u_{N-1}}\) |
| \(u_{Np}\) | \([0,\pi/(2N))\) | \(\Delta t_N\) | \(\Delta SOC_{u_N}\) |
If the load current is sinusoidal and in phase with the voltage, the SOC decrease magnitude can be estimated as:
\[
\Delta SOC_{u_j} =
\frac{1}{C_{bat}}
\int_{(N-j)\pi/(2N)}^{(N-j+1)\pi/(2N)}
I_{AC}\sin\theta\,d\theta
\]
Here, \(I_{AC}\) is the amplitude of the AC load current, and \(C_{bat}\) is the nominal capacity of the energy storage battery subpack expressed in coulombs. From the angular intervals, it is clear that \(u_{Np}\) is active in every interval. Therefore, \(u_{Np}\) has the largest SOC decrease. Meanwhile, \(u_{1p}\) is active only near the peak, so it has the smallest SOC decrease. This operating difference will make the energy storage battery become unbalanced even if all cells are initially identical.
AC Output and Balancing Synchronized Control
I now introduce the synchronized control strategy. The objective is to maintain the staircase output voltage while moving charge from a subpack with a relatively high SOC to a subpack with a relatively low SOC. The equalization is implemented by the inductor connected to each subpack.
Consider the interval \(\Delta t_1\). In this interval, all \(N\) positive-side subpacks are in series and supply the highest output level. The subpack \(u_{1p}\) has the smallest discharge depth. Therefore, during this interval, \(u_{1p}\) should discharge through its balancing inductor \(L_{1p}\) to the other subpacks. I define the gate signal \(g_{1pA}\) as the PWM signal of the switch \(S_{1pA}\). When \(g_{1pA}\) is high, \(u_{1p}\) charges \(L_{1p}\). When \(g_{1pA}\) is low, the inductor current continues through the switches \(S_{2pB},S_{3pB},\ldots,S_{NpB}\) and transfers energy to the remaining subpacks. To prevent the inductor from being bypassed, the bypass switch \(S_{1pD}\) is turned off during the equalization interval.
For the interval \(\Delta t_2\), the output level is formed by \(u_{2p}+u_{3p}+\cdots+u_{Np}\). The subpack \(u_{2p}\) has the smallest discharge depth among the subpacks that are active in this interval. Therefore, \(u_{2p}\) discharges through \(L_{2p}\) to \(u_{3p},\ldots,u_{Np}\). The same principle is repeated for \(u_{3p}\), and so on. The subpack \(u_{Np}\) has the largest discharge depth and never needs to perform an equalizing discharge. Table 2 summarizes this arrangement for the positive half-cycle.
| Battery subpack | Total discharge magnitude | Equalization interval | PWM gate signal |
|---|---|---|---|
| \(u_{1p}\) | \(\Delta SOC_{u_1}\) | \(\Delta t_1\) | \(g_{1pA}\) |
| \(u_{2p}\) | \(\Delta SOC_{u_2}\) | \(\Delta t_2\) | \(g_{2pA}\) |
| \(\vdots\) | \(\vdots\) | \(\vdots\) | \(\vdots\) |
| \(u_{N-1,p}\) | \(\Delta SOC_{u_{N-1}}\) | \(\Delta t_{N-1}\) | \(g_{N-1,pA}\) |
| \(u_{Np}\) | \(\Delta SOC_{u_N}\) | No equalizing discharge | \(- \) |
The negative half-cycle is handled with the same method using the negative-side subpacks. In the charging mode, the direction of power transfer is reversed. A subpack that has a higher charging depth can discharge through the same inductor to a subpack that has a lower charging depth. Therefore, the proposed method is suitable for both discharging and charging operation of the energy storage battery.
To calculate the PWM duty cycle, I first define the average SOC decrease of the positive-side subpacks in a quarter cycle:
\[
\Delta SOC_{ave}
=
\frac{1}{N}\sum_{j=1}^{N}\Delta SOC_{u_j}
\]
For \(u_{1p}\), the required balancing SOC decrease is:
\[
\Delta SOC_{bal,1}
=
\Delta SOC_{ave}-\Delta SOC_{u_1}
\]
During the interval \(\Delta t_1\), the PWM switch operates at frequency \(f_s\). If the balancing inductor current is discontinuous, the average current drawn from \(u_{1p}\) in one switching cycle is:
\[
I_{L,avg,1}
=
\frac{u_{1p}d_{1pA}^2}{2L_1f_s}
\]
where \(L_1\) is the inductance of \(L_{1p}\), and \(d_{1pA}\) is the duty cycle of \(g_{1pA}\). The required average balancing current during \(\Delta t_1\) is:
\[
I_{bal,1}
=
\frac{C_{bat}\Delta SOC_{bal,1}}{\Delta t_1}
\]
Equating the two expressions gives:
\[
d_{1pA}
=
\sqrt{
\frac{2L_1f_sC_{bat}\Delta SOC_{bal,1}}
{\Delta t_1u_{1p}}
}
\]
This formula can be applied to \(u_{2p},\ldots,u_{N-1,p}\) by changing the index. The duty cycles must be updated online because the SOC values change slowly and the subpack voltages change with the state of charge. In my implementation, I use a slow outer loop to compute \(\Delta SOC_{bal,j}\) and a fast inner loop to generate the synchronized PWM pulses. The PWM duty cycle therefore remains consistent with the instantaneous output level.
The synchronized operation has an important advantage. The same power switches are used for the staircase output and for active balancing. There is no need to add a separate equalizer. The inductors are small because they operate at a relatively high PWM frequency. The voltage stress on each power switch is approximately equal to the voltage of one energy storage battery subpack. Therefore, low-voltage MOSFETs can be used in each branch.
Comparison with Conventional Inverter-Based Solution
I compared the proposed scheme with a conventional cascaded multi-level scheme. In the conventional scheme, the AC output is produced by cascaded H-bridge inverters, while the energy storage battery balancing is performed by a separate equalization circuit. The conventional scheme has two independent control systems. The proposed scheme uses one unified controller.
I also considered the effect of voltage stress on switching losses. For a power switch, the switching loss can be approximated as:
\[
E_{sw}
=
\frac{1}{2}V_{ds}I_{ds}\left(t_r+t_{off}\right)
\]
Here, \(V_{ds}\) is the blocking voltage, \(I_{ds}\) is the current at the switching instant, and \(t_r+t_{off}\) is the total switching time. Thus, the switching loss is approximately proportional to the voltage stress of the device. In a cascaded multi-level converter with fewer levels, each switch must block a higher voltage. This increases not only switching loss but also device cost and footprint.
I normalized the comparison for a system with \(N=4\). The proposed topology has \(10N-4\) power switches and \(2N-2\) inductors. The cascaded solution with the same number of output levels has \(10N\) power switches. The cascaded solution with half the number of output levels has \(6N\) power switches, but each switch must block twice the voltage. Table 3 gives the normalized performance metrics.
| Metric | Proposed scheme | Cascaded multi-level, same output levels | Cascaded multi-level, half output levels |
|---|---|---|---|
| Number of power switches | 1 | 1.11 | 0.67 |
| Power-switch cost | 1 | 1.11 | 1.33 |
| Power-switch area | 1 | 1.11 | 1.33 |
| Number of inductors | 1 | 1 | 0.5 |
| Switching loss | 1 | 2.5 | 2.75 |
| Control systems | 1 | 2 | 2 |
The proposed scheme has a slightly larger switch count than the half-level cascaded solution, but it has lower switch-cost and lower switching loss. More importantly, the proposed scheme avoids the separate balancing circuit and the second control system. The integration of AC output and balancing also reduces the total number of high-frequency-switched devices. In the proposed scheme, only the balancing switches operate at high frequency during their corresponding output intervals. The staircase output switches operate at line frequency. This is beneficial for efficiency and electromagnetic interference.
Simulation and Experimental Verification
I built a simulation model in MATLAB/Simulink and a laboratory prototype to validate the proposed energy storage battery grouping strategy. The simulation parameters were \(N=4\), battery voltage platform \(55\text{ V}\), fundamental frequency \(50\text{ Hz}\), and PWM switching frequency \(10\text{ kHz}\). The load was designed to draw a sinusoidal current in phase with the AC voltage, which represents a power-factor-corrected load.
I first simulated the system without active balancing. The output voltage was still a staircase AC waveform, but the SOC of the positive-side subpacks diverged quickly. The subpack that was connected for the longest time had the largest SOC decrease. The subpack that was connected only near the peak had the smallest SOC decrease. After a few cycles, the difference became significant. This divergence would reduce the usable capacity of the energy storage battery pack. When the most discharged subpack reaches the lower SOC limit, the whole series string must stop delivering power even if other subpacks still have energy.
I then enabled the proposed synchronized balancing control. The output voltage waveform remained almost unchanged. The individual subpack currents contained high-frequency pulses during their equalization intervals. These pulses redistributed charge from the less discharged energy storage battery subpacks to the more discharged subpacks. As a result, the SOC trajectories of all positive-side subpacks stayed close to each other. In the first fundamental cycle, the maximum SOC deviation was less than \(0.3\%\). This verified that the balancing control does not disturb the AC output.
The simulation also showed that the balancing inductor current is discontinuous. This is acceptable because the PWM duty cycle was calculated from the average current requirement. The inductor current rises when the PWM switch is on and falls to zero before the end of the switching cycle. The discontinuous current mode makes the balancing action easier to control and avoids reverse-recovery problems in the freewheeling diodes.
On the experimental prototype, I measured the output voltage and current for both the proposed scheme and a conventional cascaded multi-level scheme. The proposed scheme produced a pulse-amplitude-modulated staircase voltage. The output current was a smooth sine wave after the small filter. The cascaded multi-level scheme produced a high-frequency PWM voltage. The measured total harmonic distortion of the proposed scheme was \(2.29\%\), while the efficiency was \(98.77\%\). The measured THD of the cascaded multi-level scheme was \(3.67\%\), and its efficiency was \(96.25\%\). Table 4 summarizes these measured results.
| Measured quantity | Proposed scheme | Cascaded multi-level scheme |
|---|---|---|
| Total harmonic distortion | 2.29% | 3.67% |
| Efficiency | 98.77% | 96.25% |
The higher efficiency of the proposed scheme is mainly due to the reduced number of high-frequency-switched power switches. In the conventional cascaded scheme, every switch in every H-bridge operates at a high PWM frequency. In the proposed scheme, many switches operate at line frequency. Only the balancing switches operate at high frequency, and only during specific angular intervals. The reduced switching loss is particularly important for a large energy storage battery system, because heat management becomes more difficult as power increases.
I also recorded the SOC values after a continuous test of 30 minutes. In the unbalanced case, the most discharged subpack reached \(30.0\%\), while the least discharged subpack remained above \(42.5\%\). This large spread shows that an unconstrained staircase output will make the energy storage battery unusable in a short time. With the proposed balancing control, all four positive-side subpacks converged to approximately \(35.2\%\). The conventional cascaded multi-level scheme with its own balancing circuit converged to \(34.6\%\). The small difference is consistent with the higher efficiency of the proposed topology. Table 5 presents the SOC results.
| Condition | Lowest SOC after 30 min | Highest SOC after 30 min | Final spread |
|---|---|---|---|
| Without balancing | 30.0% | 42.5% | 12.5% |
| Proposed scheme with balancing | 35.2% | 35.2% | <0.3% |
| Cascaded multi-level with balancing | 34.6% | 34.6% | <0.3% |
The experimental SOC trajectories confirmed that the proposed strategy can actively balance the energy storage battery while supplying an AC load. The average SOC after balancing is slightly lower than the average SOC without balancing because the balancing process itself introduces some switching losses. However, this small penalty is acceptable because balancing dramatically increases the available capacity of the energy storage battery. Without balancing, the least discharged subpack still has 42.5% SOC, but the system must stop because the most discharged subpack is at 30.0%. With balancing, the system can continue to use the stored energy until all subpacks reach a safe lower limit.
I also tested the transient response when the load changes. The synchronized PWM control is able to keep all subpacks balanced during the transient because the SOC estimation loop is slow but the output voltage control is fast. The staircase voltage is generated directly from the line-frequency switch sequence, so it does not depend on the balancing control bandwidth. The balancing duty cycle is updated every few fundamental cycles, which is sufficient because the SOC changes slowly compared with the AC period.
Discussion
The proposed topology is best suited for applications where the number of levels is moderate, such as \(N=4\) or \(N=6\). For a very large number of levels, the number of power switches increases linearly, just as in a cascaded converter. However, the proposed scheme avoids the additional equalizer and the separate controller. The unified control strategy reduces communication and coordination overhead. It also allows each energy storage battery subpack to be made of standard modules. The modularity is still preserved because each subpack has its own switch network and balancing inductor.
One limitation is that the output voltage is a staircase rather than a high-frequency PWM waveform. If the AC load is sensitive to voltage harmonics, a small LC filter is needed. In my experiments, the filter was part of the AC load and produced a nearly sinusoidal load voltage. The inductive elements in the circuit also contribute to filtering. The total harmonic distortion of \(2.29\%\) is acceptable for many industrial and commercial loads.
Another consideration is the equalization speed. The balancing current is limited by the inductor value, the switching frequency, and the duty cycle. A larger balancing current will equalize the energy storage battery faster, but it also increases the voltage and current stress of the power switches. In my design, I chose a balancing current that is a fraction of the rated AC current. This is sufficient because the SOC imbalance caused by the staircase output accumulates over many cycles. A slow balancing action is acceptable as long as the average balancing power matches the imbalance power.
The proposed method can also be extended to three-phase systems. For a three-phase energy storage battery system, I would use three separate single-phase units with synchronized switching angles. Alternatively, I could share some switches between phases to reduce the total switch count. The balancing strategy remains the same because each phase has its own positive-side and negative-side subpacks. The only additional task is to manage the unbalanced AC power among phases, which is a normal function of the higher-level power management controller.
In the future, I plan to improve the efficiency further by introducing soft-switching techniques. The balancing switches in the proposed topology switch under a voltage close to the subpack voltage. By adding a small auxiliary resonant network, the switch can be turned on with zero-current or zero-voltage. This would reduce the switching loss associated with active balancing. Another direction is to use model predictive control to optimize both the staircase output and the balancing duty cycle in real time. The model would include the SOC of each energy storage battery subpack, the inductor current, and the AC voltage reference.
Conclusion
In this article, I have presented a topology and control strategy that allows an energy storage battery pack to produce multi-level AC voltage and perform active balancing at the same time. The topology is based on dynamic series connection of battery subpacks. Power switches and inductors form a power-electronic network that can synthesize a staircase voltage wave. The control strategy synchronizes the equalization action with the output level. The battery subpack that is active in a given output interval uses its balancing inductor to transfer energy to subpacks that have a larger discharge depth. I derived the duration of each output level and the PWM duty cycle required for balancing. I also compared the proposed scheme with a conventional cascaded multi-level system. The comparison shows that the proposed scheme has fewer high-frequency-switched devices, lower switching loss, and a simpler control structure.
Simulation and experimental results confirmed the theoretical analysis. Without balancing, the state of charge of the energy storage battery diverges rapidly. With the proposed synchronized PWM balancing, all subpacks stay close to the average SOC. The output voltage remains a multi-level staircase waveform, and the output current is sinusoidal. The measured THD was \(2.29\%\), and the measured efficiency was \(98.77\%\). After 30 minutes of operation, the proposed scheme maintained the SOC of all subpacks at about \(35.2\%\), while the unbalanced case had a spread of \(12.5\%\). This demonstrates that the proposed solution increases the usable capacity of the energy storage battery system.
I believe that the proposed energy storage battery grouping topology is a promising alternative for applications where AC output and cell balancing must be achieved with low cost and high efficiency. Future work will focus on soft switching and advanced model predictive control to further improve the performance of the system.