The integration of renewable energy sources like wind and photovoltaic generation into modern power grids is paramount. In this context, the battery energy storage system (BESS) serves as a critical cornerstone for stabilizing the intermittent power supply and managing load fluctuations. As the vital interface between the battery energy storage system and the DC bus, the bidirectional DC-DC converter’s performance directly determines the efficiency, reliability, and dynamic response of the entire energy management system. Multi-phase interleaved parallel topologies, particularly the three-phase interleaved bidirectional Buck-Boost converter, are favored for their ability to handle high power levels while reducing current stress on individual switches, minimizing input/output current ripple, and enhancing power density. However, a significant challenge arises from inherent inconsistencies in parasitic parameters (e.g., inductor equivalent series resistance, MOSFET on-resistance) among the parallel phases. These discrepancies lead to uneven current distribution, causing thermal imbalance, over-stressing specific components, and ultimately jeopardizing the reliability and lifespan of the battery energy storage system.
This article delves into a novel control strategy designed to address this current imbalance. The proposed method synergistically combines Sliding Mode Control (SMC) for the voltage outer loop with Model Predictive Control (MPC) for the current inner loop, forming an SMC-MPC strategy. This approach aims to provide superior robustness, faster dynamic response, and precise current sharing compared to conventional methods, thereby enhancing the operational stability of the battery energy storage system.
Topology and Operational Analysis of the Three-Phase Interleaved Converter
The topology of the three-phase interleaved bidirectional Buck-Boost converter is central to this study. It consists of three identical Buck-Boost cells connected in parallel at both input and output. Each phase comprises a switching leg with two power MOSFETs and their intrinsic body diodes, an energy storage inductor, and shared input/output filter capacitors. The interleaving technique, where the gate drive signals for the active switches in each phase are phase-shifted by 120°, effectively multiplies the ripple frequency at the input and output, allowing for smaller filter components and reduced electromagnetic interference.
The converter operates in two distinct modes, managed by the battery energy storage system controller based on power flow requirements:
- Boost Mode (Energy Release): When the battery energy storage system discharges to support the DC bus, the converter acts as a step-up converter. The lower switches (S2, S4, S6) are inactive, and their body diodes serve as freewheeling paths. The upper switches (S1, S3, S5) are controlled with interleaved Pulse Width Modulation (PWM).
- Buck Mode (Energy Storage): When surplus energy from the DC bus needs to be stored in the battery energy storage system, the converter operates in step-down mode. Here, the upper switches are inactive, and the lower switches (S2, S4, S6) are actively controlled with interleaved PWM.
The current and voltage ripple characteristics vary with the duty cycle (D). For analysis, the duty cycle range is divided into segments. The expressions for input current ripple (ΔI_in) and output voltage ripple (ΔU_o) in Boost mode across different duty cycle ranges are summarized below.
| Mode | Duty Cycle Range | Input Current Ripple (ΔI_in) | Output Voltage Ripple (ΔU_o) |
|---|---|---|---|
| Boost | 0 < D_Boost < 1/3 | $$\frac{U_o D_{Boost}(1-3D_{Boost})T_s}{L}$$ | $$\frac{U_o D_{Boost}(1-3D_{Boost})T_s}{3RC_2(1-D_{Boost})}$$ |
| 1/3 ≤ D_Boost ≤ 2/3 | $$\frac{U_o T_s (1-2D_{Boost})(3D_{Boost}-1)}{3L}$$ | $$\frac{U_o T_s (1-2D_{Boost})(3D_{Boost}-1)}{9RC_2(1-D_{Boost})}$$ | |
| 2/3 < D_Boost ≤ 1 | $$\frac{U_o T_s (3D_{Boost}-2)(1-D_{Boost})}{L}$$ | $$\frac{U_o T_s (3D_{Boost}-2)}{3RC_2}$$ |
For modeling and control design, the state-space averaging method is applied to a single-phase equivalent circuit. The continuous-time state-space equations for the Boost mode are derived. When the active switch is ON (interval: $$[kT_s, kT_s + D(k)T_s]$$):
$$ \frac{d}{dt} \begin{bmatrix} i_L \\ U_o \end{bmatrix} = \begin{bmatrix} 0 & 0 \\ 0 & -\frac{1}{RC_2} \end{bmatrix} \begin{bmatrix} i_L \\ U_o \end{bmatrix} + \begin{bmatrix} \frac{1}{L} \\ 0 \end{bmatrix} U_{in} $$
When the active switch is OFF (interval: $$[kT_s + D(k)T_s, (k+1)T_s]$$):
$$ \frac{d}{dt} \begin{bmatrix} i_L \\ U_o \end{bmatrix} = \begin{bmatrix} 0 & -\frac{1}{L} \\ \frac{1}{C_2} & -\frac{1}{RC_2} \end{bmatrix} \begin{bmatrix} i_L \\ U_o \end{bmatrix} + \begin{bmatrix} \frac{1}{L} \\ 0 \end{bmatrix} U_{in} $$
Discretizing these equations using a zero-order hold with sampling period $$T_s$$ yields the discrete-time model crucial for digital predictive control:
$$ i_L(k+1) = i_L(k) + \frac{T_s}{L} U_{in}(k) + \frac{D(k)T_s}{L} U_o(k) $$
$$ U_o(k+1) = U_o(k) + \frac{(1-D(k))T_s}{C_2} i_L(k) – \frac{T_s}{RC_2} U_o(k) $$
where $$k$$ denotes the sampling instant. Similar derivations apply to the Buck mode operation.
Proposed SMC-MPC Current Sharing Control Strategy
The core of this work is the development of a composite control strategy. The outer voltage loop employs Sliding Mode Control to generate a robust global current reference, while the inner current loop uses Model Predictive Control to achieve fast and accurate tracking of individual phase current references, inherently compensating for parameter mismatches.
Improved Master-Slave Framework with SMC Voltage Loop
Traditional master-slave current sharing methods often rely on PI controllers, which may suffer from slow response and parameter tuning difficulties. Our framework modifies this concept. The voltage error is processed by the SMC block, which outputs a total inductor current reference $$i_{ref}$$. This total reference is then divided equally among the three phases to obtain individual phase references $$i_{L1,ref}, i_{L2,ref}, i_{L3,ref}$$. A “maximum current” block monitors the actual phase currents and calculates steady-state error terms. These error terms are fed back to adjust the SMC output, forming a correction loop that actively balances the currents.
The SMC design defines a sliding surface $$S$$ that forces the system dynamics to converge to the desired equilibrium. We select the state vector $$\mathbf{x}$$ to include current tracking error, voltage error, and the integral of voltage error to eliminate steady-state偏差:
$$ \mathbf{x} = \begin{bmatrix} x_1 \\ x_2 \\ x_3 \end{bmatrix} = \begin{bmatrix} \sum_{m=1}^{3}(i_{ref} – i_{Lm}) \\ U_{oref} – U_o \\ \int (U_{oref} – U_o) dt \end{bmatrix} $$
The sliding surface is defined as:
$$ S = \Delta_1 x_1 + \Delta_2 x_2 + \Delta_3 x_3 = 0 $$
where $$\Delta_1, \Delta_2, \Delta_3$$ are positive sliding coefficients. According to the reachability condition of SMC, the system trajectory will reach this surface. Solving $$S=0$$ for $$i_{ref}$$ provides the reference current generated by the SMC voltage controller:
$$ i_{ref} = \frac{1}{3}\sum_{m=1}^{3} i_{Lm} – \frac{\Delta_2}{\Delta_1}(U_{oref} – U_o) – \frac{\Delta_3}{\Delta_1} \int (U_{oref} – U_o) dt $$
This reference ensures robust voltage regulation against load and input variations in the battery energy storage system.
Model Predictive Current Control with Duty Cycle Compensation
The inner loop utilizes Finite Control Set MPC. For each phase, a cost function $$J$$ is formulated to penalize the future tracking error of both the inductor current and the output voltage. Using the discrete model for Boost mode, the one-step-ahead predictions $$i_L(k+1)$$ and $$U_o(k+1)$$ from the previous section are substituted into the cost function:
$$ J = [U_o(k+1) – U_{oref}]^2 + [i_L(k+1) – i_{L,ref}]^2 $$
The optimal duty cycle $$D_{opt}(k)$$ for the upcoming switching period is found by minimizing $$J$$ with respect to $$D(k)$$, i.e., solving $$\partial J / \partial D(k) = 0$$. This process yields an explicit analytical expression for the optimal duty cycle for phase *i* (where i=1,2,3):
$$ D_{Boost,i}(k) = 1 + \frac{C_2 L_i}{T_s^2} – \frac{L_i i_{Li}(k)}{T_s U_o(k)} + \frac{C_2 L_i [U_{oref} – U_o(k)]}{T_s^2 U_o(k)} – \frac{C_2 [U_{in}(k) – U_o(k)]}{T_s U_o(k)} – \frac{L_i i_{Li,ref}}{T_s U_o(k)} $$
This equation is the cornerstone of the MPC-based current sharing. Notice that the duty cycle depends on the individual phase inductance $$L_i$$ and the sampled current $$i_{Li}(k)$$. If phase *i* has a lower current than its reference due to a larger parasitic resistance, the term $$-L_i i_{Li}(k)/(T_s U_o(k))$$ becomes less negative, and the term $$-L_i i_{Li,ref}/(T_s U_o(k))$$ provides a fixed offset. The MPC calculation automatically adjusts $$D_i(k)$$ upward to increase the current in that particular phase. This inherent compensation mechanism works simultaneously for all phases, achieving precise current sharing without needing separate, explicit compensators for each imbalance source. The equivalent derivation for Buck mode leads to:
$$ D_{Buck,i}(k) = \frac{L_i i_{Li,ref} – L_i i_{Li}(k) + T_s U_{in}(k)}{T_s U_o(k)} $$
Simulation Analysis and Performance Verification
To validate the proposed SMC-MPC strategy, a detailed simulation model was constructed. The parameters for the three-phase interleaved bidirectional Buck-Boost converter, representing a typical battery energy storage system interface, are listed below.
| Parameter | Value |
|---|---|
| Input Voltage (U_in) | 10 – 48 V |
| Output Voltage (U_o) | 48 V |
| Inductors L1, L2, L3 | 0.90 mH (with mismatched ESR: 0.08, 0.10, 0.12 Ω) |
| Input/Output Capacitors (C1, C2) | 470 µF |
| Switching Frequency (f_s) | 20 kHz |
| Rated Power | 500 W |
Steady-State Current Sharing Performance
The proposed SMC-MPC strategy was compared against a conventional PI-MPC strategy (PI voltage outer loop + MPC current inner loop). Under steady-state operation in Boost mode with a duty cycle of 0.3, the SMC-MPC controller demonstrated significantly superior current balancing. The average current per phase was nearly identical, whereas the PI-MPC strategy showed visible dispersion. A quantitative comparison under different conditions is presented below.
| Control Strategy | Operating Mode | Max Current Sharing Error | Remarks |
|---|---|---|---|
| PI-MPC | Boost (D=0.3) | 4.0% | Visible steady-state imbalance |
| SMC-MPC | Boost (D=0.3) | 2.0% | Excellent balance |
| PI-MPC | Buck (D=0.7) | 4.0% | Consistent imbalance across modes |
| SMC-MPC | Buck (D=0.7) | 1.0% | Near-perfect balance |
Dynamic Response and Load Transient Performance
The robustness of the battery energy storage system interface is critically tested during load transients. Simulations and experimental tests were conducted where the load resistor changed abruptly. The SMC-MPC controller exhibited a dramatically faster recovery to the new steady-state with minimal overshoot in the output current, thanks to the finite-horizon optimization of MPC and the robust, nonlinear nature of SMC. In contrast, the PI-MPC strategy showed a pronounced overshoot and a longer settling time.
| Control Strategy | Output Current Overshoot | Settling Time (approx.) | Current Sharing during Transient |
|---|---|---|---|
| PI-MPC | 11.5% | 50 ms | Recovers after oscillation |
| SMC-MPC | ~0% | 0.4 ms | Maintained effectively |
The experimental waveforms from a 500W prototype further confirmed these findings. During a step load change in Buck mode, the three inductor currents quickly and evenly adjusted to the new level with no observable overshoot, and the output voltage remained tightly regulated. This demonstrates the strategy’s effectiveness in maintaining both voltage stability and current balance in a real battery energy storage system power converter.
Conclusion
This article has presented a comprehensive study on a high-performance control strategy for three-phase interleaved bidirectional Buck-Boost converters used in battery energy storage system applications. The proposed SMC-MPC strategy successfully addresses the critical issue of inherent current imbalance caused by parasitic parameter mismatches. The SMC outer loop provides a robust voltage regulation and generates a stable current reference, while the MPC inner loop delivers fast, accurate, and decentralized current tracking with inherent imbalance compensation.
The key advantages validated through simulation and experimental results include:
- Superior Current Sharing Accuracy: The strategy reduces current sharing error significantly compared to PI-MPC, ensuring equal thermal stress on components and improving the reliability of the battery energy storage system power stage.
- Excellent Dynamic Response: The combined strategy exhibits virtually no overshoot and a settling time orders of magnitude faster during load transients, enhancing the battery energy storage system‘s ability to respond to rapid grid demands.
- Enhanced Robustness: The nonlinear SMC and the predictive nature of MPC make the system less sensitive to parameter variations and disturbances, a crucial feature for the varying operating conditions of a battery energy storage system.
- Simplified Implementation: The control parameters are primarily based on the converter’s physical components (L, C, T_s), reducing the need for complex empirical tuning associated with PI controllers.
In summary, the SMC-MPC control strategy represents a significant advancement for managing power flow in battery energy storage system interfaces. It ensures efficient, reliable, and stable operation by guaranteeing balanced current distribution and robust dynamic performance across both Buck and Boost modes, ultimately contributing to the longevity and effectiveness of the energy storage solution.