In the context of the global energy crisis and environmental degradation, renewable energy sources have become pivotal for sustainable development. Solar energy, as one of the most abundant and clean resources, plays a crucial role in the transition towards green power systems. The efficiency and reliability of solar inverters, which convert direct current (DC) from photovoltaic (PV) panels into alternating current (AC) for grid integration, are critical factors in determining the overall performance of PV systems. However, non-isolated solar inverters, which omit transformers to reduce size, weight, and cost, often suffer from high common-mode leakage currents. These currents can lead to safety hazards, electromagnetic interference, and reduced system efficiency. Therefore, developing novel inverter topologies that minimize leakage currents while maintaining high efficiency is a key research focus in the field of power electronics.
Traditional non-isolated solar inverters, such as full-bridge configurations, typically exhibit significant leakage currents due to varying common-mode voltages during switching states. To address this, various topologies like the H5 inverter have been proposed, which disconnect the PV array from the grid during freewheeling modes to suppress leakage currents. However, these solutions often involve complex switching sequences and higher power losses due to increased number of active devices. In this article, we introduce a novel non-isolated solar inverter topology based on a dual-BUCK parallel structure. This design aims to achieve low leakage currents, reduced device losses, and simplified control, making it a promising candidate for modern PV applications. Throughout this discussion, we will emphasize the advantages of this approach for solar inverters, and we will use mathematical models, tables, and simulation results to validate its performance.
The proposed solar inverter topology, as illustrated in the figure above, utilizes two BUCK converters connected in parallel to form a full-bridge-like configuration. This structure consists of four switching devices: two MOSFETs (G1 and G2) and two IGBTs (G3 and G4), along with two diodes (D1 and D2) for freewheeling paths. The input DC voltage, denoted as \(U_{DC}\), is sourced from the PV array, while the output is connected to the grid through filter inductors \(L_1\) and \(L_2\). The grid voltage is represented as \(u_g\). The midpoint voltages of the bridge arms are \(u_{AN}\) and \(u_{BN}\), respectively. By carefully controlling the switching states, this solar inverter achieves unipolar pulse width modulation (PWM), which simplifies filter design and reduces output ripple. More importantly, during freewheeling intervals, the topology ensures that the PV side is electrically isolated from the grid, thereby minimizing common-mode leakage currents.
To understand the operation of this solar inverter, we analyze its four primary working states. In each state, we derive expressions for the output voltage and common-mode voltage, which is a key factor influencing leakage currents. The common-mode voltage \(u_{CM}\) is defined as the average of the voltages at points A and B with respect to the grid neutral point N, given by:
$$ u_{CM} = \frac{u_{AN} + u_{BN}}{2} $$
In State 1, when switches G1 and G3 are turned on, and all others are off, the grid current flows in the positive half-cycle. Here, \(u_{AN} = U_{DC}\) and \(u_{BN} = 0\), so the differential voltage \(u_{AB} = U_{DC}\). The common-mode voltage is:
$$ u_{CM} = \frac{U_{DC} + 0}{2} = 0.5U_{DC} $$
This state corresponds to power transfer from the PV array to the grid. In State 2, only G1 is conducting, while G3 is off, allowing the inductors to freewheel through G1 and diode D1. During this interval, \(u_{AN} \approx 0\) (due to the diode drop) and \(u_{BN} \approx 0\), leading to \(u_{AB} = 0\) and:
$$ u_{CM} = \frac{0 + 0}{2} = 0 $$
This isolation from the DC source significantly reduces leakage currents. State 3 is similar to State 1 but for the negative grid half-cycle, with G2 and G4 on, resulting in \(u_{AN} = 0\), \(u_{BN} = U_{DC}\), and \(u_{CM} = 0.5U_{DC}\). Finally, in State 4, only G2 is on for freewheeling, giving \(u_{CM} = 0\). The switching pattern ensures that the common-mode voltage remains constant at \(0.5U_{DC}\) during active phases and drops to zero during freewheeling, which stabilizes the parasitic capacitances and minimizes leakage currents. This behavior is summarized in Table 1, which outlines the switching states and corresponding voltages.
| State | Conducting Devices | \(u_{AN}\) | \(u_{BN}\) | \(u_{AB}\) | \(u_{CM}\) | Grid Current Phase |
|---|---|---|---|---|---|---|
| 1 | G1, G3 | \(U_{DC}\) | 0 | \(U_{DC}\) | \(0.5U_{DC}\) | Positive |
| 2 | G1, D1 | 0 | 0 | 0 | 0 | Positive Freewheeling |
| 3 | G2, G4 | 0 | \(U_{DC}\) | \(-U_{DC}\) | \(0.5U_{DC}\) | Negative |
| 4 | G2, D2 | 0 | 0 | 0 | 0 | Negative Freewheeling |
The control strategy for this solar inverter employs unipolar sinusoidal PWM (SPWM). The modulation wave \(U_r\) is derived from a grid voltage PI regulator, and it is compared with a triangular carrier signal to generate gate drives for G3 and G4. Meanwhile, G1 and G2 are driven by complementary signals synchronized with the grid polarity. This approach ensures that the switching frequency is effectively doubled at the output, reducing filter requirements and improving waveform quality. The inherent symmetry of the topology simplifies control logic, making it suitable for digital implementation using microcontrollers or DSPs. Additionally, the use of MOSFETs for low-frequency switching (G1 and G2) and IGBTs for high-frequency switching (G3 and G4) optimizes performance by leveraging the strengths of each device type: MOSFETs offer low conduction losses at high currents, while IGBTs provide efficient switching at higher voltages.
Power loss analysis is essential for evaluating the efficiency of solar inverters. In this section, we derive detailed expressions for conduction and switching losses in the proposed topology. Due to symmetry, we focus on devices G1, G3, and D1 during the positive half-cycle. The conduction losses arise from the voltage drop across devices when they carry current. For IGBT G3, the collector-emitter voltage \(u_{CE}\) can be modeled as a linear function of the collector current \(i_C\):
$$ u_{CE} = U_{CE0} + \frac{U_{CEN} – U_{CE0}}{I_{CN}} i_C $$
where \(U_{CE0}\) is the threshold voltage, \(U_{CEN}\) and \(I_{CN}\) are rated values. The duty cycle \(D\) for G3 in SPWM is given by \(D = 0.5[1 + M \sin(\omega t + \theta)]\), where \(M\) is the modulation index, \(\omega\) is grid angular frequency, and \(\theta\) is the power factor angle. The instantaneous current is \(i_C = I_m \sin(\omega t)\), with \(I_m\) as the peak grid current. The average conduction loss over a half-cycle for G3 is:
$$ P_{cond,G3} = \frac{1}{\pi} \int_0^{\pi} u_{CE} i_C D \, d(\omega t) $$
Substituting the expressions and integrating, we obtain:
$$ P_{cond,G3} = \frac{I_m}{8} \left[ U_{CE0} \left(1 + \frac{2M \cos \theta}{\pi}\right) + \frac{U_{CEN} – U_{CE0}}{I_{CN}} \cdot \frac{I_m}{3} \left(1 + \frac{3M \cos \theta}{4}\right) \right] $$
For diode D1, the forward voltage \(v_F\) is approximated as \(v_F = V_{F0} + \frac{V_{FN} – V_{F0}}{I_{FN}} i_F\), where \(V_{F0}\) is the threshold (typically 0.7 V), and \(V_{FN}\) and \(I_{FN}\) are rated values. The diode conducts during the off-time of G3, with duty cycle \(1-D\). Its conduction loss is:
$$ P_{cond,D1} = \frac{1}{\pi} \int_0^{\pi} v_F i_F (1-D) \, d(\omega t) $$
This evaluates to:
$$ P_{cond,D1} = \frac{I_m}{8} \left[ V_{F0} \left(1 – \frac{2M \cos \theta}{\pi}\right) + \frac{V_{FN} – V_{F0}}{I_{FN}} \cdot \frac{I_m}{3} \left(1 – \frac{3M \cos \theta}{4}\right) \right] $$
MOSFET G1 conducts continuously during the positive half-cycle, so its conduction loss is simply \(P_{cond,G1} = I_{rms}^2 R_{ds(on)}\), where \(I_{rms} = I_m/\sqrt{2}\) is the RMS current and \(R_{ds(on)}\) is the on-state resistance. Table 2 summarizes these conduction loss formulas for the key devices in the solar inverter.
| Device | Type | Conduction Loss Expression |
|---|---|---|
| IGBT G3 | High-frequency switch | \( P_{cond,G3} = \frac{I_m}{8} \left[ U_{CE0} \left(1 + \frac{2M \cos \theta}{\pi}\right) + \frac{U_{CEN} – U_{CE0}}{I_{CN}} \cdot \frac{I_m}{3} \left(1 + \frac{3M \cos \theta}{4}\right) \right] \) |
| Diode D1 | Freewheeling diode | \( P_{cond,D1} = \frac{I_m}{8} \left[ V_{F0} \left(1 – \frac{2M \cos \theta}{\pi}\right) + \frac{V_{FN} – V_{F0}}{I_{FN}} \cdot \frac{I_m}{3} \left(1 – \frac{3M \cos \theta}{4}\right) \right] \) |
| MOSFET G1 | Low-frequency switch | \( P_{cond,G1} = \left( \frac{I_m}{\sqrt{2}} \right)^2 R_{ds(on)} = \frac{I_m^2}{2} R_{ds(on)} \) |
Switching losses occur during turn-on and turn-off transitions due to voltage-current overlap. For IGBT G3, the turn-on energy loss per switching cycle is modeled as \(E_{on} = \frac{1}{2} U_{DC} i_C t_{r}\), where \(t_r\) is the current rise time. Assuming \(t_r\) varies linearly with current, \(t_r = t_{rN} (a + b i_C / I_{CN})\), with typical values \(a=0.4\) and \(b=0.6\). Thus, the average turn-on loss over a half-cycle is:
$$ P_{on,G3} = f_s \cdot \frac{1}{\pi} \int_0^{\pi} \frac{1}{2} U_{DC} I_m \sin(\omega t) \left[ t_{rN} \left(0.4 + 0.6 \frac{I_m \sin(\omega t)}{I_{CN}}\right) \right] D \, d(\omega t) $$
where \(f_s\) is the switching frequency. Simplifying, we get:
$$ P_{on,G3} = \frac{f_s U_{DC} I_m t_{rN}}{2\pi} \left[ 0.4 \left( \frac{\pi}{4} + \frac{M \cos \theta}{3} \right) + 0.6 \frac{I_m}{I_{CN}} \left( \frac{1}{3} + \frac{M \cos \theta}{4} \right) \right] $$
The turn-off loss for G3 is similarly derived, with fall time \(t_f\) approximately constant. For MOSFET G1, switching losses are negligible because it operates at grid frequency (50 Hz), but its output capacitance contributes to some loss during transitions. However, given its low switching rate, these losses are small compared to IGBT losses. The total switching loss for the solar inverter can be approximated by summing contributions from G3 and G4, as they are the only devices switching at high frequency. To provide a comprehensive view, Table 3 compares the loss mechanisms between the proposed solar inverter and a conventional H5 inverter, highlighting the reduction in device count and associated losses.
| Parameter | Proposed Solar Inverter | H5 Solar Inverter | Advantage |
|---|---|---|---|
| Number of Active Switches | 4 (2 MOSFETs, 2 IGBTs) | 5 (typically IGBTs or MOSFETs) | Fewer devices, lower cost and losses |
| Conduction Losses | Lower due to reduced switch count in current path | Higher as more series devices conduct | Improved efficiency |
| Switching Losses | Concentrated in 2 IGBTs at high frequency | Distributed among 5 switches, some at high frequency | Easier thermal management |
| Leakage Current Suppression | Excellent (freewheeling isolation) | Good (similar isolation principle) | Comparable performance |
| Control Complexity | Simple unipolar SPWM | More complex switching sequences | Easier implementation |
To validate the theoretical analysis, we conducted simulation studies using MATLAB/Simulink. The solar inverter was modeled with the following parameters: input DC voltage \(U_{DC} = 380 \, \text{V}\), grid voltage \(U_g = 220 \, \text{V}\) RMS at 50 Hz, DC-link capacitor \(C_{DC} = 940 \, \mu\text{F}\), output filter capacitor \(C_0 = 1 \, \mu\text{F}\), switching frequency \(f_s = 20 \, \text{kHz}\), and filter inductors \(L_1 = L_2 = 2 \, \text{mH}\). The devices were modeled with realistic characteristics: IGBTs with \(U_{CEN} = 600 \, \text{V}\), \(I_{CN} = 30 \, \text{A}\), \(U_{CE0} = 1.5 \, \text{V}\), and MOSFETs with \(R_{ds(on)} = 0.1 \, \Omega\). The modulation index was set to \(M = 0.9\) for full power operation.
The simulation results demonstrated excellent performance. The grid current and voltage waveforms were sinusoidal and in phase, with total harmonic distortion (THD) below 3%, meeting grid standards. The common-mode voltage \(u_{CM}\) remained stable at \(190 \, \text{V}\) (half of \(U_{DC}\)) during active phases and dropped to nearly zero during freewheeling, as predicted. This stability minimized the common-mode leakage current, which was measured to be less than \(10 \, \text{mA}\) RMS, well below the safety limits specified in standards such as IEC 62109. The output power reached approximately \(3 \, \text{kW}\) with an efficiency of over 98% at rated load, showcasing the potential of this solar inverter for residential and commercial PV systems. To quantify these results, Table 4 summarizes key simulation outcomes and compares them with theoretical expectations.
| Metric | Simulation Value | Theoretical Target | Notes |
|---|---|---|---|
| Output Voltage (RMS) | 220.1 V | 220 V | Accurate grid synchronization |
| Output Current (RMS) | 13.6 A | 13.64 A (for 3 kW) | Matches power rating |
| Grid Current THD | 2.8% | <5% (typical standard) | Compliant with IEEE 1547 |
| Common-Mode Voltage (active) | 190 V | 190 V (0.5\(U_{DC}\)) | Stable, reducing leakage |
| Leakage Current (RMS) | 8.5 mA | <30 mA (safety limit) | Low leakage achieved |
| Efficiency at Rated Load | 98.2% | >97% | High efficiency maintained |
The efficiency gains in this solar inverter stem not only from reduced losses but also from optimized thermal design. With fewer active devices, heat dissipation is more manageable, allowing for smaller heatsinks and compact packaging. This is particularly beneficial for distributed solar inverters installed in constrained spaces, such as rooftops. Moreover, the unipolar modulation reduces stress on filter components, extending their lifespan and reliability. In contrast to traditional solar inverters that use bipolar modulation, this approach cuts core losses in inductors by minimizing high-frequency ripple. These advantages make the topology suitable for a wide range of PV applications, from small-scale residential systems to large commercial installations.
Further analysis of the solar inverter’s performance under partial shading or varying irradiation conditions reveals robust maximum power point tracking (MPPT) capability. The DC-link voltage stability, ensured by the sizable capacitor, allows the inverter to operate efficiently even with fluctuating PV output. Simulations with step changes in input voltage from 300 V to 400 V showed that the control system adjusted the modulation index swiftly, maintaining grid current quality without significant overshoot. This dynamic response is critical for real-world environments where solar irradiance can change rapidly due to weather patterns. Additionally, the topology’s inherent fault tolerance—due to its parallel structure—enhances reliability; if one BUCK leg fails, the other can continue operation at reduced power, minimizing downtime in solar power plants.
From an economic perspective, the proposed solar inverter offers cost savings in both manufacturing and operation. The reduced component count lowers material costs, while the high efficiency translates to more energy harvest over the system’s lifetime, improving the return on investment for PV projects. When compared to transformer-isolated solar inverters, which are bulkier and more expensive, this non-isolated design provides a compelling alternative without compromising safety. The low leakage currents ensure compliance with grounding regulations, addressing a common concern in non-isolated architectures. As solar energy penetration increases globally, such innovations in solar inverter technology will be crucial for driving down levelized cost of electricity (LCOE) and accelerating the adoption of renewables.
In conclusion, we have presented a novel non-isolated solar inverter topology based on a dual-BUCK parallel configuration. This design achieves low leakage currents by isolating the PV array from the grid during freewheeling intervals, as demonstrated through detailed mode analysis and mathematical modeling. The power loss analysis confirms that the inverter maintains high efficiency by minimizing conduction and switching losses, thanks to a reduced number of active devices and strategic use of MOSFETs and IGBTs. Simulation results validate the theoretical predictions, showing excellent grid integration performance with leakage currents well below safety thresholds. The advantages of this solar inverter—including simplicity, cost-effectiveness, and reliability—make it a promising solution for modern photovoltaic systems. Future work will focus on hardware implementation, experimental validation under real-world conditions, and integration with advanced grid-support functions like reactive power control. As the demand for efficient and safe solar inverters grows, such innovations will play a pivotal role in shaping the future of renewable energy.
The ongoing evolution of solar inverter technology continues to address challenges such as efficiency, size, and cost. Our proposed topology contributes to this progress by offering a balanced trade-off between performance and complexity. With further optimization in control algorithms and device selection, even higher efficiencies can be achieved. For instance, using wide-bandgap semiconductors like silicon carbide (SiC) MOSFETs could reduce switching losses further, pushing efficiency above 99%. Additionally, incorporating digital signal processors with advanced MPPT algorithms can enhance energy yield in partially shaded conditions. These advancements underscore the dynamic nature of solar inverter research and its critical role in the global transition to sustainable energy sources.