In the realm of photovoltaic (PV) power generation, solar inverters play a pivotal role in converting direct current (DC) from solar panels into alternating current (AC) suitable for grid integration. Non-isolated solar inverters, which eliminate the bulky and inefficient transformer, have gained significant attention due to their higher efficiency, lower cost, and compact size. However, a critical challenge persists: the leakage current caused by the parasitic capacitance between the PV panels and ground. This leakage current not only poses safety hazards but also leads to electromagnetic interference and reduced system reliability. According to standards such as VDE 0126-1-1, the leakage current amplitude must be limited below 300 mA. Various topologies and control strategies have been proposed to mitigate this issue, including half-bridge, H5, and HERIC configurations for single-phase systems. Yet, for three-phase systems, which are commonly used in industrial and large-scale PV installations, effective solutions that completely eliminate leakage current while maintaining simplicity and robustness are still evolving. In this context, I propose a novel combined three-phase non-isolated solar inverter topology incorporating flying capacitors. This topology inherently shorts the parasitic capacitance to ground, thereby suppressing leakage current entirely. Moreover, it operates with decoupled phases, enabling independent control and exceptional capability under unbalanced loads. This article delves into the operational principles, modulation strategy, design methodology, and experimental validation of this advanced solar inverter system.
The core innovation lies in the topology’s structure. It comprises three independent single-phase H5 inverter legs, each enhanced with a flying capacitor. The negative terminal of the PV array is directly connected to the ground wire, effectively short-circuiting the parasitic capacitance (Cpv) between the PV panels and earth. This grounding strategy is fundamental to leakage current elimination. Each phase operates autonomously, meaning that the three-phase system is essentially a combination of three single-phase solar inverters sharing a common DC bus. The DC input voltage is denoted as Udc, with Cdc serving as the DC-link stabilizing capacitor. Each phase leg includes five power switches (e.g., V1 to V5 for phase A), a flying capacitor (Cfly,a, Cfly,b, Cfly,c), an output filter inductor (Lf), and a filter capacitor (Cf). The AC outputs are connected to the three-phase grid via these filters. The decoupled nature allows for straightforward three-phase sinusoidal pulse width modulation (SPWM) control without cross-coupling complications, making this solar inverter highly versatile for various grid conditions.
To understand the leakage current suppression mechanism, analyzing the common-mode behavior is essential. For a single-phase non-isolated solar inverter, the common-mode voltage (UCM) and differential-mode voltage (UDM) are defined relative to the ground. The common-mode voltage is a primary driver of leakage current through the parasitic capacitance. In the proposed topology, by grounding the PV negative terminal, the common-mode voltage for each phase is constrained. Let’s derive the common-mode model. For any phase (e.g., phase A), the voltages from output points A and N (neutral) to ground are UAN and UBN (where B is a virtual point in a single-phase context, but here we consider the phase output relative to ground). The common-mode voltage UCM,phase and differential-mode voltage UDM,phase are:
$$ U_{CM,phase} = \frac{U_{AN} + U_{BN}}{2} $$
$$ U_{DM,phase} = U_{AN} – U_{BN} $$
In a simplified common-mode equivalent circuit, the total common-mode voltage (UCM,total) for the three-phase system is the superposition of individual phase common-mode voltages. For the proposed solar inverter, during all switching states, the grounding ensures that UCM,phase remains constant at zero or a fixed value, depending on the mode. Specifically, when analyzing the switching states, the voltage between the PV negative (grounded) and the grid neutral is minimized. The total common-mode voltage for the three-phase solar inverter can be expressed as:
$$ U_{CM,total} = \frac{U_{CM,A} + U_{CM,B} + U_{CM,C}}{3} $$
where UCM,A, UCM,B, and UCM,C are the total common-mode voltages of phases A, B, and C, respectively. Through detailed modal analysis, it is shown that UCM,phase for each phase remains invariant over switching cycles, leading to UCM,total ≈ 0. Since leakage current (ileak) is proportional to the derivative of the common-mode voltage across the parasitic capacitance, i.e.,
$$ i_{leak} = C_{pv} \frac{dU_{CM,total}}{dt} $$
a constant UCM,total results in zero leakage current. This foundational principle underscores the effectiveness of this solar inverter topology in eliminating ground leakage currents.
The operation of each phase can be dissected into eight distinct modes per switching cycle, dictated by the states of the five power switches. These modes ensure proper charging and discharging of the flying capacitor, which is crucial for generating the AC output while maintaining common-mode voltage stability. The following table summarizes the switch states for phase A (with 1 denoting ON and 0 denoting OFF) over these modes:
| Mode | V1 | V2 | V3 | V4 | V5 | Description |
|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 0 | 1 | DC source supplies load and charges flying capacitor. |
| 2 | 1 | 0 | 0 | 0 | 1 | Flying capacitor charging continues; inductor freewheels. |
| 3 | 0 | 1 | 0 | 1 | 0 | Inductor current flows, aiding flying capacitor charge. |
| 4 | 0 | 0 | 0 | 1 | 1 | Inductor freewheeling mode. |
| 5 | 0 | 1 | 0 | 1 | 0 | Flying capacitor discharges to supply load. |
| 6 | 1 | 0 | 0 | 1 | 1 | DC source charges flying capacitor; inductor freewheels. |
| 7 | 1 | 0 | 1 | 0 | 1 | DC source and inductor current charge flying capacitor. |
| 8 | 1 | 0 | 0 | 1 | 1 | Flying capacitor charging continues; inductor freewheels. |
These modes alternate between positive and negative half-cycles of the output AC waveform. In modes 1-4 (positive half-cycle), the flying capacitor is charged to approximately half the DC-link voltage, while in modes 5-8 (negative half-cycle), it discharges to provide negative voltage polarity. The switching sequence ensures that the common-mode voltage remains stable. For instance, in mode 1, the output voltage UAN ≈ Udc, and UBN ≈ 0, yielding UCM,phase = Udc/2. However, due to the grounded PV negative, the potential difference across Cpv is negligible, so UCM,total is effectively zero. Similar analysis for other modes confirms this invariance. This modal operation is replicated across all three phases, with phase shifts of 120 degrees, to generate balanced three-phase outputs. The independence of each phase means that imbalances in load or grid conditions do not propagate, enhancing the reliability of this solar inverter in real-world applications.
Control of this solar inverter is achieved through a synchronized double-carrier unipolar SPWM strategy. This modulation technique offers advantages over bipolar SPWM, including lower switching losses, reduced electromagnetic interference, and smaller filter requirements. For each phase, two triangular carrier waves with opposite phases are compared with a sinusoidal reference signal. The comparison generates gate signals for the switches, ensuring that the flying capacitor is properly engaged during the negative half-cycle. The modulation scheme can be described mathematically. Let the sinusoidal reference for phase A be:
$$ v_{ref,A}(t) = M \cdot \sin(2\pi f t) $$
where M is the modulation index (0 ≤ M ≤ 1) and f is the grid frequency (e.g., 50 Hz). The carrier waves have frequency fsw (switching frequency, e.g., 20 kHz) and amplitudes adjusted to match the DC-link voltage. The gate signals are derived as follows: when vref,A > carrier1, switch V1 is turned ON; when vref,A < carrier2, switch V2 is turned ON, and so on, according to the mode table. This approach ensures continuous duty cycle variation, enabling smooth output voltage transitions. For closed-loop control, a voltage feedback loop is implemented. The output AC voltage is measured and compared with a reference sine wave. The error is processed through a proportional-integral (PI) controller to adjust the modulation index, maintaining stable output under varying load and input conditions. The decoupled nature allows independent PI controllers for each phase, simplifying the control architecture. This control strategy is highly effective for solar inverters, ensuring grid-compliant power injection with low total harmonic distortion (THD).
A critical component in this solar inverter topology is the flying capacitor. Its design directly impacts performance, efficiency, and cost. The flying capacitor acts as a temporary energy storage element during the negative half-cycle, supplying power when the DC source is disconnected from the load. The capacitor must be sized to minimize voltage ripple while ensuring reliable operation. The design principle is based on energy balance. During the negative half-cycle, the energy discharged by the capacitor (Edischarge) should approximately equal the energy consumed by the load (Eload) over that interval. For a phase with output voltage Uout (RMS), load resistance R, and switching period Tsw = 1/fsw, the energy consumed in half a switching cycle (Δt = 0.5/fsw) is:
$$ E_{load} = \frac{U_{out}^2}{R} \Delta t $$
The energy stored in a capacitor with capacitance Cfly and voltage change from U1 to U2 is:
$$ E_{discharge} = \frac{1}{2} C_{fly} (U_1^2 – U_2^2) $$
Setting Edischarge ≈ Eload and assuming U1 ≈ Udc/2 (the charged voltage) and U2 slightly lower, we can derive Cfly. To limit voltage ripple ΔU = U1 – U2 to a small value (e.g., 5 V), the capacitance can be calculated as:
$$ C_{fly} = \frac{I_{avg} \Delta t}{\Delta U} $$
where Iavg is the average output current during discharge. For a 200 W per phase solar inverter with Udc = 200 V, Uout = 110 V RMS, R = 60 Ω, fsw = 20 kHz, and ΔU = 0.1 V (for tight ripple), the calculation yields Cfly ≈ 250 μF. In practice, to ensure robustness, a larger capacitance such as 440 μF (by paralleling two 220 μF capacitors) is selected. This design minimizes losses due to equivalent series resistance (ESR) and ensures stable operation across temperature variations. Proper selection of flying capacitors is essential for the longevity and efficiency of solar inverters, particularly in high-power applications.
To validate the theoretical analysis, a prototype three-phase solar inverter was built and tested. The key parameters are summarized in the table below:
| Parameter | Value |
|---|---|
| DC Input Voltage (Udc) | 200 V |
| Output Voltage per Phase (RMS) | 110 V |
| Rated Power per Phase | 200 W |
| Output Frequency | 50 Hz |
| Switching Frequency (fsw) | 20 kHz |
| DC-Link Capacitor (Cdc) | 220 μF |
| Filter Capacitor (Cf) | 4.7 μF |
| Filter Inductor (Lf) | 5 mH |
| Flying Capacitor (Cfly) | 440 μF |
| Parasitic Capacitance (Cpv) | 100 nF |
The prototype was subjected to various load conditions, including balanced full load and unbalanced loads. Experimental waveforms confirmed the theoretical predictions. Under full load (200 W per phase), the output voltages were sinusoidal with low distortion, and the output currents were balanced. Critically, the leakage current was measured to be below 10 mA peak, far under the 300 mA limit. This demonstrates the effectiveness of the grounding scheme in eliminating leakage current. For unbalanced load conditions, where one phase delivered 150 W while others delivered 200 W, the output voltages remained stable due to independent phase control, and leakage current stayed similarly low. These results highlight the robustness of this solar inverter topology in practical scenarios. The modulation strategy ensured smooth switching transitions, and the flying capacitors maintained stable voltages with minimal ripple. The system’s efficiency was measured to be above 95% at rated load, competitive with existing non-isolated solar inverters.
The integration of such solar inverters into modern PV systems often involves hybrid configurations that include energy storage, as illustrated in the image above. This combination enhances grid stability and enables self-consumption of solar energy. The proposed topology, with its leakage current elimination and decoupled control, is well-suited for these advanced applications. For instance, in a hybrid system, the solar inverter must handle bidirectional power flow and frequent load variations; the independent phase operation ensures that imbalances from storage charging or discharging do not affect grid synchronization. Moreover, the use of flying capacitors can be extended to multi-level topologies for higher voltage applications, further improving the scalability of solar inverters.
In-depth analysis of the common-mode behavior reveals additional insights. The total common-mode voltage for the three-phase solar inverter can be expressed in terms of phase voltages. Let UAG, UBG, and UCG be the voltages from phases A, B, and C to ground, respectively. The common-mode voltage UCM and differential-mode voltages UDM1, UDM2 are:
$$ U_{CM} = \frac{U_{AG} + U_{BG} + U_{CG}}{3} $$
$$ U_{DM1} = U_{AG} – U_{BG}, \quad U_{DM2} = U_{BG} – U_{CG} $$
For the proposed topology, due to the grounded PV negative, UAG, UBG, UCG are constrained such that UCM is constant. Simulation studies using tools like MATLAB/Simulink confirm this. A model was developed with the parameters above, and the common-mode voltage was monitored over time. The results showed that UCM had negligible high-frequency components, with a peak-to-peak variation of less than 1 V, compared to tens of volts in conventional topologies. This directly correlates with the suppressed leakage current. The simulation also assessed total harmonic distortion (THD) of the output current. Under full load, the THD was below 3%, meeting grid codes such as IEEE 1547. These simulations validate the design before hardware implementation, reducing development time for solar inverters.
The flying capacitor design can be optimized further by considering temperature effects and aging. The capacitance value may drift over time, affecting performance. Using film capacitors with low ESR and high ripple current ratings is recommended for long-life solar inverters. The energy balance equation can be refined to account for non-idealities like switch voltage drops and inductor resistance. Let the average discharge current Idis be:
$$ I_{dis} = \frac{U_{out}}{R} + \Delta I_{ripple} $$
where ΔIripple is the inductor current ripple. Then, the capacitance required to limit voltage ripple ΔU is:
$$ C_{fly} = \frac{I_{dis} \cdot D \cdot T_{sw}}{\Delta U} $$
where D is the duty cycle during discharge. For high-power solar inverters, this calculation ensures reliable operation under peak loads. Additionally, the flying capacitor voltage rating must exceed Udc/2 with a safety margin. For Udc = 200 V, a 400 V rated capacitor is suitable. These design considerations are crucial for commercializing this solar inverter topology.
Comparative analysis with existing three-phase non-isolated solar inverters underscores the advantages. Topologies like the three-phase H6 or HERIC variants often rely on complex modulation or additional switches to clamp common-mode voltage, but they may not fully eliminate leakage current under all conditions. In contrast, the proposed combined topology guarantees leakage current suppression through physical grounding. Moreover, the decoupled phases simplify control algorithms; each phase can use standard single-phase SPWM without need for coordinate transformations like dq0. This reduces computational burden on digital signal processors (DSPs), lowering cost. The table below compares key attributes:
| Topology | Leakage Current Suppression | Control Complexity | Efficiency | Unbalanced Load Capability |
|---|---|---|---|---|
| Proposed Combined Inverter | Complete (theoretical zero) | Low (independent phases) | High (>95%) | Excellent |
| Three-Phase H6 Inverter | Partial (depends on modulation) | Moderate (coupled phases) | High | Limited |
| NPC Three-Level Inverter | Good but requires clamping | High (complex PWM) | Medium | Moderate |
This comparison highlights the suitability of the proposed solar inverter for applications where safety and grid quality are paramount. As solar penetration increases, grid codes become stricter regarding leakage current and harmonics; this topology offers a compliant solution.
Experimental validation extended to dynamic conditions, such as sudden load changes and input voltage variations. The solar inverter was tested with a DC source emulating PV panels with maximum power point tracking (MPPT) variations. The output voltage regulation remained stable, with transient responses settling within 20 ms. The leakage current never exceeded 15 mA, even during transients. This robustness is attributed to the inherent common-mode voltage stability. Furthermore, the prototype was connected to a grid simulator to test anti-islanding protection and power factor correction. The solar inverter maintained unity power factor injection with reactive power control capability. These tests demonstrate readiness for grid-tied applications. The modular design allows scaling to higher power levels by paralleling phases or using higher-rated components. For instance, a 10 kW system could use three phases of 3.3 kW each, with shared cooling and control. This scalability makes it attractive for residential and commercial solar installations.
In conclusion, I have presented a novel combined three-phase solar inverter topology with flying capacitors that completely eliminates leakage current by grounding the PV negative terminal. The topology features decoupled phase operation, enabling independent control and superior unbalanced load capability. Through detailed analysis of common-mode models, switching modalities, and control strategies, I have shown how constant common-mode voltage is maintained, driving leakage current to near zero. The flying capacitor design ensures efficient energy transfer during negative half-cycles. Experimental results from a 200 W per phase prototype confirm theoretical predictions, with leakage currents below 10 mA and high efficiency. This solar inverter offers a compelling solution for modern PV systems, addressing safety and regulatory concerns while simplifying control and enhancing reliability. Future work may explore integration with wide-bandgap devices for higher switching frequencies, multi-level extensions for medium-voltage grids, and advanced fault-tolerant features. As the demand for clean energy grows, such innovations in solar inverter technology will be crucial for sustainable power networks.