As the construction of new power systems steadily advances, the high penetration of power electronic interfaces in the source‑grid‑load chain has become a defining trend. Among the various types of solar inverter topologies, the LC‑type inverter is widely adopted for distributed generation and grid connection due to its superior attenuation of high‑order switching harmonics and smaller total inductance. However, the interaction between the LC filter and the grid impedance induces an LCL resonance that threatens system stability. To address this challenge, active damping based on state‑variable feedback has been extensively studied because it introduces a virtual resistor without physical power losses. Yet, the inherent digital control delay – typically one computation cycle plus a half‑cycle zero‑order hold – degrades the damping performance, especially when the resonance frequency exceeds one‑sixth of the switching frequency. In this work, we propose a robust active damping method that exploits double‑sampling of the point‑of‑common‑coupling (PCC) voltage to compensate for the 1.5‑cycle delay, thereby extending the positive damping region up to nearly the Nyquist frequency. The method is computationally simple, requires no extra parameter tuning, and significantly improves the robustness of LC‑type grid‑connected inverters against variations in grid inductance.
System Model of the LC‑type Grid‑Connected Inverter
Figure 1 (not shown) illustrates the topology of a three‑phase LC‑type grid‑connected inverter. The system consists of a bridge‑side inductor \(L_1\), a filter capacitor \(C_{fil}\), and the grid inductance \(L_{grid}\). The DC‑link voltage is \(v_{dc}\), the inverter output voltage is \(v_{inv}\), the PCC voltage is \(v_{pcc}\), and the grid voltage is \(v_{grid}\). The bridge current \(i_1\), the capacitor current \(i_{C_{fil}}\), and the grid current \(i_2\) are measured. A phase‑locked loop (PLL) extracts the phase \(\theta\) from the PCC voltage, and the three‑phase bridge currents are transformed into the rotating \(dq\) frame. A proportional‑integral (PI) controller in the synchronous reference frame tracks the current references \(i_{d}^{ref}\) and \(i_{q}^{ref}\). The PCC voltage is fed forward to achieve pre‑synchronization and limit the inrush current. Finally, space‑vector pulse‑width modulation (SVPWM) generates the gate signals.
The transfer function of the PI current controller in the continuous domain is
\[
H_{coni}(s) = K_P + \frac{K_I}{s}
\]
where \(K_P\) and \(K_I\) are the proportional and integral gains.
The digital control delay, including one computation delay and a half‑sample zero‑order hold, is modeled as
\[
H_{del}(s) = e^{-1.5 s T_{swi}}
\]
with \(T_{swi}\) being the switching period. For a typical 60 kW inverter prototype used in this study, the parameters are listed in Table 1.
| Parameter | Value |
|---|---|
| Grid voltage \(v_{grid}\) | 380 V |
| DC‑link voltage \(v_{dc}\) | 640 V |
| Bridge inductor \(L_1\) | 341 µH |
| Filter capacitor \(C_{fil}\) | 20 µF |
| Proportional gain \(K_P\) | 1.65 |
| Integral gain \(K_I\) | 794 |
| Grid frequency \(f_{grid}\) | 50 Hz |
| Switching frequency \(f_{swi}\) | 19.2 kHz |
Analysis of Inherent Damping and Stability
To quantify the damping contribution, we derive the equivalent virtual admittances introduced by the capacitor‑current feedback and the PCC voltage feedforward. After simplifying the control block diagram (ignoring the integral term of the PI controller which has negligible effect near the LCL resonance), the equivalent parallel admittances are
\[
Y_{eq1}(s) = \frac{K_P C_{fil}}{L_1} e^{-1.5 s T_{swi}}
\]
\[
Y_{eq2}(s) = -\frac{1}{s L_1} e^{-1.5 s T_{swi}}
\]
Substituting \(s = j\omega\) yields the real parts (conductances):
\[
G_{eq1}(\omega) = \frac{K_P C_{fil}}{L_1} \cos(1.5 \omega T_{swi})
\]
\[
G_{eq2}(\omega) = \frac{\sin(1.5 \omega T_{swi})}{\omega L_1}
\]
The positive damping band of \(G_{eq1}\) is limited to \((0, f_{swi}/6)\); that of \(G_{eq2}\) extends to \((0, f_{swi}/3)\). Their sum \(G_{eq} = G_{eq1}+G_{eq2}\) exhibits a positive region narrower than \(f_{swi}/3\). Consequently, when the LCL resonance frequency \(f_r > f_{swi}/3\), the combined virtual conductance becomes negative, producing open‑loop right‑half‑plane poles and threatening closed‑loop stability. The resonance frequency is given by
\[
\omega_r = 2\pi f_r = \sqrt{\frac{L_1+L_{grid}}{L_1 L_{grid} C_{fil}}}
\]
The outer‑loop gain Bode plot (not shown) confirms that for \(L_{grid}=180\) µH and \(100\) µH the system is minimum‑phase and stable, whereas for \(L_{grid}=25\) µH it becomes non‑minimum‑phase and a careful design is needed to avoid instability.
Proposed Double‑Sampling Delay Compensation Method
The root cause of the reduced robustness is the negative conductance contributed by the delayed PCC voltage feedforward. To compensate the 1.5‑cycle delay, we propose a double‑sampling scheme that acquires the PCC voltage at both the valley and the peak of the carrier wave within one switching period. The conventional single‑sampling (valley) obtains \(v_{pcc}\); the additional sample (peak) yields \(v’_{pcc}\). These two samples are combined to generate an advanced signal:
\[
u’_m = u_m + v_{pcc} + 3(v’_{pcc} – v_{pcc})
\]
which approximates a 1.5‑step lead in the \(s\)‑domain:
\[
u’_m \approx u_m + (1 + 1.5 s T_{swi})v_{pcc}
\]
Figure 2 (not shown) depicts the timing diagram. The controller must satisfy the timing constraints:
\[
t_{AD1} + t_{con} + t_{pcc} + t_{SVPWM} < T_{swi}
\]
\[
t_{pcc} + t_{SVPWM} < \frac{T_{swi}}{2} – t_{AD2}
\]
The second constraint allows more relaxed computation than many real‑time methods, because the PCC feedforward and SVPWM tasks have up to \(5T_{swi}/12 – t_{AD2}\) additional time.
After compensation, the equivalent virtual conductance of the PCC voltage feedforward becomes
\[
G_{ceq2}(\omega) = \frac{\sin(1.5\omega T_{swi}) + 1.5\omega T_{swi} \cos(1.5\omega T_{swi})}{\omega L_1}
\]
Its positive damping band extends to \(0.48 f_{swi}\), as shown in Figure 3 (not shown). Even with the negative contribution from \(G_{eq1}\) in the band \((f_{swi}/6, f_{swi}/2)\), the total conductance \(G_{ceq}\) remains positive up to \(0.46 f_{swi}\).
The compensated inner‑loop gain and outer‑loop gain become:
\[
T_{com}^{in}(s) = H_{del}(s) H_{v_{inv}-i_2}(s) \left( K_P s C_{fil} – \frac{1.5 s T_{swi}+1}{L_{grid} s} \right)
\]
\[
T_{com}^{out}(s) = \frac{H_{coni}(s) H_{del}(s) H_{v_{inv}-i_2}(s)}{1 + T_{com}^{in}(s)}
\]
The Bode plot of \(T_{com}^{out}\) (not shown) indicates that the system remains minimum‑phase for all tested grid inductances, with a minimum gain margin of 2.3 dB and a minimum phase margin of 58°. Hence, the inverter can stably operate even when the resonance frequency exceeds \(f_{swi}/3\).
It is worth emphasizing that the proposed double‑sampling technique is universally applicable to different types of solar inverter configurations, because it only relies on the availability of PCC voltage measurements, which are standard in grid‑tied inverters. The method does not require complex parameter tuning, making it a plug‑and‑play solution that enhances the active damping performance of various types of solar inverter topologies, including those using LCL or LC filters.
Experimental Verification
Hardware‑in‑the‑loop tests were conducted using a Typhoon HIL604 platform with a TMS320F28377D digital signal processor. All parameters matched Table 1. We evaluated three grid inductance cases: \(L_{grid}=180\) µH, 100 µH, and 25 µH. The steady‑state waveforms without delay compensation (not shown) reveal that for \(L_{grid}=25\) µH the PCC voltage and grid current exhibit pronounced high‑frequency oscillations, confirming the predicted instability. In contrast, with the proposed double‑sampling compensation, all three cases exhibit stable, clean waveforms (not shown). The A‑phase grid current spectrum, summarized in Table 2, demonstrates the dramatic reduction of the LCL resonance harmonic.
| Grid Inductance \(L_{grid}\) | Without Compensation | With Compensation |
|---|---|---|
| 180 µH | < 0.3% | < 0.3% |
| 100 µH | < 0.3% | < 0.3% |
| 25 µH | 52.06% | < 0.3% |
Dynamic responses from full load to half load (not shown) were also recorded. In all cases, the grid current reached steady state within 4 ms with a maximum overshoot below 10%, and no high‑frequency oscillations were observed. The experimental results decisively prove that the proposed double‑sampling delay compensation method effectively suppresses the LCL resonance irrespective of the grid impedance, thereby improving the robustness of LC‑type grid‑connected inverters. In addition, the method can be directly applied to other types of solar inverter systems that use similar digital control architectures, such as two‑level or multilevel inverters.
It is important to note that the technique is not limited to the specific inverter tested here. Many types of solar inverter designs, including those for residential, commercial, and utility‑scale applications, can benefit from this simple yet effective delay compensation. The ability to maintain stable operation under varying grid impedances is especially valuable for weak grids, which are becoming more common as renewable penetration increases.
Conclusions
In this paper we have presented a robust active damping control method for LC‑type grid‑connected inverters based on double‑sampling delay compensation. By acquiring the PCC voltage at both the valley and peak of the carrier wave within the same switching cycle, we construct a 1.5‑step lead signal that compensates the digital control delay. The key findings are summarized as follows:
- The equivalent positive damping range of the PCC voltage feedforward is extended from \(f_{swi}/3\) to approximately \(0.48 f_{swi}\), effectively eliminating the negative damping region that causes instability.
- The proposed method requires no complex parameter tuning and imposes relaxed timing constraints compared to real‑time computation approaches, making it suitable for plug‑and‑play implementation.
- Experimental hardware‑in‑the‑loop results confirm that the inverter remains stable for grid inductances ranging from 25 µH to 180 µH, while the uncompensated system becomes unstable at low inductance. The LCL resonance harmonic is suppressed to below 0.3% even in the worst case.
- Dynamic performance is excellent, with a settling time of 4 ms and overshoot less than 10% during load steps.
The proposed approach is generic and can be readily adapted to various types of solar inverter topologies, including single‑phase, three‑phase, and multi‑level inverters, thereby enhancing the grid‑connection robustness of distributed generation systems.