In a DC microgrid, renewable energy sources such as wind and photovoltaic power are widely integrated into distributed generation systems. Energy storage batteries and supercapacitors serve as the core energy storage units within these distributed systems, playing a vital role in balancing power fluctuations and ensuring grid stability. The bidirectional DC‑DC converter acts as the interface between the distributed generation system and the energy storage battery, enabling energy to flow in both directions. Efficient and robust control of this converter is essential to enhance the stability and dynamic response of the entire system. Multi-phase interleaved parallel bidirectional DC‑DC converters have been increasingly adopted due to their advantages of low switch current stress, reduced switching losses, and high power density. However, the parasitic parameters among the parallel phases are never perfectly identical, leading to unbalanced inductor currents. This imbalance causes uneven current stress on the switches, potentially damaging the devices with higher stress and eventually causing the whole parallel system to fail. Therefore, developing a control strategy that can achieve fast current sharing, low output ripple, high reliability, and robust dynamic performance for the energy storage battery interface is of great importance.
Many scholars have proposed various current‑sharing control methods for multi-phase interleaved converters. Traditional PI dual‑loop control suffers from slow response, poor robustness, and complicated parameter tuning. Some methods rely on duty‑cycle assignment using neural‑network‑based active disturbance rejection control, but the algorithm complexity is high and only steady‑state performance is considered. Other approaches use parasitic resistance compensation or loop‑shaping, but the dynamic current‑sharing performance is limited. More recently, PI‑Model Predictive Control (PI‑MPC) has been applied to two‑phase interleaved converters, showing improved closed‑loop performance, yet the computational burden is high and the anti‑interference ability and current‑sharing accuracy still need enhancement.
To address these issues, we propose a sliding mode control and model predictive control (SMC‑MPC) based current‑sharing strategy for a three‑phase interleaved parallel bidirectional Buck‑Boost converter used in energy storage battery systems. The voltage outer loop adopts sliding mode control to improve robustness and response speed, while the current inner loop uses model predictive control to achieve precise duty‑cycle compensation for each phase. The proposed method is validated by both simulation and experiments on a 500 W prototype.
First, we analyze the topology and characteristics of the three‑phase interleaved parallel bidirectional Buck‑Boost converter. In Boost mode, energy flows from the input side (energy storage battery) to the output side (DC bus), with switches S1, S3, S5 operating with 120° phase shift. In Buck mode, energy flows from the output side to the input side, with switches S2, S4, S6 active. The converter has eight operating modes under full duty‑cycle range. The input current ripple and output voltage ripple expressions for different duty‑cycle intervals are summarized in Table 1.
| Mode | Duty‑cycle range | Input current ripple | Output voltage ripple |
|---|---|---|---|
| Boost | \(0<D_{\mathrm{Boost}}<\frac{1}{3}\) | \(\Delta i_{\mathrm{in}}=\frac{U_o D_{\mathrm{Boost}} T_s (1-3D_{\mathrm{Boost}})}{L}\) | \(\Delta u_{C2}=\frac{U_o D_{\mathrm{Boost}} T_s (1-3D_{\mathrm{Boost}})}{3RC_2(1-D_{\mathrm{Boost}})}\) |
| \(\frac{1}{3}\le D_{\mathrm{Boost}}\le\frac{2}{3}\) | \(\Delta i_{\mathrm{in}}=\frac{U_o T_s (3-1-2D_{\mathrm{Boost}})(2D_{\mathrm{Boost}}-1)}{3L}\) | \(\Delta u_{C2}=\frac{U_o T_s (3-1-2D_{\mathrm{Boost}})(2D_{\mathrm{Boost}}-1)}{9RC_2(1-D_{\mathrm{Boost}})}\) | |
| \(\frac{2}{3}<D_{\mathrm{Boost}}\le 1\) | \(\Delta i_{\mathrm{in}}=\frac{U_o T_s (1-3-2D_{\mathrm{Boost}})(D_{\mathrm{Boost}}-1)}{L}\) | \(\Delta u_{C2}=\frac{U_o T_s (3-2D_{\mathrm{Boost}})}{3RC_2}\) | |
| Buck | \(0<D_{\mathrm{Buck}}<\frac{1}{3}\) | \(\Delta i_o=\frac{U_o D_{\mathrm{Buck}} T_s (1-3D_{\mathrm{Buck}})}{L}\) | \(\Delta u_{C1}=\frac{U_{\mathrm{in}} T_s^2 D_{\mathrm{Buck}} (1-3D_{\mathrm{Buck}})}{24C_1L}\) |
| \(\frac{1}{3}\le D_{\mathrm{Buck}}\le\frac{2}{3}\) | \(\Delta i_o=\frac{U_o T_s (3-1-2D_{\mathrm{Buck}})(2D_{\mathrm{Buck}}-1)}{3L}\) | \(\Delta u_{C1}=\frac{U_{\mathrm{in}} T_s^2 D_{\mathrm{Buck}} (3-1-2D_{\mathrm{Buck}})(2D_{\mathrm{Buck}}-1)}{36C_1L D_{\mathrm{Buck}}}\) | |
| \(\frac{2}{3}<D_{\mathrm{Buck}}\le 1\) | \(\Delta i_o=\frac{U_o T_s (1-3-2D_{\mathrm{Buck}})(D_{\mathrm{Buck}}-1)}{L}\) | \(\Delta u_{C1}=\frac{U_{\mathrm{in}} T_s^2 D_{\mathrm{Buck}} (1-3-2D_{\mathrm{Buck}})(D_{\mathrm{Buck}}-1)}{24C_1L D_{\mathrm{Buck}}}\) |
To simplify the modeling, we derive the continuous state‑space equations for a single‑phase Buck‑Boost converter. For Boost mode, when main switch S1 is on, the equations are:
$$
\frac{\mathrm{d} i_{L1}}{\mathrm{d}t} = 0 \cdot i_{L1} + 0 \cdot u_o + \frac{1}{L_1} U_{\mathrm{in}},\quad
\frac{\mathrm{d} u_o}{\mathrm{d}t} = 0 \cdot i_{L1} – \frac{1}{R C_2} u_o + 0 \cdot U_{\mathrm{in}}.
$$
When S1 is off, with the freewheeling diode conducting:
$$
\frac{\mathrm{d} i_{L1}}{\mathrm{d}t} = 0 \cdot i_{L1} – \frac{1}{L_1} u_o + \frac{1}{L_1} U_{\mathrm{in}},\quad
\frac{\mathrm{d} u_o}{\mathrm{d}t} = \frac{1}{C_2} i_{L1} – \frac{1}{R C_2} u_o.
$$
Discretizing these equations with sampling period \(T_s\) yields the discrete state‑space model. For Boost mode:
$$
i_{L1}(k+1) = i_{L1}(k) + \frac{(1-D_{\mathrm{Boost1}}(k)) T_s}{L_1} u_o(k) + \frac{T_s}{L_1} U_{\mathrm{in}}(k),
$$
$$
u_o(k+1) = \frac{(1-D_{\mathrm{Boost1}}(k)) T_s}{C_2} i_{L1}(k) + \left(1 – \frac{T_s}{R C_2}\right) u_o(k).
$$
Similarly, for Buck mode:
$$
i_{L1}(k+1) = i_{L1}(k) – \frac{D_{\mathrm{Buck1}}(k) T_s}{L_1} U_{\mathrm{in}}(k) + \frac{T_s}{L_1} u_o(k),
$$
$$
u_{\mathrm{in}}(k+1) = \frac{T_s}{C_1} i_{L1}(k) + \left(1 – \frac{T_s}{R C_1}\right) u_{\mathrm{in}}(k).
$$
Based on these discrete models, we design the sliding mode control for the voltage outer loop. The sliding surface \(S\) is chosen as:
$$
S = \sum_{m=1}^{3} \Delta_1 (i_{\mathrm{ref}} – i_{Lm}) + \Delta_2 (U_{\mathrm{oref}} – U_o) + \Delta_3 \int (U_{\mathrm{oref}} – U_o + i_{\mathrm{ref}} – i_{Lm}) \mathrm{d}t,
$$
where \(\Delta_1, \Delta_2, \Delta_3\) are positive sliding coefficients. From \(S=0\), the reference inductor current for each phase can be derived as:
$$
i_{\mathrm{ref}}(t) = \frac{1}{\Delta_1} \left[ \Delta_2 (U_{\mathrm{oref}} – U_o) + \Delta_3 \int (U_{\mathrm{oref}} – U_o) \mathrm{d}t \right] – \sum_{m=1}^{3} i_{Lm}(t).
$$
For the current inner loop, we adopt model predictive control. The objective function to minimize is:
$$
Q = \left[ u_o(k+1) – U_{\mathrm{oref}} \right]^2 + \left[ i_{L1}(k+1) – i_{\mathrm{ref}} \right]^2.
$$
Substituting the discrete state equations into \(Q\) and taking the derivative with respect to the duty cycle \(D_{\mathrm{Boost1}}(k)\) yields the optimal duty cycle that minimizes \(Q\). After simplification and elimination of the load resistance \(R\) by using \(R = U_o / i_o\), the optimal duty cycle for Boost mode phase 1 is:
$$
\begin{aligned}
D_{\mathrm{Boost1}}(k) = &\frac{U_o(k) i_{L1}(k) C_2 L_1 – C_2 L_1}{C_2 U_o(k) T_s} + \frac{C_2 L_1 U_o(k) i_{\mathrm{ref}} – C_2 L_1 i_{L1}(k) U_{\mathrm{oref}}}{C_2 U_o(k) T_s} \\
&+ \frac{C_2 T_s U_o(k) U_{\mathrm{in}}(k)}{C_2 U_o(k) T_s}.
\end{aligned}
$$
Similar expressions for phase 2 and phase 3 can be written by replacing subscript 1 with 2 or 3. For Buck mode, the optimal duty cycles are:
$$
D_{\mathrm{Buck1}}(k) = \frac{L_1 i_{\mathrm{ref}} – L_1 i_{L1}(k) + T_s U_{\mathrm{in}}(k)}{U_o(k) T_s}.
$$
The overall control block diagram is shown conceptually. The outer loop sliding mode controller generates the reference inductor current, and the inner loop model predictive controller determines the optimal duty cycle for each phase. A modified maximum current sharing module adjusts the reference by feeding back the steady‑state current error among phases, thereby achieving balanced inductor currents.
We built a simulation platform using Matlab/Simulink with the parameters listed in Table 2. The sampling frequency is 20 kHz, and the control step is 0.05 s. For comparison, a PI‑MPC control strategy was also implemented with PI gains \(K_p = 0.1\), \(K_i = 20\).
| Parameter | Value |
|---|---|
| Input voltage \(U_{\mathrm{in}}\) | 10 – 40 V |
| Output voltage \(U_o\) | 50 V |
| Inductors \(L_1, L_2, L_3\) | 0.82 mH, 0.8 mH, 0.78 mH |
| Parasitic resistances \(R_1, R_2, R_3\) | 0.08 Ω, 0.10 Ω, 0.12 Ω |
| Capacitors \(C_1, C_2\) | 470 μF |
| Switching frequency \(f_s\) | 20 kHz |
Simulation results demonstrate that the proposed SMC‑MPC strategy significantly reduces overshoot and improves current‑sharing accuracy compared to PI‑MPC. Table 3 summarizes the comparison at a duty cycle of 0.5 in both Boost and Buck modes.
| Control method | Operating mode | Overshoot (%) | Settling time (ms) | Current‑sharing error (%) |
|---|---|---|---|---|
| PI‑MPC | Buck | 32.8 | 13 | 3.56 |
| PI‑MPC | Boost | 30.3 | 15 | 2.37 |
| SMC‑MPC | Buck | — | 5 | 2.69 |
| SMC‑MPC | Boost | — | 5 | 1.98 |
In Boost mode, the overshoot is reduced by 30.3%, settling time by 66.7%, and current imbalance by 16.5%. In Buck mode, the improvements are 32.8%, 61.5%, and 24.4% respectively.
We also tested the dynamic response under load step changes. In Boost mode, a load perturbation from 20 Ω to 10 Ω and back was applied at 0.05 s and 0.1 s. The SMC‑MPC controlled converter recovered to steady state within a few milliseconds with negligible overshoot, while the PI‑MPC controller exhibited a significant deviation and longer settling time. The output voltage waveform remained stable under SMC‑MPC, confirming the enhanced robustness.
An experimental prototype rated at 500 W was built using IRF3205PBF MOSFETs, a TMS320F28335 DSP controller, and Hall sensors for current measurement. Table 4 lists the prototype parameters.
| Parameter | Value |
|---|---|
| Input voltage \(U_{\mathrm{in}}\) | 10 – 48 V |
| Output voltage \(U_o\) | 48 V |
| Switching frequency \(f_s\) | 20 kHz |
| Inductors \(L_1, L_2, L_3\) | 0.90 mH |
| Input/output capacitors \(C_1, C_2\) | 470 μF |
Figure 1 in the source paper shows the experimental setup. The proposed SMC‑MPC strategy was tested under closed‑loop operation. In Boost mode with duty cycle 0.3, the three‑phase inductor currents measured with PI‑MPC gave a maximum current‑sharing error of 4%, whereas with SMC‑MPC the error reduced to 2%. In Buck mode with duty cycle 0.7, PI‑MPC yielded a 4% error, while SMC‑MPC achieved only 1% error. These results confirm the superior steady‑state current‑sharing accuracy of the proposed method.
Dynamic experiments were also conducted. In Buck mode, the load was stepped between 0.4 Ω and 0.8 Ω. The three inductor currents responded swiftly and remained balanced during and after the transient. In Boost mode, load steps between 20 Ω and 10 Ω showed similar fast recovery. A comparative dynamic test in Buck mode with load change from 2.4 Ω to 1.2 Ω and back is summarized in Table 5. The SMC‑MPC strategy exhibited zero overshoot, a settling time of only 0.4 ms, and a current‑sharing error of 2%, whereas PI‑MPC exhibited 11.5% overshoot, 50 ms settling time, and 4% error.
| Control strategy | Overshoot (%) | Minimum settling time (ms) | Current‑sharing error (%) |
|---|---|---|---|
| SMC‑MPC | 0 | 0.4 | 2 |
| PI‑MPC | 11.5 | 50 | 4 |
In conclusion, the proposed SMC‑MPC current‑sharing control strategy for the three‑phase interleaved parallel bidirectional Buck‑Boost converter used in energy storage battery systems offers significant advantages over the traditional PI‑MPC method. The final controller parameters depend only on the converter passive components, simplifying tuning. Under full duty‑cycle range in both Boost and Buck modes, the strategy achieves excellent current‑sharing accuracy and balances the current stress among phases. Moreover, during load disturbances, the system recovers rapidly with minimal overshoot, demonstrating strong robustness. The energy storage battery interface benefits from improved efficiency, reliability, and dynamic performance. Future work can explore extending the strategy to higher‑phase interleaved converters and integrating it with battery management algorithms for enhanced system‑level optimization.
