The proliferation of grid-connected photovoltaic (PV) systems has ushered in an era where renewable energy constitutes a significant portion of the power supply. This integration, however, introduces challenges related to grid stability due to the inherent variability of solar power generation, influenced by diurnal and seasonal cycles. To mitigate these impacts and ensure reliable grid operation, the ability to actively dispatch and regulate the output of PV plants is paramount. Central to this capability is the solar inverter, the intelligent core that converts DC power from PV arrays into grid-compliant AC power. Modern high-power solar inverters increasingly rely on high-performance Digital Signal Processors (DSPs) for critical tasks like real-time maximum power point tracking (MPPT), sophisticated pulse-width modulation (PWM) control, and system management. While DSPs excel in computational speed and digital signal processing, a common limitation in many such processors is the lack of dedicated, robust asynchronous serial communication interfaces, which are essential for command-and-control networks within a power plant.
This communication gap becomes a critical bottleneck for implementing advanced functions like real-time active (P) and reactive (Q) power dispatching. A dispatch center must be able to send setpoint commands to individual solar inverters swiftly and reliably. This article presents a detailed engineering solution to this problem by employing an external Universal Asynchronous Receiver/Transmitter (UART) chip, the TL16C752, interfaced with a TMS320VC33 DSP. This architecture facilitates high-reliability, real-time communication for power dispatching in a 500kW grid-connected solar inverter, effectively bridging the gap between the high-speed DSP and the lower-speed plant communication bus.
The fundamental architecture for dispatching power in a PV plant involves a hierarchical communication structure. At the top, a remote dispatch center generates power setpoint commands based on grid requirements. These commands are transmitted via the plant’s backbone communication network to a local data concentrator or human-machine interface (HMI) station, often located within the inverter station. This local station acts as a protocol gateway and may provide a local interface for manual control and monitoring. Finally, the dispatching commands are delivered to the individual solar inverter control boards via a robust, industry-standard RS-485 serial bus. It is at this final link—between the plant network gateway and the inverter’s internal DSP controller—that the need for a reliable asynchronous serial port is most acute. The solar inverter must not only execute complex control algorithms but also remain responsive to external dispatch commands without performance degradation.
The core of the proposed solution lies in the hardware interface between the DSP and the TL16C752 dual UART. The TMS320VC33 DSP utilizes its External Memory Interface (EMIF) for communication with peripherals. The TL16C752, with its 8-bit parallel host interface, is memory-mapped into the DSP’s address space. A Complex Programmable Logic Device (CPLD) serves as the essential glue logic, translating DSP control signals into the precise timing required by the UART chip. Key signal connections include the DSP’s address lines (A0-A2) connected directly to the UART, and the DSP’s read/write signal (R/W) used by the CPLD to generate the TL16C752’s IOR# and IOW# signals. A dedicated chip-select signal for the UART is generated from the DSP’s higher-order address lines via the CPLD.
A critical aspect of this interface is timing management. The TL16C752’s read and write cycle requirements are longer than the default cycle of the high-speed DSP. To resolve this, the CPLD inserts wait states by controlling the DSP’s READY (RDY) input signal during access cycles to the UART’s address range. This ensures that the IOR# or IOW# pulse width meets the minimum specification of the TL16C752, which is typically two cycles of its input clock (CLK). Given a common UART clock of 1.8432 MHz, the minimum pulse width required is approximately 1.085 μs. The CPLD logic extends the DSP’s cycle to meet this requirement, guaranteeing stable data transfer. The TL16C752’s independent transmit (TX) and receive (RX) lines are then connected to RS-485 transceivers, which provide the differential signaling necessary for robust long-distance communication on the plant floor.
The TL16C752 offers significant advantages over simpler UARTs, primarily through its 64-byte deep, configurable FIFOs for both transmission and reception. For a solar inverter handling multiple real-time tasks, this FIFO capability is crucial. It minimizes the DSP’s interrupt overhead by allowing the UART to buffer a substantial amount of data before requiring service. The trigger levels for these FIFOs (e.g., generating an interrupt when 8, 16, 32, or 56 bytes are present) are software-programmable via the FIFO Control Register (FCR). This allows the system designer to tune the balance between response latency and interrupt frequency to best suit the solar inverter‘s real-time control loop. The device also provides comprehensive line status information (overrun, parity, framing errors) via the Line Status Register (LSR), enhancing communication robustness.
Configuring the TL16C752 involves writing to a set of internal registers mapped to the base address assigned by the DSP/CPLD logic. A typical register map for one of its two channels is summarized below:
| Address Offset (A2:A0) | Register Mnemonic | Function (When DLAB=0) |
|---|---|---|
| 000 | RHR / THR | Receiver Hold Register (Read), Transmitter Holding Register (Write) |
| 001 | IER | Interrupt Enable Register |
| 010 | IIR / FCR | Interrupt Identification Register (Read), FIFO Control Register (Write) |
| 011 | LCR | Line Control Register (Data Format, DLAB bit) |
| 100 | MCR | Modem Control Register |
| 101 | LSR | Line Status Register |
| 110 | MSR | Modem Status Register |
| 111 | SCR | Scratch Register |
When the Divisor Latch Access Bit (DLAB) in the LCR is set to 1, offsets 000 and 001 map to the Divisor Latch registers (DLL and DLM) for baud rate generation. The baud rate is calculated based on the input clock and a 16x oversampling scheme:
$$ \text{Baud Rate} = \frac{\text{UART Input Clock Frequency}}{16 \times \text{Divisor}} $$
For example, with a 1.8432 MHz clock and a desired baud rate of 38,400, the divisor is calculated as:
$$ \text{Divisor} = \frac{1.8432 \times 10^6}{16 \times 38400} = 3 $$
Thus, the value 3 would be loaded into the 16-bit divisor latch (DLL=0x03, DLM=0x00).
The software architecture within the solar inverter‘s DSP is designed for deterministic operation. Given the high computational load of inverter control, a polled (non-interrupt) approach for UART communication is often employed within a timer interrupt service routine (ISR) that runs at a fixed, known period. This provides predictable timing and avoids the potential jitter associated with asynchronous communication interrupts in a hard real-time system. The software flow for receiving a dispatching command is as follows:
1. Initialization: After system reset, the DSP software configures the TL16C752. This involves setting the LCR to access the divisor latches (DLAB=1), writing the baud rate divisor values, then clearing DLAB and setting the data frame format (e.g., 8 data bits, 1 stop bit, no parity). Finally, the FIFO Control Register (FCR) is written to enable and set the trigger level for the RX FIFO.
2. Polling Routine: Periodically, within a timer ISR, the software reads the Line Status Register (LSR).
3. Error Checking: It checks for critical errors (Bit 1: Overrun Error, Bit 2: Parity Error, Bit 3: Framing Error, Bit 4: Break Indicator). If an error is detected, the software initiates a recovery sequence, which typically involves reading the Receiver Buffer Register to flush the faulty data and resetting the FIFO.
4. Data Available Check: If no errors are present, it checks LSR Bit 0 (Data Ready). If set, it indicates at least one byte is available in the RX FIFO.
5. Data Read & Protocol Assembly: The software reads a byte from the RHR. It then assembles incoming bytes into a frame based on the Modbus RTU protocol rules.
6. Frame Validation: Once a complete frame is received (determined by byte count or a inter-character silence timeout), a Cyclical Redundancy Check (CRC) calculation is performed on the message and compared to the received CRC. The Modbus RTU CRC is based on a 16-bit polynomial:
$$ \text{CRC-16} = x^{16} + x^{15} + x^2 + 1 $$
7. Command Execution: If the CRC matches, the frame is valid. The DSP decodes the function code and data fields. For power dispatching, the relevant data is extracted and used to update the internal active and reactive power setpoints for the inverter’s control algorithms.
8. Response: Acknowledgment or response is sent back to the master device by writing data to the TL16C752’s Transmitter Holding Register (THR), utilizing the TX FIFO.
The Modbus RTU protocol is widely adopted in industrial automation, including PV plant communications, due to its simplicity and efficiency. For power dispatching to a solar inverter, a typical command uses the “Preset Multiple Registers” function (code 0x10). This function allows the master to write values to a contiguous block of holding registers in the inverter slave device. The structure of such a command and its corresponding response are detailed below:
| Field | Example Bytes | Description for a Power Dispatch Command |
|---|---|---|
| Slave Address | 0x02 | Unique identifier for the target solar inverter. |
| Function Code | 0x10 | “Preset Multiple Registers”. |
| Starting Address Hi | 0x00 | High byte of the first register to write to. |
| Starting Address Lo | 0xD3 | Low byte (e.g., register address 0x00D3 = Decimal 211). |
| Quantity of Regs Hi | 0x00 | High byte of the number of registers to write. |
| Quantity of Regs Lo | 0x05 | Low byte (e.g., write 5 registers). |
| Byte Count | 0x0A | Number of data bytes to follow (2 x Quantity of Registers). |
| Data Register 1 (Hi) | 0x00 | Remote Control Enable (0=Disable, 1=Enable). |
| Data Register 1 (Lo) | 0x01 | |
| Data Register 2 (Hi) | 0x00 | Reactive Power Dispatch Enable (0=Disable, 1=Enable). |
| Data Register 2 (Lo) | 0x01 | |
| Data Register 3 (Hi) | 0x00 | Power Factor Setpoint (e.g., 95 for 0.95 lead/lag). |
| Data Register 3 (Lo) | 0x5F | (0x5F = Decimal 95) |
| Data Register 4 (Hi) | 0x00 | Phase Command (0=Current Leads Voltage, 1=Current Lags). |
| Data Register 4 (Lo) | 0x00 | |
| Data Register 5 (Hi) | 0x00 | Active Power Setpoint (0-100% of rated power). |
| Data Register 5 (Lo) | 0x32 | (0x32 = Decimal 50, meaning 50%) |
| CRC Lo | 0x2B | Low byte of the calculated CRC. |
| CRC Hi | 0x93 | High byte of the calculated CRC. |
Upon successful processing, the solar inverter responds with an echo of the header (Address, Function Code, Starting Address, Quantity of Registers), confirming the write operation.
The efficacy of this communication architecture was validated on a 500kW grid-connected solar inverter prototype. A local HMI station was used to simulate the remote dispatch center, sending Modbus RTU commands via the RS-485 link to the inverter’s control board equipped with the TMS320VC33 and TL16C752. A serial port monitor confirmed the accurate transmission and reception of the data frames as described in the table above. When a dispatch command set the active power to 50%, the inverter’s output power stabilized at approximately 250kW, demonstrating successful active power regulation. For reactive power testing, with the reactive dispatch enabled, a power factor setpoint of 0.95 leading was commanded. Measurements showed the output current phase angle leading the grid voltage phase angle by approximately 18 degrees, confirming that the solar inverter was successfully injecting reactive power according to the dispatched command while simultaneously delivering active power. These tests were conducted under various grid conditions, and the communication link remained stable without causing faults or performance degradation in the core inverter control loops, proving the real-time capability and reliability of the solution.
In conclusion, the integration of the TL16C752 high-performance UART with a modern DSP via flexible CPLD logic presents a highly effective solution for a critical challenge in advanced PV plant operation. It enables reliable, real-time bidirectional communication necessary for grid-support functions like active and reactive power dispatching. This architecture successfully decouples the high-speed demands of switching control in a solar inverter from the timing requirements of industrial fieldbus communication. By leveraging deep FIFOs and programmable features of the TL16C752, the DSP can service the communication port efficiently, often through simple polling within a deterministic control loop, ensuring that dispatch commands are processed with minimal latency and high reliability. This design pattern is scalable and applicable to a wide range of power conversion systems where robust external communication is required alongside complex real-time digital control.