As the global energy transition accelerates, solar inverters have become the key interface between photovoltaic modules and AC loads. In my design, I treat the solar array and its DC-DC stage as a regulated DC source and concentrate on the DC-AC stage and its parallel operation. A single solar inverter is often limited by device ratings, thermal constraints, and reliability. Parallel operation of solar inverters increases capacity, improves redundancy, and allows modular expansion. However, parallel solar inverters introduce circulating currents and power-sharing errors. This article describes my design of a single-phase solar inverter parallel operation system, including modeling, control, hardware, software, and experiments.
1. Motivation and Scope
I began with the observation that modern energy consumption is large, conventional resources are limited, and environmental constraints are severe. Solar power is clean, flexible, and widely distributed. Solar inverters convert the DC output of photovoltaic panels into AC power for loads or grids. In many practical systems, one solar inverter is not enough. The single-unit capacity is limited, and a failure can interrupt the whole supply. Therefore, I study parallel operation of solar inverters to achieve capacity expansion, redundant operation, and flexible scheduling.
The main challenge is that parallel solar inverters are not ideal voltage sources. Differences in output impedance, phase, and amplitude cause circulating current. This current increases losses, distorts waveforms, and may lead to uneven power sharing. My work addresses these issues through a single-inverter double-loop controller, a virtual-impedance improved droop controller, and a local pre-synchronization scheme based on a second-order generalized integrator phase-locked loop. I verify the design through simulation and a prototype platform.
2. Single Solar Inverter Modeling
2.1 Main Circuit Topology Selection
I compared three common single-phase topologies for solar inverters: half-bridge, full-bridge, and push-pull. The comparison is summarized in the following table.
| Topology | Advantages | Disadvantages | Typical Use |
|---|---|---|---|
| Half-bridge | Simple structure, low cost, good disturbance rejection with large split capacitors | Output amplitude is only half of DC input, lower utilization, larger ripple | Low-cost low-power solar inverters |
| Full-bridge | Double output amplitude, high DC utilization, low THD, good for higher power | More switches, more complex drive and control | Industrial solar inverters, medium and high power |
| Push-pull | Simple drive, suitable for low-voltage DC input, voltage gain | Magnetic saturation risk, poor utilization of transformer core, limited inductive load capability | Small off-grid solar inverters below several hundred watts |
Because I need stable operation, high conversion efficiency, and good output quality, I selected the full-bridge topology for my solar inverters. It provides bipolar symmetric drive and can handle input voltage variations and nonlinear loads better than the half-bridge and push-pull alternatives.
2.2 Filter Design
I evaluated L, LC, and LCL filters. The comparison is shown below.
| Filter | Advantages | Disadvantages |
|---|---|---|
| L | Simple, low cost, easy control | Large inductance needed, bulky, high switching loss for low THD |
| LC | Good harmonic attenuation, economical, simple design | Capacitor may introduce phase shift in grid-tied operation |
| LCL | Excellent high-frequency attenuation | Resonance risk, complex design, needs damping |
I chose the LC filter for the single-phase solar inverters because it balances filtering performance, stability, and cost.
For the LC filter, I used the rated current ripple coefficient \(\alpha\). The maximum ripple current is
\[
\Delta I_L = \alpha I_{\max}
\]
During one switching period, the ripple current can be expressed as
\[
\Delta I_L = \frac{U_{DC}-u_o(t)}{L}\frac{D(t)}{f_s}
\]
where \(D(t)\) is the switching function and \(f_s\) is the switching frequency. Since the switching frequency is much higher than the fundamental frequency,
\[
u_o(t) = D(t)U_{DC}
\]
Substituting and simplifying gives
\[
\Delta I_L = \frac{U_{DC}-u_o(t)}{L}\frac{u_o(t)}{f_s U_{DC}}
\]
The maximum ripple occurs around \(u_o(t)=U_{DC}/2\):
\[
\Delta I_{L,\max} = \frac{U_{DC}}{4L f_s}
\]
Therefore, the minimum inductance is
\[
L \ge \frac{U_{DC}}{4 f_s \Delta I_{L,\max}}
\]
The maximum inductance is limited by the allowed voltage drop:
\[
L \le \frac{0.05U}{\omega I}
\]
The resonance frequency is
\[
f_k = \frac{1}{2\pi\sqrt{LC}}
\]
I set \(f_k = 1.5\,\mathrm{kHz}\), which satisfies \(10 f_n \le f_k \le f_s/5\). This gives the filter capacitor value.
2.3 Equivalent Model of One Solar Inverter
I modeled the solar inverter as a controlled voltage source behind an LC filter. The KCL and KVL equations in the \(s\)-domain are
\[
(Ls+r)i_L = u_i – u_o
\]
\[
(i_L – i_o)\frac{1}{Cs} = u_o
\]
Using state-space averaging, the inverter output can be written as
\[
u_i = K_{pwm}u_{ref}
\]
\[
K_{pwm} = \frac{E}{U_{pt}}
\]
where \(E\) is the equivalent DC bus voltage and \(U_{pt}\) is the triangular carrier amplitude. This model is used for the current inner loop and voltage outer loop design.
3. Modulation Strategy for Solar Inverters
I compared unipolar and bipolar SPWM. The results are summarized below.
| Modulation | Output Levels | Harmonic Performance | Control Complexity | Switching Loss |
|---|---|---|---|---|
| Unipolar SPWM | Three-level-like output | Lower THD | Higher, sensitive to phase matching | Lower |
| Bipolar SPWM | Two-level output | Higher THD | Simpler | Higher |
For my solar inverters, I selected unipolar SPWM because it gives better harmonic suppression and lower ripple. The increased control complexity is acceptable because I use a digital signal controller with sufficient computation capability.
4. Single Solar Inverter Control Strategy
4.1 Double Closed-Loop Structure
I adopted a voltage-current double closed-loop control structure. The outer loop regulates the capacitor voltage, and the inner loop regulates the inductor current. Compared with a single current loop, the double-loop structure improves dynamic disturbance rejection and steady-state accuracy. The inductor current is used as the inner-loop feedback because it provides better signal-to-noise ratio and natural overcurrent protection. I also added an output voltage feedforward path to reduce the coupling effect and simplify the controller design.
4.2 Current Inner Loop Design
I used a proportional-integral controller for the current inner loop:
\[
G_i(s) = k_{pi} + \frac{k_{ii}}{s}
\]
The open-loop transfer function is
\[
G_{op}(s) = \frac{k_{pi}s + k_{ii}}{s}\frac{1}{Ls+r}
\]
The closed-loop transfer function is
\[
G_{cl}(s) = \frac{k_{pi}s + k_{ii}}{Ls^2 + (r+k_{pi})s + k_{ii}}
\]
From the Bode analysis, increasing the integral coefficient did not improve the steady-state and tracking performance significantly. Large integral gain could even cause resonance. Therefore, I set \(k_{ii}=0\). The current loop then becomes a proportional controller. I selected the current-loop crossover frequency at about one tenth of the switching frequency. With \(f_s=20\,\mathrm{kHz}\), I chose \(2\,\mathrm{kHz}\). Solving the magnitude condition gives
\[
20\log k_{pi} – 20\log\sqrt{(r+k_{pi})^2 + L^2\omega^2} = -3\,\mathrm{dB}
\]
This yields \(k_{pi}=0.3\).
4.3 Voltage Outer Loop Design
For the voltage outer loop, a conventional PI controller cannot achieve zero steady-state error for an AC reference. Therefore, I used a quasi-proportional-resonant controller. The ideal PR controller is
\[
G_u(s) = k_{pu} + \frac{2k_{ru}s}{s^2+\omega_0^2}
\]
The ideal PR controller has infinite gain at the fundamental frequency, but it is sensitive to frequency drift. To improve robustness, I used the quasi-PR form:
\[
G_{QPR}(s) = k_{pu} + \frac{2k_{ru}\omega_c s}{s^2+2\omega_c s+\omega_0^2}
\]
where \(\omega_0\) is the fundamental angular frequency and \(\omega_c\) is the cutoff frequency. The bandwidth is
\[
\Delta\omega = 2\omega_c
\]
For an allowed frequency variation of \(\Delta f\),
\[
\omega_c = \pi \Delta f
\]
I tuned \(k_{pu}\) mainly for proportional gain, \(k_{ru}\) for peak gain and steady-state error, and \(\omega_c\) for bandwidth. The selected values are listed in the control parameter table.
4.4 Discrete Implementation of Quasi-PR Control
I implemented the quasi-PR controller in a digital signal controller. The discrete equations are
\[
y_k = y_{k-1} + \omega_c T_s (x_{k-1} – m_{k-1} – n_{k-1})
\]
\[
m_k = m_{k-1} + \frac{\omega_0^2}{\omega_c} T_s y_k
\]
\[
n_k = y_k
\]
\[
q = k_{pu}x + k_{ru}y
\]
This form is suitable for real-time execution in the interrupt service routine.
4.5 Simulation of One Solar Inverter
I built a simulation model of one solar inverter. The main circuit and control parameters are given below.
| Parameter | Value |
|---|---|
| DC voltage amplitude \(E\) | 40 V |
| Filter inductance \(L\) | 1.2 mH |
| Equivalent resistance \(r\) | 0.1 \(\Omega\) |
| Filter capacitance \(C\) | 6.9 \(\mu\)F |
| Switching frequency \(f_s\) | 20 kHz |
| Output voltage RMS \(u_o\) | 24 V |
| Load resistance \(R_L\) | 12 \(\Omega\) |
| Control Parameter | Value |
|---|---|
| Reference amplitude | 34 V |
| Current inner loop \(k_{pi}\) | 0.3 |
| Voltage outer loop \(k_{pu}\) | 0.1 |
| Voltage outer loop \(k_{ru}\) | 45 |
| Cutoff coefficient \(\omega_c\) | \(\pi\) |
The simulation showed that the improved QPR control tracks the reference with much smaller error than conventional PI control. Under no-load conditions, the output voltage remained a 50 Hz sine wave with 34 V peak. Under rated resistive load, voltage and current were in phase. The total harmonic distortion of the output voltage was about \(1.05\%\), which is well below the \(5\%\) limit. During load switching, the output voltage dropped by about \(0.4\) V and recovered quickly, with frequency variation within \(0.5\) Hz. These results confirm that my single solar inverter design meets the dynamic and steady-state requirements.
5. Parallel Operation of Solar Inverters
5.1 Equivalent Model and Circulating Current
I modeled two parallel solar inverters as two controlled voltage sources behind output impedances. The equations are
\[
\dot E_1 – Z_1 \dot I_1 = \dot U_L
\]
\[
\dot E_2 – Z_2 \dot I_2 = \dot U_L
\]
\[
\dot I_1 + \dot I_2 = \dot I_o
\]
\[
\dot I_o = \frac{\dot U_L}{Z_L}
\]
If the two solar inverters have the same output impedance \(Z_1=Z_2=Z\), then
\[
\dot I_1 = \frac{\dot U_L}{2Z_L} + \frac{\dot E_1 – \dot E_2}{2Z}
\]
\[
\dot I_2 = \frac{\dot U_L}{2Z_L} – \frac{\dot E_1 – \dot E_2}{2Z}
\]
The circulating current is
\[
\dot I_c = \frac{\dot E_1 – \dot E_2}{2Z}
\]
Expanding this expression gives
\[
\dot I_c = \frac{1}{2}\left(\frac{E_1\angle\phi_1 – U_L\angle 0}{Z_1\angle\theta_1} – \frac{E_2\angle\phi_2 – U_L\angle 0}{Z_2\angle\theta_2}\right)
\]
This shows that circulating current is caused by differences in voltage amplitude, phase, and output impedance. In practical solar inverters, cable impedance, switch losses, and filter parameters are not identical. Therefore, parallel solar inverters require a dedicated control strategy.
5.2 Traditional Droop Control
The apparent power of inverter \(i\) is
\[
S_i = \dot E_i \dot I_i^* = P_i + jQ_i
\]
After simplification, the active and reactive powers are
\[
P_i = \frac{U_L[(E_i-U_L)\cos\theta_i + E_i\phi_i\sin\theta_i]}{|Z_i|}
\]
\[
Q_i = \frac{U_L[(E_i-U_L)\sin\theta_i – E_i\phi_i\cos\theta_i]}{|Z_i|}
\]
When the output impedance is purely inductive, \(\theta_i = 90^\circ\), and
\[
P_i = \phi_i \frac{U_L E_i}{X_i}
\]
\[
Q_i = \frac{U_L(E_i-U_L)}{X_i}
\]
Thus, active power is mainly controlled by phase, and reactive power is mainly controlled by voltage amplitude. The traditional droop equations are
\[
\omega = \omega^* – mP
\]
\[
E = E^* – nQ
\]
I selected the droop coefficients according to
\[
0 \le m \le \frac{\Delta f}{P_{\max}}
\]
\[
0 \le n \le \frac{\Delta V}{Q_{\max}}
\]
With the allowed frequency deviation and voltage deviation, I set \(m=0.01\) and \(n=0.03\).
5.3 Local Pre-Synchronization Using SOGI-PLL
Before parallel connection, the voltage amplitude, frequency, and phase of each solar inverter must match the common bus. Direct connection can cause large inrush current. I designed a local pre-synchronization scheme based on a second-order generalized integrator phase-locked loop. The SOGI generates two orthogonal signals:
\[
D(s) = \frac{v_\alpha(s)}{v(s)} = \frac{k\omega’ s}{s^2+k\omega’ s+\omega’^2}
\]
\[
Q(s) = \frac{v_\beta(s)}{v(s)} = \frac{k\omega’^2}{s^2+k\omega’ s+\omega’^2}
\]
Here, \(D(s)\) is a second-order band-pass filter and \(Q(s)\) is a low-pass filter. I chose the damping coefficient \(k=0.9\) to balance bandwidth and filtering. The phase-locked loop uses a PI controller to drive the quadrature component to zero. This gives the phase and frequency of the common bus. The pre-synchronization loop is active only before parallel connection. After synchronization, the control mode switches back to droop control. Therefore, the “no communication” and “plug-and-play” advantages of droop control are preserved.
5.4 Virtual-Impedance Improved Droop Control
Traditional droop control assumes a purely inductive output impedance. In real solar inverters, the output impedance contains resistance, switch losses, and filter effects. To solve this problem, I introduced virtual impedance. The equivalent output impedance becomes
\[
Z_{\mathrm{eq}} = (R+R_v) + j(X+X_v)
\]
The virtual impedance is implemented in software. I used an inductor current feedback path with a second-order generalized integrator to generate a clean virtual inductive drop. The control equation is
\[
u_0(s) = G_{kL}(s)U_{ref}(s) – Z_{kL}(s)I_o(s) – G_{Lv}(s)G_{kL}(s)I_o(s)
\]
where
\[
G_{kL}(s) = \frac{G_v(s)G_i(s)}{Cs(Ls+R)+G_v(s)G_i(s)+G_i(s)Cs}
\]
\[
Z_{kL}(s) = \frac{G_i(s)+Ls+R}{Cs(Ls+R)+G_v(s)G_i(s)+G_i(s)Cs}
\]
\[
G_{Lv}(s) = \frac{k_s L_v \omega_0 s^2}{s^2+k_s \omega_0 s+\omega_0^2}
\]
Adding virtual impedance increases the inductive component at the fundamental frequency and reduces the impact of line impedance mismatch. However, the virtual impedance must not be too large, because it reduces the output voltage and affects control accuracy.
5.5 Power Calculation and Droop Implementation
I calculated active and reactive power using orthogonal signals:
\[
p = u_\alpha i_\alpha + u_\beta i_\beta
\]
\[
q = u_\beta i_\alpha – u_\alpha i_\beta
\]
A low-pass filter removes the double-frequency ripple. The filtered powers are used by the droop controller. The droop controller generates the reference voltage amplitude and frequency, which are combined into the reference voltage for the double closed-loop controller.
5.6 Simulation of Parallel Solar Inverters
I built a two-unit parallel simulation model. The line impedances were intentionally set differently to represent practical mismatch:
| Parameter | Value |
|---|---|
| DC voltage amplitude \(E\) | 40 V |
| Filter inductance \(L\) | 1.2 mH |
| Equivalent resistance \(r\) | 0.1 \(\Omega\) |
| Filter capacitance \(C\) | 6.9 \(\mu\)F |
| Switching frequency \(f_s\) | 20 kHz |
| Output voltage RMS \(u_o\) | 24 V |
| Load resistance \(R_L\) | 12 \(\Omega\) |
| Feeder impedance \(Z_1\) | \(0.1+j0.23\,\Omega\) |
| Feeder impedance \(Z_2\) | \(1+j23\,\mathrm{m}\Omega\) |
| Parallel Control Parameter | Value |
|---|---|
| Reference amplitude | 34 V |
| Current inner loop \(k_{pi}\) | 0.3 |
| Voltage outer loop \(k_{pu}\) | 0.1 |
| Voltage outer loop \(k_{ru}\) | 45 |
| Cutoff coefficient \(\omega_c\) | \(\pi\) |
| Active droop coefficient \(m\) | 0.01 |
| Reactive droop coefficient \(n\) | 0.03 |
| SOGI damping coefficient \(k\) | 0.9 |
| Virtual inductance | 0.3 mH |
In the simulation, the first solar inverter started at \(t=0\), and the second solar inverter was connected at \(t=0.13\,\mathrm{s}\). The output voltage remained a stable sine wave. The frequency was about \(49.7\,\mathrm{Hz}\), and the RMS voltage was about \(23.9\,\mathrm{V}\). The small deviations are consistent with droop control. The THD of the parallel output voltage was about \(3.01\%\), which is below the \(5\%\) limit.
With traditional droop control, the active power of the two solar inverters was shared, but the reactive power difference was about \(17\,\mathrm{Var}\). With the virtual-impedance improved droop control, the reactive power difference dropped to about \(4.3\,\mathrm{Var}\). The output currents also showed smooth transition during parallel connection, with no large inrush current. After synchronization, both currents settled near \(2\,\mathrm{A}\) and remained in phase. These results confirm that the improved droop control and the SOGI-PLL pre-synchronization effectively reduce circulating current and improve power sharing among parallel solar inverters.
6. Hardware Platform Design
I built a prototype platform for the parallel solar inverters. The main components are listed below.
| Module | Selected Device or Method | Purpose |
|---|---|---|
| Main controller | STM32F103ZET6 | Digital control, PWM, ADC, communication |
| Power switches | N-channel MOSFET HY1906P | Full-bridge DC-AC conversion |
| Gate driver | IR2104 half-bridge driver | MOSFET gate drive with dead time |
| Voltage sampling | LM358 differential amplifier and filter | Output voltage feedback |
| Current sampling | LM358 signal conditioning | Inductor current and output current feedback |
| 40 V to 12 V | PW2153 buck controller | Gate driver supply |
| 12 V to 5 V | LM2596 buck regulator | Controller and sensor supply |
The full-bridge inverter uses four MOSFETs. Each leg is driven by an IR2104 with bootstrap capacitor and fast recovery diode. The dead time is generated internally, which simplifies software design. The voltage and current sampling circuits use operational amplifiers with low-pass filtering to remove high-frequency noise. The auxiliary power supply provides stable 12 V and 5 V rails from the DC bus.
7. Software Design
The software runs on the main controller and is divided into a main program and interrupt service routines. The main program initializes the system clock, GPIO, ADC, timers, PWM, and control variables. It also monitors the operating state and coordinates the power calculation and control mode.
The interrupt service routine performs the following tasks:
- Reads the sampled output voltage and current.
- Detects whether the common bus has voltage.
- If the bus is not energized, the inverter enters droop control directly.
- If the bus is energized, the pre-synchronization SOGI-PLL captures phase and frequency.
- After five consecutive locked cycles, the parallel switch is closed.
- After paralleling, the control switches back to droop control.
- The double closed-loop controller updates the duty cycle.
The power calculation module performs a fast Fourier transform on the sampled voltage and current to obtain peak values and phase information. Then it calculates active and reactive power. The droop control module uses these powers to generate the reference voltage amplitude and phase. The reference voltage is then passed to the double-loop controller. The virtual impedance and pre-synchronization functions are integrated into the same control framework.
8. Experimental Results and Analysis
8.1 Single Solar Inverter Experiment
I first tested one solar inverter under rated load. The voltage outer loop used quasi-PR control, and the current inner loop used PI control with output voltage feedforward. The output voltage RMS was \(23.98\,\mathrm{V}\), and the output current RMS was \(2.041\,\mathrm{A}\). The voltage and current were in phase, which matches a resistive load. The output frequency was \(50.01\,\mathrm{Hz}\), and the frequency variation was within \(\pm 0.5\,\mathrm{Hz}\). The voltage THD was \(1.69\%\), well below the \(5\%\) requirement.
8.2 Parallel Solar Inverter Experiment
I then tested two parallel solar inverters. The two units had identical main circuits, filters, drivers, and sampling circuits. I intentionally introduced differences in the output cables to create unequal line impedances. After stable parallel operation, the output voltage was a \(24\,\mathrm{V}\) sine wave, and the output current of each solar inverter settled near \(1\,\mathrm{A}\). The currents had no obvious phase difference and no significant circulating current. A small amount of switching-frequency harmonic remained in the current because of the limited bandwidth of the quasi-PR controller. The overall THD was below \(4.5\%\), which is acceptable for the prototype. The experiment confirms that my improved droop control and local pre-synchronization work effectively for parallel solar inverters.
9. Conclusion and Future Work
I designed and verified a single-phase solar inverter parallel operation system. The main contributions are as follows.
- I selected a full-bridge topology and an LC filter for the solar inverters and derived the parameter design equations.
- I built a double closed-loop controller with a PI current inner loop, a quasi-PR voltage outer loop, and output voltage feedforward.
- I analyzed the circulating current mechanism in parallel solar inverters and proposed a virtual-impedance improved droop control strategy.
- I designed a local SOGI-PLL pre-synchronization method to reduce inrush current during parallel connection.
- I implemented the hardware and software on a prototype platform and validated the design through experiments.
The experimental results show that a single solar inverter has good steady-state accuracy and dynamic response. The parallel solar inverters achieve effective current sharing and reduced circulating current. The improved droop control solves the reactive power sharing problem caused by unequal output impedances.
In future work, I plan to study nonlinear loads, variable solar irradiance, and parameter drift. I also intend to introduce adaptive or intelligent tuning for the virtual impedance and droop coefficients. Extending the method to multiple solar inverters and three-phase systems is another important direction. These improvements will make parallel solar inverters more robust and more suitable for practical solar power supply systems.