In this thesis, I present a thorough investigation into a single-stage non-isolated five-level step-up photovoltaic inverter that is specifically designed to eliminate leakage current while achieving high voltage gain. The research background, topology derivation, operating principles, modulation strategy, steady-state analysis, grid-connected control, hardware design, and experimental validation are all discussed in detail. Throughout this work, I emphasize the application of the proposed solar inverter in photovoltaic grid-connected systems, where issues such as leakage current, discontinuous input current, and limited voltage gain are critical. My objective is to provide a comprehensive solution that combines the advantages of multi-level inverters, common-ground structures, and boost capability in a single conversion stage.
1. Introduction and Background
With the rapid growth of global energy consumption and the increasing depletion of fossil fuels, the development of renewable energy sources has become an urgent task. Solar energy, as a clean and widely distributed renewable resource, has received extensive attention. The photovoltaic (PV) system is one of the most promising technologies for utilizing solar energy. In a PV system, the solar inverter plays a key role in converting the DC power generated by PV panels into AC power that can be fed into the grid or used by local loads. The performance of the solar inverter directly determines the overall efficiency, reliability, and safety of the entire PV system.
Conventional two-level inverters suffer from high voltage stress on switching devices, large output harmonics, and relatively low power density. To overcome these limitations, multilevel inverters have been developed. Among them, the five-level inverter is particularly attractive because it offers a good balance between component count, control complexity, and output waveform quality. The five-level inverter can be implemented using various topologies, such as diode-clamped, flying capacitor, and cascaded H-bridge structures. However, many of these conventional multilevel topologies require multiple DC sources or complex capacitor voltage balancing circuits, which limit their application in photovoltaic systems.
Another important issue for transformerless grid-connected inverters is the common-mode leakage current. In non-isolated PV systems, the parasitic capacitance between the PV array and ground can form a common-mode resonant circuit. High-frequency switching of power devices generates a varying common-mode voltage across this parasitic capacitance, producing a leakage current. This leakage current not only increases system losses but also creates safety hazards and electromagnetic interference. Therefore, suppressing leakage current is a key design challenge for any solar inverter intended for transformerless operation.
Traditional solutions for leakage current suppression include adding an AC-side freewheeling circuit or a DC-side bypass circuit, as in the H6 and HERIC topologies. Although these methods can reduce the leakage current by decoupling the DC and AC sides during freewheeling intervals, they require additional active switches and diodes, increasing the cost and complexity of the system. Moreover, these topologies are usually derived from the full-bridge inverter, which acts as a Buck converter. As a result, the peak AC output voltage is limited by the DC input voltage. For PV applications where the PV module voltage is relatively low, an additional DC-DC boost converter is required, leading to a two-stage system with lower efficiency and higher cost.
To address these issues, I propose a single-stage non-isolated five-level step-up photovoltaic inverter with no leakage current. The proposed inverter is based on a common-ground structure, where the negative terminal of the DC input is directly connected to the neutral point of the AC output. This connection effectively short-circuits the parasitic capacitance and eliminates the common-mode leakage current from the source. In addition, the inverter integrates a boost converter with a diode-clamped five-level bridge, achieving a high voltage gain in a single stage. The proposed solar inverter uses only seven switches and two diodes, which is fewer than many existing multilevel boost inverters. This reduction in component count not only reduces cost and size but also simplifies the control circuit.
2. Proposed Topology and Derivation
The circuit configuration of the proposed single-stage non-isolated five-level step-up photovoltaic inverter is shown below. The inverter consists of a PV source \(U_{in}\), an input inductor \(L_{in}\), two diodes \(D_1, D_2\), seven power switches \(S_1\) through \(S_7\), two storage capacitors \(C_1\) and \(C_2\), a filter network (\(L_{f1}, C_f, L_{f2}\)), and the grid/load \(U_g\). The input inductor and switches \(S_1, S_2, S_3\) form a boost-type DC-DC stage that charges the capacitors \(C_1\) and \(C_2\). The diode-clamped five-level bridge, composed of switches \(S_2\) through \(S_7\) and diodes \(D_1, D_2\), synthesizes the five-level output voltage.
The topology can be derived by replacing the storage capacitors and the right-side bridge arm of a previously proposed common-grounded three-level boost inverter with a diode-clamped multilevel bridge. By moving the neutral point of the diode-clamped circuit to coincide with the negative rail of the boost circuit, the common-ground connection is naturally created. This structure ensures that the parasitic capacitance across the PV panel is always shorted, regardless of the switching state. Therefore, the proposed solar inverter inherently eliminates leakage current without any additional bypass circuitry.
For the theoretical analysis, I make the following assumptions: all power devices are ideal; the capacitors \(C_1\) and \(C_2\) have equal capacitances; and the capacitor voltages are equal and constant during steady-state operation, i.e., \(U_{C1}=U_{C2}=U_C\).
3. Operating Principle and Modulation Strategy
The proposed inverter was first analyzed using the conventional sinusoidal pulse-width modulation (SPWM) method. In this modulation scheme, two triangular carriers \(V_{tri1}\) and \(V_{tri2}\) are compared with a sinusoidal reference \(V_{ref}\) to generate the gating signals. The switching states for the positive and negative half cycles are summarized in Table 1. The inverter produces output voltage levels of \(+2U_C\), \(+U_C\), \(0\), \(-U_C\), and \(-2U_C\), resulting in a five-level output voltage waveform. However, under this SPWM strategy, the input inductor current operates in discontinuous conduction mode (DCM), which leads to a high peak current and increased stress on the input source. The DCM mode also creates a more complex voltage gain expression and makes the control design more challenging.
| Mode | \(U_{AB}\) | \(S_1\) | \(S_2\) | \(S_3\) | \(S_4\) | \(S_5\) | \(S_6\) | \(S_7\) |
|---|---|---|---|---|---|---|---|---|
| Positive (Mode 1) | \(+U_{C1}+U_{C2}\) | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| Positive zero | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive (Mode 5) | \(+U_{C2}\) | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Negative (Mode 7) | \(-U_{C1}-U_{C2}\) | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
| Negative zero | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative (Mode 13) | \(-U_{C1}\) | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
To overcome the DCM drawback, I adopted an improved modulation strategy called constant-duty-cycle PWM for the input inductor. In this method, the reference \(V_{dc-ref}\) is added for switch \(S_1\), so that \(S_1\) operates with a fixed duty cycle. The gating signals for the other switches are still generated by comparing the sinusoidal reference with the triangular carriers. This simple modification makes the input inductor current continuous, and the converter operates in continuous conduction mode (CCM). Table 2 shows the switch states under the improved PWM strategy. There are sixteen operating modes in total, but the additional modes only affect the inductor current path; the output voltage levels remain the same.
| Mode | \(U_{AB}\) | \(S_1\) | \(S_2\) | \(S_3\) | \(S_4\) | \(S_5\) | \(S_6\) | \(S_7\) |
|---|---|---|---|---|---|---|---|---|
| Positive (Mode 1) | \(+U_{C1}+U_{C2}\) | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| Positive (Mode 2,4,6,8) | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive (Mode 3,7) | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive (Mode 5) | \(+U_{C2}\) | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Negative (Mode 9) | \(-U_{C1}-U_{C2}\) | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
| Negative (Mode 10,12,14,16) | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative (Mode 11,15) | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative (Mode 13) | \(-U_{C1}\) | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
During the positive half-cycle, mode 1 charges the input inductor through \(S_1\) while capacitors \(C_1\) and \(C_2\) supply the load. In mode 2, the inductor is still charged by \(S_1\) but the load is freewheeling through \(S_3, S_5, S_7\). In mode 3, \(S_1\) is turned off, and the input source and inductor together transfer energy to \(C_1\) and \(C_2\). In mode 5, the output voltage is \(+U_{C2}\) because capacitor \(C_2\) is connected to the load through \(S_3, S_4\) and \(D_1\). The negative half-cycle operates similarly with the opposite polarity. Because the inductor current never drops to zero, the converter maintains continuous conduction.
4. Steady-State Analysis
4.1 Voltage Gain
In CCM operation, the front-end boost converter formed by \(L_{in}\), \(S_1, S_2, S_3\) and \(C_1, C_2\) provides a steady capacitor voltage given by
$$U_{C1}=U_{C2}=U_C=\frac{U_{in}}{1-D}$$
where \(D\) is the duty cycle of switch \(S_1\). The output voltage of the five-level bridge can be expressed as
$$U_o = m (U_{C1}+U_{C2}) = \frac{2m U_C}{1-D}$$
where \(m\) is the modulation index of the PWM bridge. Therefore, the voltage gain of the proposed solar inverter in CCM mode is
$$G = \frac{U_o}{U_{in}} = \frac{m}{1-D}$$
This gain equation is much simpler than the gain expression in DCM mode, which depends on the output power, switching frequency, and inductance value. In DCM mode, the gain is given by
$$G_{DCM}=\frac{m^2}{4} + \frac{m U_{in}}{U_o} + \frac{m^2 U_{in}^2}{4 P_o L_{in} f_s}$$
which clearly shows the additional dependency on power \(P_o\), inductance \(L_{in}\), and switching frequency \(f_s\). The CCM mode is therefore preferred for practical PV applications because it simplifies the design of the controller and provides a more stable input current.
4.2 Voltage and Current Stress
The voltage stresses of the power devices are important for component selection. From the switching states, the maximum voltages across the switches and diodes are:
$$U_{S1,max}=U_{S2,max}=U_{S3,max}=U_{S5,max}=U_{S7,max}=U_{C1}+U_{C2}=2U_C$$
$$U_{S4,max}=U_{S6,max}=U_{C1}=U_C$$
$$U_{D1,max}=U_{D2,max}=U_C$$
The current stresses are determined from the worst-case inductor current and output current. Let \(I_{Lin,max}\) be the maximum inductor current and \(I_{om}\) be the maximum output current amplitude. Then
$$i_{S1,max}=i_{Lin,max}+I_{om}, \quad i_{S4,max}=i_{S5,max}=i_{S6,max}=i_{S7,max}=I_{om}$$
$$i_{S2,max}=i_{S3,max}=I_{Lin,max}, \quad i_{D1,max}=i_{D2,max}=I_{om}$$
These stress values are relatively low compared with two-level boost inverters, which helps to improve the overall efficiency.
4.3 Loss Analysis
I also carried out a detailed loss analysis for the proposed inverter. The total losses are divided into switching losses, conduction losses, and magnetic losses. The switching loss of a MOSFET during the \(N\)-th switching cycle can be expressed as
$$P_{sw}(N)=\frac{1}{2} f_s U_{ds}(N) I_{ds}(N) (t_{cr}+t_{vf}+t_{cf}+t_{vr})$$
where \(U_{ds}\) and \(I_{ds}\) are the drain-source voltage and current at the switching instant, and \(t_{cr}, t_{vf}, t_{cf}, t_{vr}\) are the current rise time, voltage fall time, current fall time, and voltage rise time, respectively.
Conduction losses are caused by the on-state resistance \(R_{DS}\) of the switches and the forward voltage of the diodes. For a switch \(S_x\), the conduction loss over one fundamental period is
$$P_{cond,S_x} = \frac{1}{T_o} \int_{0}^{T_o} i_{S_x}(t) u_{DS,S_x}(t) D_{S_x}(t) dt$$
where \(D_{S_x}(t)\) is the duty cycle of that switch at time \(t\). The diode conduction loss is similarly calculated using its forward resistance and forward voltage drop.
Magnetic losses in the input inductor and filter inductor consist of core loss and copper loss. The core loss is estimated using the Steinmetz equation:
$$P_{core} = k f_s^{\eta} B^{\lambda}$$
where \(k, \eta, \lambda\) are material-dependent coefficients and \(B\) is the peak flux density. The copper loss is
$$P_{cu} = I_{rms}^2 R_{cu}$$
where \(I_{rms}\) is the RMS current through the inductor and \(R_{cu}\) is the equivalent series resistance of its winding. At an output power of 500 W, the calculated efficiency is approximately 95.5%, with the majority of losses distributed among the switching losses, conduction losses, and inductor losses.
5. Common-Mode Leakage Current Analysis
For a transformerless solar inverter, the common-mode leakage current path is formed by the parasitic capacitance \(C_{pvg}\) between the PV panel and ground. In a conventional full-bridge inverter, the common-mode voltage can be expressed as
$$V_{cm} = 0.5 (V_{AN}+V_{BN}) + 0.5 V_g$$
where \(V_{AN}\) and \(V_{BN}\) are the output voltages of the two bridge legs with respect to the negative DC bus, and \(V_g\) is the grid voltage. Due to the high-frequency switching, \(V_{cm}\) varies at the switching frequency, causing a current
$$i_{cm} = C_{pvg} \frac{dV_{cm}}{dt}$$
This leakage current is undesirable and must be suppressed. In the proposed inverter, the negative terminal of the PV source is directly connected to the neutral point of the AC output. As a result, the parasitic capacitance \(C_{pvg}\) is short-circuited, and the common-mode voltage becomes constant. Therefore, the proposed solar inverter theoretically produces zero leakage current. This is a major advantage because it eliminates the need for additional CM filters or complex modulation schemes.
6. Simulation and Comparison
To verify the theoretical analysis, I built simulation models in MATLAB/Simulink for both DCM and CCM modes. The simulation parameters are listed in Table 3.
| Parameter | Symbol | DCM | CCM |
|---|---|---|---|
| Input voltage | \(U_{in}\) | 40–60 V | 40–60 V |
| Output voltage (RMS) | \(U_o\) | 110 V | 110 V |
| Output power | \(P_o\) | 600 W | 600 W |
| Switching frequency | \(f_s\) | 20 kHz | 20 kHz |
| Input inductor | \(L_{in}\) | 0.2 mH | 4 mH |
| Storage capacitors | \(C_1, C_2\) | 220 μF | 220 μF |
| Filter inductor | \(L_o\) | 4 mH | 4 mH |
| Filter capacitor | \(C_f\) | 5 μF | 5 μF |
The simulation results show that in DCM mode the input inductor current exhibits a pulsed waveform with high peaks, whereas in CCM mode the input current is continuous and smooth. The capacitor voltages and switch voltages in CCM mode have much lower ripple. Both modes can output 110 V AC, confirming that the proposed solar inverter achieves boost inversion. The total harmonic distortion (THD) of the output voltage was 0.68% in DCM mode and 0.51% in CCM mode, both satisfying the grid-connection requirement.
I also compared the proposed solar inverter with several other recently published inverters. Table 4 summarizes the key parameters and performance metrics. The proposed inverter uses only 7 switches and 2 diodes, which is the fewest among the compared topologies with step-up capability. It also provides continuous input current, high voltage gain, and low leakage current. This combination makes it particularly suitable for single-phase transformerless PV systems.
| Converter | Switches | Diodes | Inductors | Capacitors | Gain | Input current | Leakage current |
|---|---|---|---|---|---|---|---|
| Ref. [15] | 8 | 1 | 0 | 2 | >1 | Discontinuous | High |
| Ref. [49] | 7 | 2 | 0 | 0 | <1 | Discontinuous | High |
| Ref. [50] | 9 | 1 | 0 | 2 | >1 | Discontinuous | Low |
| Ref. [51] | 10 | 0 | 1 | 1 | >1 | Continuous | High |
| Ref. [52] | 9 | 2 | 1 | 3 | <1 | Continuous | High |
| Ref. [53] | 8 | 8 | 1 | 0 | >1 | Continuous | High |
| Ref. [54] | 9 | 1 | 1 | 2 | >1 | Discontinuous | High |
| Ref. [55] | 12 | 0 | 0 | 4 | <1 | Continuous | High |
| Ref. [56] | 12 | 0 | 0 | 3 | <1 | Continuous | High |
| Proposed | 7 | 2 | 1 | 2 | >1 | Continuous | Very low |
7. Grid-Connected Control with MPPT
For the practical application of the proposed solar inverter in a PV grid-connected system, I studied several control strategies. The single-current closed-loop control is simple but has poor phase alignment with the grid voltage. The voltage-current double closed-loop control can improve phase tracking by using a PLL, but it only operates at unity power factor. To achieve flexible reactive power control, I adopted the direct power control (DPC) strategy, which is shown in the block diagram concept. In DPC, the instantaneous active power \(P\) and reactive power \(Q\) are calculated from the grid voltage and current. For a single-phase system, a virtual orthogonal voltage \(u_{\beta}\) and current \(i_{\beta}\) are created by delaying the measured signals by one quarter of the grid period. The power equations are
$$\begin{bmatrix} P \\ Q \end{bmatrix} = \frac{1}{2} \begin{bmatrix} u_g & u_{\beta} \\ u_{\beta} & -u_g \end{bmatrix} \begin{bmatrix} i_g \\ i_{\beta} \end{bmatrix}$$
The reference active power \(P^*\) is obtained from a maximum power point tracking (MPPT) controller, while the reference reactive power \(Q^*\) can be set independently. The errors \(\Delta P = P^* – P\) and \(\Delta Q = Q^* – Q\) are fed into two PI controllers to generate the active current component \(I_{pm}\) and reactive current component \(I_{qm}\). The reference grid current amplitude is then computed as
$$I_{gm} = \sqrt{I_{pm}^2 + I_{qm}^2}, \quad \theta = \tan^{-1}(I_{qm}/I_{pm})$$
$$i_g^* = I_{gm} \sin(\omega t – \theta)$$
The actual grid current is regulated by another PI controller to track \(i_g^*\), and the output of this controller generates the PWM signals for the inverter switches.
Among the MPPT methods, I compared constant voltage tracking, perturb and observe (P&O), and incremental conductance (INC). The constant voltage method is simple but fails when the temperature changes. P&O is widely used but produces oscillations around the maximum power point. The incremental conductance method offers better accuracy and dynamic response by comparing the instantaneous conductance with the incremental conductance. The condition for reaching the maximum power point is
$$\frac{dP_{pv}}{dV_{pv}} = 0 \quad \Rightarrow \quad \frac{dI_{pv}}{dV_{pv}} = -\frac{I_{pv}}{V_{pv}}$$
Therefore, I chose the incremental conductance method for the proposed solar inverter.
The combined control strategy is a maximum-power-point-tracking direct power control (MPPT-DPC). I built the complete simulation model in MATLAB/Simulink, including a PV panel model, the proposed five-level inverter, the DPC controller, and the INC-MPPT algorithm. The PV panel parameters were set to give a maximum power of 500 W at \(V_{mpp}=100\) V and \(I_{mpp}=5\) A under standard test conditions of 1000 W/m² and 25 °C. The simulation results show that after a short transient, the PV voltage, current, and power settle at 100 V, 5 A, and 500 W, respectively, which confirms that the MPPT works correctly.
I also tested the dynamic response under changing conditions. When the irradiance was stepped from 1000 W/m² to 600 W/m² at 0.5 s while the temperature remained at 25 °C, the MPPT controller successfully tracked the new maximum power point. In the same simulation, the reactive power reference was changed from 0 Var to 200 Var, and the grid current phase shifted accordingly, demonstrating the reactive power control capability of the proposed solar inverter. Similar tests with a temperature step from 25 °C to 100 °C showed that the system still maintains stable operation and good dynamic performance.
In all simulation cases, the grid voltage and current remained in phase when the reactive power reference was zero, and the THD of the grid current was 3.62%, which satisfies the standard for grid-connected solar inverters.
8. Hardware Design and Experimental Validation
To experimentally verify the theoretical analysis and simulation results, I designed and built a prototype of the proposed solar inverter. The main circuit parameters are listed in Table 5.
| Parameter | Value |
|---|---|
| Input voltage \(U_{in}\) | 80–120 V |
| Output voltage \(U_g\) | 110 V / 50 Hz |
| Output power \(P_o\) | 450 W |
| Switching frequency \(f_s\) | 20 kHz |
| Input inductor \(L_{in}\) | 4 mH |
| Storage capacitors \(C_1, C_2\) | 220 μF / 450 V |
| Filter inductors \(L_{f1}, L_{f2}\) | 4 mH, 5 mH |
| Filter capacitor \(C_f\) | 5 μF |
8.1 Power Circuit Design
The input inductor was designed based on the allowable current ripple. In CCM mode, the inductor current ripple \(\Delta i_{Lin}\) is related to the duty cycle \(D\), switching period \(T_s\), and input voltage by
$$L_{in} = \frac{U_{in} D T_s}{\gamma I_{Lin}}$$
where \(\gamma\) is the current ripple ratio. With \(U_{in}=80\) V, \(D=0.55\), \(T_s=50\,\mu s\), \(I_{Lin}\approx 5.6\) A, and \(\gamma=0.2\), the calculated inductance is about 4 mH.
The storage capacitors were selected to maintain a small voltage ripple. Using the charge-balance equation, the minimum capacitance is
$$C \ge \frac{U_C}{R_C U_C f_s \cdot \Delta U_C / U_C}$$
where \(\Delta U_C\) is the allowed voltage ripple. I chose 220 μF capacitors with a rated voltage of 450 V to provide a sufficient safety margin.
The power switches are selected based on their voltage and current stresses. From the earlier analysis, switches \(S_1, S_2, S_3, S_5, S_7\) see a maximum voltage of about \(2U_C=250\) V, while \(S_4\) and \(S_6\) see about 125 V. The maximum switch current is around 10.3 A. Considering a safety margin, I selected the IRFP460PBF MOSFET, which has a 500 V drain-source breakdown voltage and a 20 A continuous current rating. The diodes \(D_1\) and \(D_2\) were chosen as QRT3006P, rated at 600 V and 30 A.
The LCL filter was designed to attenuate the high-frequency switching harmonics. The inverter-side inductor \(L_{f1}\) was chosen as 4 mH, the filter capacitor \(C_f\) as 5 μF, and the grid-side inductor \(L_{f2}\) as 5 mH. The resonance frequency of the LCL filter is
$$\omega_r = \sqrt{\frac{L_{f1}+L_{f2}}{L_{f1} L_{f2} C_f}}$$
which was set to about 5 kHz, well below the 20 kHz switching frequency.
8.2 Control Board Design
The control board is centered around the digital signal processor TMS320F28335. This DSP provides high-speed floating-point computation, six enhanced PWM modules (12 outputs), and eight 12-bit ADCs. Since the DSP outputs 3.3 V PWM signals, which cannot directly drive the MOSFETs, I designed a gate-drive circuit using the isolated gate driver chip NSI6602A. Each NSI6602A provides two isolated outputs with a maximum isolation voltage of 5700 Vrms. The dead-time between the two outputs can be adjusted using an external resistor. I also used small DC-DC isolated modules (B1515S-1W) to provide isolated 15 V supplies for each output channel. This arrangement ensures reliable and safe driving of all switches.
For voltage sensing, I designed a resistive divider followed by an op-amp level shifter. The amplifier DIO2362LSO8 operates from a 3.3 V supply, which matches the DSP reference. The sensing circuit maps a ±400 V AC voltage into 0–3 V DC, with the transfer function
$$V_{ADC} = 1.65 + \frac{V_{in}}{300}$$
For current sensing, I used the hall-effect current sensor CC6903SO, which provides an analog output voltage proportional to the measured current. Its output is centered at 1.65 V and has a sensitivity of about 132 mV/A. The transfer function is
$$V_{ADC} = 1.65 + \frac{I_{AC}}{7.58}$$
Both voltage and current sensing circuits were calibrated and tested. The measured waveforms show good linearity and negligible phase shift, making them suitable for the grid-connected control loop.
8.3 Experimental Results
The complete experimental platform consists of the power board, the control board, a DC voltage source, an oscilloscope, and a resistor load. I first tested the inverter in steady-state operation with an input voltage of 90 V and an output target of 110 V RMS. The obtained waveforms show a stable output voltage and a low-distortion output current of about 4 A. The output power was approximately 440 W.
The bridge-arm voltage \(U_{AB}\) was measured and found to have five levels with a peak value of about 240 V. The zero-voltage intervals are present in the expected positions, confirming the correct multilevel modulation. The gate-source voltage of switch \(S_1\) shows a constant duty cycle, and the input inductor current is continuous with a small ripple. This verifies that the improved constant-duty-cycle PWM successfully makes the solar inverter operate in CCM mode.
I also measured the common-mode voltage \(U_{cm}\) and the leakage current \(i_{cm}\). As expected, both waveforms are nearly zero, confirming that the common-ground structure completely eliminates the leakage current. This is a major advantage of the proposed solar inverter.
The voltage stresses across the switches were recorded. Switches \(S_1, S_2, S_3, S_5, S_7\) block approximately 240 V, while \(S_4\) and \(S_6\) block approximately 120 V. These values agree with the theoretical calculation.
To test the dynamic response of the grid-connected control, I applied a step change in the reference current from 2.9 A to 4.09 A and then back to 2.9 A. The grid current responded quickly without significant overshoot or oscillation, indicating a well-designed PI regulator. In a separate test, the reactive power reference was changed to a positive value, and the grid current was observed to lead the grid voltage, confirming the ability of the proposed solar inverter to provide reactive power compensation.
Finally, I measured the efficiency of the proposed inverter at different output power levels. The results are shown in Table 6. The efficiency exceeds 90% for output powers from 100 W to 500 W, and the peak efficiency reaches 95.5% at 500 W. This demonstrates that the proposed solar inverter achieves both high performance and high efficiency.
| Output power (W) | 100 | 200 | 300 | 400 | 500 |
|---|---|---|---|---|---|
| Efficiency (%) | 91.2 | 93.5 | 94.3 | 95.0 | 95.5 |
9. Conclusion
In this thesis, I have presented a comprehensive study of a single-stage non-isolated five-level step-up photovoltaic inverter without leakage current. The proposed solar inverter combines a common-ground boost stage with a diode-clamped five-level bridge to achieve high voltage gain, continuous input current, and zero common-mode leakage current in a single power conversion stage. The topology uses only seven switches and two diodes, which is fewer than many existing multilevel inverters. I derived the operating principle under both conventional SPWM and an improved constant-duty-cycle PWM, and I showed that the improved modulation leads to CCM operation of the input inductor. The voltage gain in CCM mode is simply \(G=m/(1-D)\), which greatly simplifies the control design.
The common-ground configuration completely suppresses the leakage current because the PV parasitic capacitance is short-circuited by the input-output connection. This was confirmed by both simulation and experiment. The proposed solar inverter also exhibits low voltage stress on the switches, with the maximum switch voltage being only twice the capacitor voltage. The loss analysis and efficiency measurements show that the inverter can achieve a peak efficiency of 95.5%.
I also designed and implemented a grid-connected control strategy based on direct power control with incremental conductance MPPT. The combined MPPT-DPC method enables the inverter to track the maximum power point of the PV array while regulating the active and reactive power independently. Simulation results under varying irradiance and temperature confirm the excellent dynamic performance of the control system. The experimental prototype based on TMS320F33535 validates the feasibility and correctness of the proposed solar inverter. All experimental waveforms agree well with the theoretical analysis, demonstrating that the proposed inverter is a promising candidate for low-cost, high-efficiency, transformerless photovoltaic grid-connected systems.
Future work will focus on replacing the DC voltage source with real PV panels to test the MPPT algorithm under actual irradiance and temperature profiles. In addition, I plan to extend the proposed topology to higher level numbers and to develop a more advanced modulation scheme that further reduces the common-mode noise and improves the efficiency. The experimental comparison between the conventional SPWM and the improved constant-duty-cycle PWM will also be carried out to provide a more complete validation of the advantages of the proposed solar inverter.