Real-time simulation systems are essential tools for the analysis, design, and experimental validation of three-phase inverters and their control algorithms. Existing commercial real-time simulation platforms are often expensive and struggle to meet the requirements for multi-time-scale simulations that encompass both component-level and system-level dynamics. To address these limitations, we have developed a real-time simulation system for a three-phase inverter based on a multi-FPGA architecture. This system employs a segmented fitting strategy to model the dynamic switching processes of IGBTs, constructs models for the three-phase IGBT bridge arms, LC filters, and loads based on the IGBT models and system state equations, and implements multi-time-scale real-time computation using multiple FPGAs. Additionally, we designed upper-computer software for parameter configuration and waveform visualization. Simulation results demonstrate that the proposed system achieves simulation step sizes of 20 ns for the IGBT model and 10 μs for the system, enabling real-time simulation of the three-phase inverter across multiple time scales.
The three-phase inverter plays a critical role in applications such as smart grids, renewable energy, and rail transportation. Real-time simulation systems can significantly reduce the development cycle and costs associated with three-phase inverter modules and control algorithms. However, current commercial systems are costly and often idealize IGBT models due to difficulties in simulating nanosecond-scale dynamic processes. Our work focuses on improving the modeling accuracy and simulation step size of IGBT switches, which are key factors in real-time simulation. By leveraging a multi-FPGA architecture, we achieve high-fidelity simulation of both IGBT components and the overall three-phase inverter system.
IGBT Switching Modeling
The IGBT equivalent circuit model includes a controlled current source \(i_{mos}\), parasitic capacitances \(C_{ge}\), \(C_{gc}\), and \(C_{ce}\), a gate equivalent resistance \(R_g\), and stray inductance \(l_p\). We model the dynamic characteristics of the IGBT by dividing the turn-on and turn-off processes into multiple stages and using quadratic functions to fit the collector-emitter voltage \(v_{ce}(t)\) and collector current \(i_{ce}(t)\) based on the process time \(t\).
The turn-on process is divided into six stages. In stage 1, from \(t_{0(on)}\) to \(t_{1(on)}\), the gate voltage \(v_{ge}(t)\) charges the input capacitance \(C_{ies} = C_{ge} + C_{gc}\) until it reaches the threshold voltage \(v_{ge(th)}\). During this stage, \(v_{ce}(t) = v_{ce0}\) and \(i_{ce}(t) = 0\). In stage 2, \(i_{ce}(t)\) increases linearly to the load current \(I_{c0}\) at \(t_{2(on)}\), while \(v_{ce}(t)\) decreases to \(v_{cep}\) due to the influence of \(l_p\). Stage 3 involves the freewheeling diode commutation, where \(i_{ce}(t)\) overshoots by the reverse recovery current \(I_{rr}\). In stage 4, the diode current drops to zero, and \(i_{ce}(t)\) returns to the load current. Stage 5 sees \(v_{ce}(t)\) decreasing while \(v_{ge}(t)\) remains at the Miller plateau voltage \(v_{gel}\). Finally, in stage 6, \(v_{ge}(t)\) rises to the applied gate voltage \(v_+\), and \(v_{ce}(t)\) drops to the on-state voltage \(v_{ces}\).
The turn-off process consists of five stages. In stage 1, from \(t_{0(off)}\) to \(t_{1(off)}\), \(v_{ce}(t)\) rises from \(v_{ces}\) to 10% of \(v_{ce0}\) while \(i_{ce}(t)\) remains constant. In stage 2, \(v_{ce}(t)\) increases to the DC bus voltage \(v_{ce0}\), with \(v_{ge}(t)\) at \(v_{gel}\). Stage 3 involves \(i_{ce}(t)\) decreasing and \(v_{ce}(t)\) peaking due to \(l_p\). In stage 4, \(v_{ce}(t)\) falls back to \(v_{ce0}\), and \(i_{ce}(t)\) decreases to 0.1\(I_{c0}\) with current tailing. Stage 5 completes the turn-off with \(v_{ge}(t)\) dropping to \(v_-\) and \(i_{ce}(t)\) reaching zero.
To standardize the computation, we express the voltage and current in each stage using unified quadratic functions:
$$v_{ce}(t) = K_V \begin{bmatrix} t^2 & t & 1 \end{bmatrix}^T$$
$$i_{ce}(t) = K_C \begin{bmatrix} t^2 & t & 1 \end{bmatrix}^T$$
where \(K_V\) and \(K_C\) are coefficients derived from offline calculations based on the IGBT specifications and circuit parameters. The IGBT model is implemented in VHDL with two main modules: a parameter calculation module and a model computation module. The model computation module uses a finite state machine triggered by PWM signal edges to switch between turn-on and turn-off calculations, with a multiplexer outputting the final voltage and current values.
| Stage | Description | Voltage \(v_{ce}(t)\) | Current \(i_{ce}(t)\) |
|---|---|---|---|
| 1 | Gate charging | Constant \(v_{ce0}\) | Zero |
| 2 | Current rise | Quadratic fit | Linear increase |
| 3 | Diode commutation | Quadratic fit | Overshoot due to \(I_{rr}\) |
| 4 | Diode turn-off | Quadratic fit | Quadratic decrease |
| 5 | Miller plateau | Quadratic decrease | Constant \(I_{c0}\) |
| 6 | Saturation entry | Decrease to \(v_{ces}\) | Constant \(I_{c0}\) |
Real-Time Simulation System Design
The real-time simulation system for the three-phase inverter comprises the simulation models, multi-FPGA hardware, and upper-computer software. The models are deployed on FPGAs, while the software handles parameter configuration and result display.
Three-Phase Inverter Real-Time Simulation Modeling
Based on the three-phase inverter topology, we construct the IGBT bridge arm model using the aforementioned IGBT model, and derive the LC filter and load models from system state equations.
For the IGBT bridge arm, considering the DC-link capacitor midpoint \(n’\), the phase voltage \(u_{an’}\) is \( \frac{u_d}{2} – v_{ce}(t) \) when the upper switch \(V_1\) is on, and \( -\frac{u_d}{2} – v_{ce}(t) \) when the lower switch \(V_4\) is on. The output phase voltages are calculated as:
$$v_a = u_{an’} – u_{nn’}$$
$$v_b = u_{bn’} – u_{nn’}$$
$$v_c = u_{cn’} – u_{nn’}$$
Assuming a symmetric three-phase load, \(v_a + v_b + v_c = 0\), leading to \(u_{nn’} = \frac{1}{3}(u_{an’} + u_{bn’} + u_{cn’})\).
For the three-phase LC filter with star-connected capacitors, Kirchhoff’s laws yield the discrete state equation:
$$x_s(k+1) = A_{sd} x_s(k) + B_{sd} u_s(k) + B_{isd} u_{is}(k)$$
where \(x_s(k) = \begin{bmatrix} v_{oA} & v_{oB} & v_{oC} & i_a & i_b & i_c \end{bmatrix}^T\), \(u_s(k) = \begin{bmatrix} v_a & v_b & v_c \end{bmatrix}^T\), and \(u_{is}(k) = \begin{bmatrix} i_{oa} & i_{ob} & i_{oc} \end{bmatrix}^T\). The matrices \(A_{sd}\), \(B_{sd}\), and \(B_{isd}\) are derived from system parameters and the simulation step size.
For the three-phase RL load, the discrete state equation is:
$$x_{is}(k+1) = A_{sid} x_{is}(k) + B_{sud} u_{vs}(k)$$
where \(x_{is}(k) = \begin{bmatrix} i_{oa} & i_{ob} & i_{oc} \end{bmatrix}^T\), \(u_{vs}(k) = \begin{bmatrix} v_{oA} & v_{oB} & v_{oC} \end{bmatrix}^T\), and \(A_{sid}\), \(B_{sud}\) are parameter matrices.
Multi-FPGA Hardware Design
The multi-FPGA hardware architecture distributes the simulation models across four FPGA boards. FPGA1, FPGA2, and FPGA3 handle the real-time computation of the three-phase bridge arm models with a simulation step size of 20 ns, while FPGA4 computes the LC filter and load models with a step size of 10 μs. The FPGAs communicate via LVDS, and the system interfaces with an external controller through optocouplers for PWM signals. We selected Altera/Cyclone IV series EP4CE75F23C8 FPGAs, which provide sufficient logic elements for the models and allow for future expansions.
To handle the multi-rate simulation, we average the outputs from FPGA1-3 over each period of FPGA4. Specifically, if FPGA4’s step size is \(\Delta T = k \cdot \Delta t\), where \(\Delta t\) is the step size of FPGA1-3, then FPGA4 averages the \(k\) input values from FPGA1-3 over each \(\Delta T\) to compute the inputs for the LC filter and load models.
Upper-Computer Software Design
The upper-computer software, developed in C#, facilitates parameter input and result display. The parameter input interface allows users to set IGBT device parameters, filter parameters, and load parameters. These parameters are stored in a local database and transmitted to the hardware via serial communication. The simulation result display interface shows waveforms of inductor currents, capacitor voltages, and load currents, with options to select phases and display durations (e.g., 0.1 s, 0.5 s, or 1 s). Data from the hardware is stored in the database and dynamically retrieved for plotting.
| Parameter Category | Symbol | Description |
|---|---|---|
| IGBT Parameters | \(C_{ge}\), \(C_{gc}\), \(C_{ce}\) | Parasitic capacitances |
| \(R_g\) | Gate resistance | |
| \(l_p\) | Stray inductance | |
| Filter Parameters | \(L\), \(C\) | Inductance and capacitance |
| \(r_l\) | Series resistance | |
| Load Parameters | \(R\), \(L\) | Resistance and inductance |
Simulation Studies
We validated the IGBT model using Modelsim with a simulation step size of 20 ns. The results show that the dynamic switching processes align with theoretical analysis, confirming the model’s accuracy. Real-time execution on the FPGA at 50 MHz produced consistent results, demonstrating the feasibility of the modeling approach.
For the three-phase inverter system, we configured parameters via the upper-computer software and implemented a control strategy from literature. The real-time simulation results match physical experiments, verifying the system’s effectiveness. The three-phase inverter outputs exhibit stable voltage and current waveforms under various load conditions, with the multi-FPGA architecture ensuring real-time performance across time scales.
The simulation step sizes of 20 ns for the IGBT model and 10 μs for the system enable detailed analysis of switching dynamics and system-level behavior. This multi-time-scale capability is crucial for optimizing the design and control of three-phase inverters in applications such as renewable energy integration and motor drives.
Conclusion
We have designed and implemented a real-time simulation system for three-phase inverters using a multi-FPGA architecture. The system employs segmented quadratic fitting for IGBT switching modeling and state-equation-based models for filters and loads. The multi-FPGA hardware handles multi-time-scale computations, and the upper-computer software provides a user-friendly interface for parameter management and visualization. Simulation results confirm the system’s ability to achieve real-time simulation with high accuracy at both component and system levels. Future work will focus on enhancing the system with additional modules, such as DA conversion and harmonic analysis, to improve its practicality for industrial applications. The three-phase inverter real-time simulation system offers a cost-effective and scalable solution for research and development in power electronics.