As a member of the research team focused on advanced power electronics and energy storage, I have been deeply involved in the development and validation of a real-time simulation model for a high-voltage direct-connected large-capacity battery energy storage system (BESS). This system, based on cascaded H-bridge (CHB) converters, eliminates the need for bulky line-frequency transformers, offering significant advantages in modularity, efficiency, and scalability. In this article, I will present our work on constructing the first CPU-FPGA co-simulation model for such a system, along with the associated control strategies and hardware-in-the-loop (HIL) test results. Our aim is to provide a comprehensive technical reference for the design and optimization of high-voltage BESS.
The rapid development of modern power systems has placed increasing demands on energy storage technologies. Among various options, the battery energy storage system stands out due to its fast response, high power density, and flexible siting. When a cascaded converter is used as the power conversion system for large-capacity BESS, it can be directly connected to medium/high voltage grids without a transformer, forming a “high-voltage direct-connected” or “transformerless” BESS. This configuration offers benefits such as modularity, high voltage direct connection, single-machine large capacity, and multi-level output. However, prior to our work, there was a lack of real-time simulation models that accurately account for the external characteristics of the battery, especially for systems with a large number of submodules. Our research addressed this gap by developing a CPU-FPGA based real-time simulation platform and validating it with a typical 35 kV / 10 MW system.
1. System Topology and Mathematical Model
The topology of the high-voltage direct-connected BESS is illustrated in the figure below (the image link is inserted here).
The three phases are connected in a Y-configuration and directly connected to the high-voltage grid. Each phase consists of a cascade of N submodules. The submodule topology includes a battery pack, a filtering inductor and capacitor, a pre-charge circuit (with resistors and switches), and an H-bridge converter. The H-bridge enables four-quadrant operation, allowing both charging and discharging. The bypass switch K3 provides fault isolation capability.
The electrical model of the system can be simplified by considering each phase as a controlled voltage source. The voltage balance equation in the three-phase stationary coordinate system is:
$$
L \frac{d}{dt} \begin{bmatrix} i_a \\ i_b \\ i_c \end{bmatrix} + R \begin{bmatrix} i_a \\ i_b \\ i_c \end{bmatrix} = \begin{bmatrix} e_a \\ e_b \\ e_c \end{bmatrix} – \begin{bmatrix} v_a \\ v_b \\ v_c \end{bmatrix} + v_{NO} \begin{bmatrix} 1 \\ 1 \\ 1 \end{bmatrix}
$$
where \(e_a, e_b, e_c\) are the grid phase voltages, \(i_a, i_b, i_c\) are the line currents, \(v_a, v_b, v_c\) are the converter output voltages, and \(v_{NO}\) is the voltage between the neutral point of the converter and the grid neutral. Considering that the sum of three-phase grid voltages is zero and the sum of three-phase currents is zero, we can derive the equivalent dq-model after applying the Park transformation:
$$
\begin{aligned}
L \frac{di_d}{dt} &= -R i_d + \omega L i_q + e_d – V_{dc} S_d \\
L \frac{di_q}{dt} &= -R i_q – \omega L i_d + e_q – V_{dc} S_q
\end{aligned}
$$
Here, \(V_{dc}\) is the DC bus voltage of each submodule, and \(S_d, S_q\) are the equivalent switching functions in the dq-frame. The active and reactive powers transmitted between the grid and the BESS are:
$$
P = \frac{3}{2} e_d i_d, \quad Q = -\frac{3}{2} e_d i_q
$$
Since the grid voltage d-component is constant (with q-component zero under proper PLL synchronization), the control of active and reactive powers reduces to the control of \(i_d\) and \(i_q\).
2. Control Strategy Design
Our control system consists of three main layers: power control, modulation, and state-of-charge (SOC) balancing. The power control employs a decoupled dq-current controller with PI regulators. The control laws are:
$$
\begin{aligned}
V_{dc} S_d^* &= \left(K_p + \frac{K_i}{s}\right) (i_d^* – i_d) – \omega L i_q + e_d \\
V_{dc} S_q^* &= \left(K_p + \frac{K_i}{s}\right) (i_q^* – i_q) + \omega L i_d + e_q
\end{aligned}
$$
where \(i_d^*\) and \(i_q^*\) are the current references derived from the desired active and reactive power setpoints.
For the multilevel modulation, we adopted the Nearest Level Modulation (NLM) scheme, which is well-suited for systems with a large number of submodules. The NLM algorithm determines the number of submodules to insert in each phase based on the instantaneous voltage reference. The inserted submodules are selected according to a sorting algorithm that considers both the capacitor voltages and the SOC of the batteries. To achieve intra-phase SOC balancing, we modify the sorting criterion with a correction factor:
$$
M_{ki} = u_{ki} (1 + \varepsilon \cdot \Delta S_{OC,ki})
$$
where \(u_{ki}\) is the capacitor voltage of the i-th submodule in phase k, \(\varepsilon\) is the balancing coefficient, and \(\Delta S_{OC,ki}\) is the deviation of the battery SOC from the phase average SOC. This approach ensures that submodules with higher SOC (or higher capacitor voltage) are preferentially discharged, while those with lower SOC are preferentially charged.
The modulation flow is summarized in the table below:
| Step | Action |
|---|---|
| 1 | Measure all submodule capacitor voltages and battery SOCs. |
| 2 | Compute the phase reference voltage from the controller. |
| 3 | Determine the number of submodules to insert (N_ins) by rounding the ratio of reference voltage to average submodule voltage. |
| 4 | Calculate the correction parameter M for each submodule using the formula above. |
| 5 | Sort submodules based on M values: in discharging mode, insert those with largest M; in charging mode, insert those with smallest M. |
| 6 | Generate switching signals for the selected submodules. |
3. Real-Time Simulation Platform
The real-time simulation model was developed on the OPAL-RT RT-LAB platform using an OP5707XG simulator. This simulator features a powerful Xilinx FPGA that can handle the computational demands of a 56-submodule-per-phase cascade with a simulation time-step as low as 1 μs. The model architecture is CPU-FPGA co-simulation:
- CPU (Simulink): Models the high-voltage grid (using SimPowerSystems), the analog controller (including dq-current control, SOC balancing algorithm, and NLM logic), and the communication interfaces.
- FPGA: Implements the detailed submodule models (including the H-bridge switches, filter components, pre-charge circuit, and the battery model). The FPGA receives PWM signals from the controller and sends back the phase voltages and submodule states.
The battery model is built using a second-order RC equivalent circuit, which accurately captures both static and dynamic behaviors. The circuit parameters (open-circuit voltage \(V_{oc}\), internal resistance \(R_0\), polarization resistances \(R_1, R_2\) and capacitances \(C_1, C_2\)) are dependent on SOC. We identified these parameters offline by conducting charge/discharge experiments at 5% SOC intervals. The state-space representation of the second-order RC model is:
$$
\frac{d}{dt} \begin{bmatrix} V_1 \\ V_2 \end{bmatrix} = \begin{bmatrix} -\frac{1}{R_1 C_1} & 0 \\ 0 & -\frac{1}{R_2 C_2} \end{bmatrix} \begin{bmatrix} V_1 \\ V_2 \end{bmatrix} + \begin{bmatrix} \frac{1}{C_1} \\ \frac{1}{C_2} \end{bmatrix} I_{bat}
$$
$$
V_{bat} = V_{oc} – V_1 – V_2 – I_{bat} R_0
$$
The SOC is updated using the Coulomb counting method. This model runs on the FPGA, updating the parameters in real-time as SOC changes. A lookup table stores the pre-identified parameters for 21 SOC points (0% to 100% in 5% steps).
The key specifications of the test system are summarized in the table below:
| Parameter | Value |
|---|---|
| Grid voltage (line-to-line) | 35 kV |
| Grid frequency | 50 Hz |
| Grid-side filter inductance | 20 mH |
| Grid-side filter resistance | 0.001 Ω |
| Battery type | Lithium-ion |
| Battery rated voltage | 846 V |
| Battery rated capacity | 85 Ah |
| Pre-charge resistor (submodule) | 10 Ω |
| Filter inductor (submodule) | 2.2 mH |
| Filter capacitor (submodule) | 8.9 mF |
| Number of submodules per phase | 46 |
| Rated system power | 10 MW |
The real-time simulation runs with a CPU step of 35 μs and an FPGA step of 1 μs. The control period is also 35 μs. The PI controller gains are Kp = 0.4 p.u. and Ki = 6.2 p.u., and the intra-phase balancing coefficient ε is set to 100.
4. Hardware-in-the-Loop Test Results
We conducted a series of HIL tests to validate the model and the control strategies under various operating conditions. The tests included pre-charge, standalone (passive) inverter operation, closed-loop power control, and intra-phase SOC balancing.
4.1 Pre-Charge Test
The pre-charge procedure ensures that the capacitor voltages are gradually built up to the battery voltage without excessive inrush current. We closed the pre-charge switch K1 at t=1 s, and then closed K2 at t=2 s to bypass the charging resistor. The results show that the capacitor voltage of module A1 rises from 0 to about 930 V (matching the battery voltage at 50% SOC, which is 930.62 V from the parameter table). The peak battery current was about 93 A, as expected. This confirms that the real-time model correctly simulates the pre-charge dynamics.
4.2 Standalone Inverter Test
In this test, the BESS was operated without grid connection (switches Sw1 and Sw2 open), but the controller was synchronized to the grid voltage (simulated by the CPU). The modulation index was set to 1, so the phase voltage peak should be approximately N times the submodule capacitor voltage: 46 × 930.5 V ≈ 42.8 kV. The measured output voltage waveform from the real-time simulation showed the correct amplitude and 46-level staircase shape, confirming the proper implementation of NLM.
4.3 Closed-Loop Power Control
We connected the BESS to the grid by closing Sw1 and Sw2, and then switched the controller from open-loop to closed-loop mode. First, we set the active power reference to 0 MW. At t=5 s, we changed the reference to -10 MW (discharging at rated power). At t=10 s, we switched to +10 MW (charging at rated power). The following table summarizes the expected and measured values:
| Quantity | Expected | Measured |
|---|---|---|
| Grid current amplitude at rated power (10 MW) | 233.28 A (peak) | ~233 A |
| Single submodule battery discharge current | ~77.87 A | ~77.5 A |
| Capacitor voltage ripple (peak-to-peak) | 1.84% (≈17 V) | ~1.8% |
| Battery current ripple (peak-to-peak) | 15% | 15.15% |
The active and reactive power waveforms tracked the references accurately with fast dynamics. The SOC of module A1, calculated by Coulomb counting in the model, matched the theoretical prediction within 0.1% over the test duration. This validates the battery model and the power control loop.
4.4 Intra-Phase SOC Balancing Test
To test the SOC balancing algorithm, we artificially set the initial SOCs for the first five modules of phase A as: 49.5%, 49.75%, 50%, 50.25%, 50.5%. The average SOC was 50%. The system was set to discharge at -10 MW. For the first 2 seconds, the balancing function was disabled; after t=2 s, it was activated. At t=5 s, we switched to charging at +10 MW. The results showed that without balancing, all modules exhibited identical SOC slopes. After enabling balancing, the SOC divergence was corrected: during discharge, modules with lower SOC discharged slower than those with higher SOC, and during charge, the lower-SOC modules charged faster. By the end of the charge period (t=8 s), the SOCs of all five modules converged to within 0.1% of each other. This demonstrates the effectiveness of the proposed sorting strategy.
5. Conclusion
In this work, I have presented a high-fidelity real-time simulation model for a high-voltage direct-connected large-capacity battery energy storage system. The model, developed on the OPAL-RT platform with CPU-FPGA co-simulation, can simulate up to 56 submodules per phase with a time step of 1 μs, while accurately representing the battery’s second-order RC dynamics. The control strategies, including decoupled dq power control, NLM modulation, and SOC-aware submodule sorting, were successfully implemented and validated through HIL tests under pre-charge, standalone, closed-loop power, and SOC balancing conditions. The close agreement between theoretical predictions and simulation results confirms that the model is a reliable tool for designing and optimizing high-voltage BESS. This work provides critical technical support for the engineering deployment of transformerless large-scale energy storage systems, enabling faster and safer development cycles.
The insights gained from this research can be extended to even higher voltage levels and larger cascades, contributing to the broader adoption of battery energy storage systems in modern power grids. I believe that the combination of advanced real-time simulation and robust control strategies will play a pivotal role in the future of energy storage technology.