In the field of photovoltaic (PV) power generation, different types of solar inverters are employed to interface solar panels with the grid. Among them, the voltage source inverter (VSI) is widely adopted due to its simple structure and mature control technology. However, VSI inherently requires a DC input voltage higher than the peak AC output voltage, which demands an additional boost stage or transformer under weak irradiance. In contrast, the current source inverter (CSI) exhibits unique advantages as one of the promising types of solar inverters: it possesses a boost capability, continuous DC-link current for easy MPPT implementation, and inherent overcurrent protection. The distinct characteristics of these types of solar inverters motivate the research on CSI-specific challenges. One critical issue in CSI is the necessity to avoid open-circuit faults in the DC-link inductor. This is achieved by inserting an overlap-time in the switching signals, during which both switches of the same bridge leg are simultaneously turned on. Unfortunately, this overlap-time introduces nonlinear current errors and degrades the power quality by generating low-order harmonic distortions in both inverter-side and grid-side currents. In this paper, I present a comprehensive analysis of the overlap-time effect and propose a novel compensation strategy based on digital filtering of capacitor voltages and current error look-up tables.
1. Topology and Overlap-Time Mechanism
The topology of a three-phase current source PV grid-connected inverter is composed of a DC-link inductor, a six-switch bridge with series diodes, a three-phase LC filter, and the grid. The DC-link current is regulated by an outer loop, while the grid currents are controlled in a synchronous reference frame using PI controllers with active damping and decoupling. The space vector modulation (SVM) is employed to generate the switching signals. Unlike VSI, where dead-time is inserted to prevent short circuits, CSI requires overlap-time to avoid open circuit. When the reference current vector lies in a certain sector, say sector I, the lower switches undergo commutation. The ideal switching pattern is shown in the original manuscript. In practice, due to the turn-off delay of semiconductor devices, the turn-off instant of the outgoing device is delayed, resulting in a brief period where both the outgoing and incoming switches are conducting – the overlap-time.
During the overlap-time, the DC-link current flows through the diode with the higher forward voltage when the commutation occurs between lower switches, or through the diode with the lower forward voltage when the commutation occurs between upper switches. This behavior depends solely on the instantaneous values of the three-phase capacitor voltages. Consequently, the actual inverter-side current differs from the intended one, creating current errors that accumulate over each carrier period.
2. Analysis of the Overlap-Time Effect
To quantify the effect, I establish equivalent circuits for representative commutations. Consider the transition from zero vector I7 to active vector I1 when the reference vector is in sector I. During the overlap-time, switches S4 and S6 are both on. If ua > ub, diode D4 remains forward biased and D6 is reverse biased, so the current vector remains I7, causing ia to decrease and ib to increase erroneously. Conversely, if ua < ub, D6 conducts and normal commutation occurs without error. Similarly, for upper-switch commutation in sector II, the condition is reversed: the current flows through the diode with the lower capacitor voltage. After analyzing all six sectors and possible capacitor voltage orders, I summarize the average current errors over one carrier period in the following table.
| Three-phase capacitor voltage relationship | Δia | Δib | Δic |
|---|---|---|---|
| ua > ub > uc | -2fstovidc | 0 | 2fstovidc |
| ua > uc > ub | -2fstovidc | 2fstovidc | 0 |
| ub > ua > uc | 0 | -2fstovidc | 2fstovidc |
| ub > uc > ua | 2fstovidc | -2fstovidc | 0 |
| uc > ua > ub | 0 | 2fstovidc | -2fstovidc |
| uc > ub > ua | 2fstovidc | 0 | -2fstovidc |
where fs is the switching frequency, tov is the overlap-time, and idc is the DC-link current. This table is valid for most linear modulation regions except near current zero-crossings and in over-modulation, where the error pattern may differ slightly.
3. Harmonic Characterization of the Overlap-Time Effect
Using the impulse equivalence principle, I approximate the pulsed current error signals as continuous square waves. For example, the waveform of Δia over one fundamental period is a piecewise constant function with amplitude ±2fstovidc during six intervals of 60° each. Using Fourier series expansion, I derive the harmonic components of Δia:
$$ \Delta i_a(t) = -\frac{4\sqrt{3}f_s t_{ov} i_{dc}}{\pi} \left[ \sin(\omega t) + \sum_{k=1}^{\infty} (-1)^k \left( \frac{\sin((6k-1)\omega t)}{6k-1} + \frac{\sin((6k+1)\omega t)}{6k+1} \right) \right] $$
This expression reveals that the overlap-time introduces 6k±1 order harmonics (5th, 7th, 11th, etc.) into the inverter-side current. The amplitudes are proportional to the overlap-time tov and the DC-link current idc. The fundamental component also decreases by an amount:
$$ \Delta I_a = I_a – \sqrt{ \left( I_a \sin\phi – \frac{4\sqrt{3}f_s t_{ov} i_{dc}}{\pi} \right)^2 + \left( I_a \cos\phi \right)^2 } $$
where φ is the power factor angle. The LC filter between the inverter and the grid has a transfer function that amplifies frequencies near its resonance. With typical filter parameters (L=4 mH, C=66 μF, R=0.5 Ω), the resonance frequency lies around 310 Hz, which amplifies the 5th (250 Hz) and 7th (350 Hz) harmonics significantly. Thus, the grid-side current suffers from notable low-order harmonic distortion.
4. Proposed Compensation Strategy
To mitigate the overlap-time effect, I propose a compensation scheme that operates in the dq synchronous reference frame. The key idea is to pre-compute the inverter-side current errors (Δia, Δib, Δic) using Table 1 based on the instantaneous three-phase capacitor voltages, then transform them into Δid and Δiq, and subtract these from the current references before the SVM modulator. Accurate determination of the capacitor voltage order is crucial. However, the capacitor voltages contain high-frequency ripple due to the inverter switching, which can cause misclassification if sampled directly. Therefore, I design a high-precision digital filter that extracts the fundamental component of the capacitor voltage without phase delay. The transfer function in the z-domain is:
$$ G_R(z) = \frac{40\omega_n T_s (1 – z^{-2})}{40\omega_n^2 T_s^2 + 4\omega_n T_s + 1 + 2(4 – 40\omega_n^2 T_s^2) z^{-1} + (40\omega_n^2 T_s^2 – 4\omega_n T_s + 1) z^{-2}} $$
where ωn=100π rad/s and Ts=1 ms is the sampling period. The difference equation for the a-phase voltage is:
$$ u_{af}(k) = \frac{1}{40\omega_n T_s} u_a(k) + \frac{1}{10} u_a(k-1) + \frac{1}{20} u_a(k-2) – \frac{1}{5} u_{af}(k-1) – \left(1 – \frac{1}{40\omega_n T_s}\right) u_{af}(k-2) $$
Simulation results confirm that the fundamental component is perfectly extracted with zero phase shift. The overall control structure includes a DC-link current outer loop and a grid current inner loop with PI controllers and active damping. The compensation signals Δid and Δiq are injected into the current reference path. The dynamic performance remains unchanged because the compensation does not alter the closed-loop transfer function.
5. Simulation Verification
I conduct simulations in MATLAB/Simulink with parameters: fs=10 kHz, idc=15 A, L=4 mH, C=66 μF, R=0.5 Ω. The grid voltage is 100 V (line-to-line RMS). Without overlap-time, the grid current THD is 0.43% and the inverter-side current THD is 96.53% (mainly due to switching harmonics). With tov=3 μs and no compensation, the grid-side current THD rises to 5.77%, with the 5th and 7th harmonics reaching 4.52% and 3.56%, respectively, of the fundamental. The fundamental amplitude decreases from 10.16 A to 9.71 A. After applying the proposed compensation, the grid-side current THD drops to 1.25% and the fundamental amplitude recovers to 10.15 A. The harmonic contents are suppressed effectively.
| tov (μs) | Fundamental (A) (No comp.) | Fundamental (A) (Comp.) | 5th harmonic (A) (No comp.) | 5th harmonic (A) (Comp.) | 7th harmonic (A) (No comp.) | 7th harmonic (A) (Comp.) |
|---|---|---|---|---|---|---|
| 0.5 | 9.835 | 9.897 | 0.037 | 0.005 | 0.025 | 0.003 |
| 1.0 | 9.776 | 9.896 | 0.069 | 0.009 | 0.049 | 0.005 |
| 1.5 | 9.713 | 9.896 | 0.098 | 0.017 | 0.074 | 0.009 |
| 2.0 | 9.656 | 9.890 | 0.140 | 0.028 | 0.097 | 0.018 |
| 2.5 | 9.592 | 9.890 | 0.175 | 0.041 | 0.122 | 0.027 |
| 3.0 | 9.543 | 9.876 | 0.213 | 0.068 | 0.148 | 0.049 |
The simulation results confirm that the proposed compensation effectively restores the fundamental amplitude and suppresses harmonics.
6. Experimental Validation
I build an experimental prototype using a TMS320F28335+CPLD controller, IGBT modules FF100R12RT4, and passive components as listed in the original paper. The DC-link current is set to 15 A, switching frequency 10 kHz, and overlap-time 3 μs. Without compensation, the grid-side current THD is 5.93%, and the 5th and 7th harmonics are 0.451 A and 0.356 A, respectively. After implementing the proposed compensation, the THD reduces to 1.65%, and the harmonic amplitudes drop to 0.119 A and 0.097 A. The fundamental amplitude increases from 9.69 A to 9.95 A. To demonstrate the necessity of the digital filter, I also test compensation without the filter. The filterless compensation yields inferior results due to voltage sampling errors, with THD rising to 2.65%.
| Condition | Fundamental (A) | 5th harmonic (A) | 7th harmonic (A) | THD (%) |
|---|---|---|---|---|
| No compensation | 9.69 | 0.451 | 0.356 | 5.93 |
| Compensation without filter | 9.94 | 0.215 | 0.132 | 2.65 |
| Proposed compensation | 9.95 | 0.119 | 0.097 | 1.65 |
Furthermore, I compare the proposed method with the literature method (based on stationary frame compensation) under a lower switching frequency of 1 kHz. At 1 kHz, the proposed dq-frame compensation achieves a THD of 3.95% (5th: 1.58%, 7th: 1.29%), while the stationary method yields THD of 5.22% (5th: 2.28%, 7th: 1.51%), confirming the superiority of the proposed scheme in low carrier ratio conditions.
7. Dynamic Performance
The dynamic response is tested by stepping the DC-link current reference from 10 A to 15 A. The settling time is about 80 ms in both uncompensated and compensated cases, because the compensation does not alter the control loop dynamics. The grid current waveform remains sinusoidal after the transient.
8. Conclusion
I have presented a thorough analysis of the overlap-time effect in current source grid-connected inverters, deriving the relationships between current errors and capacitor voltages, and the harmonic distortion expressions. The proposed compensation method, based on accurate detection of the fundamental component of capacitor voltages using a digital filter and a look-up table for current errors, effectively mitigates the overlap-time induced current distortion. Both simulation and experimental results validate that the strategy restores the fundamental amplitude and significantly reduces low-order harmonics without affecting the system’s dynamic performance. This work provides a practical solution for improving the power quality of CSI-based PV systems, which are increasingly recognized as competitive types of solar inverters.