In my research on photovoltaic grid-connected systems, I have focused on the characteristics and compensation methods of overlap-time in current source inverters (CSIs), which are one of the important types of solar inverter. Compared with voltage source inverters (VSIs), which are the most common types of solar inverter, CSIs offer inherent boost capability, continuous input current, and higher power density. However, CSIs require an overlap-time between switching signals to prevent open-circuit faults in the DC-link inductor, which introduces current distortion. In this paper, I present a detailed analysis of the overlap-time effect and propose a compensation strategy based on digital filtering of capacitor voltages and a look-up table method in the d-q reference frame. The work is validated through simulations and experiments.
The topology of a current source grid-connected inverter is shown in the following figure. It consists of a DC-link inductor, a three-phase bridge with six switches and series diodes, a filter capacitor bank, and grid-side inductors. This structure is typical for many types of solar inverter that require single-stage power conversion.
Overlap-Time Generation Mechanism
In space vector PWM (SVPWM) modulation for CSIs, the switching signals must include a turn-off delay to guarantee that the DC link never opens. When a switch is turned off, the next switch in the same leg is turned on after a short overlap period. During this overlap-time, two switches in the same leg are conducting simultaneously. For example, when the reference current vector lies in sector I, the lower switches (S₄, S₆, S₂) commutate, and the overlap-time occurs at each commutation instant. The switching signals with overlap-time are illustrated in the original paper.
Overlap-Time Effect Analysis
I established the equivalent circuit during the overlap-time. The current path depends on the polarity of the three-phase capacitor voltages. If the commutation is from a higher voltage to a lower voltage, the overlap-time does not introduce an average current error; otherwise, an error occurs. For the lower-leg commutation (sectors I, III, V), the DC current flows through the switch connected to the higher capacitor voltage. For the upper-leg commutation (sectors II, IV, VI), the current flows through the switch connected to the lower capacitor voltage. The average current errors over one carrier period are determined solely by the magnitude relationship of the three capacitor voltages, independent of the sector. Table I summarizes the average inverter-side current errors for all six voltage magnitude conditions.
| Capacitor Voltage Relationship | Δia | Δib | Δic |
|---|---|---|---|
| ua > ub > uc | -2fstovidc | 0 | 2fstovidc |
| ua > uc > ub | -2fstovidc | 2fstovidc | 0 |
| ub > ua > uc | 0 | -2fstovidc | 2fstovidc |
| ub > uc > ua | 2fstovidc | -2fstovidc | 0 |
| uc > ua > ub | 0 | 2fstovidc | -2fstovidc |
| uc > ub > ua | 2fstovidc | 0 | -2fstovidc |
where fs is the carrier frequency, tov is the overlap-time, and idc is the DC-link current. The above table is valid for most linear modulation regions. Near current zero-crossings or in over-modulation, the error pattern may differ, but the impact is minor.
Harmonic Characteristics of Overlap-Time Effect
Using the impulse equivalence principle, the average current error over a carrier period can be treated as a continuous square-wave signal. For example, the error in phase a, Δia, is a periodic waveform. I derived its Fourier series expansion:
$$
\Delta i_a = \frac{4\sqrt{3}f_s t_{ov} i_{dc}}{\pi} \left[ -\sin(\omega t) + \sum_{k=1}^{\infty}(-1)^k \left( \frac{\sin((6k-1)\omega t)}{6k-1} + \frac{\sin((6k+1)\omega t)}{6k+1} \right) \right]
$$
This expression shows that the overlap-time introduces (6k±1)th order harmonics in the inverter-side current, with amplitudes proportional to tov and idc. The fundamental component is also reduced. The grid-side current iag is filtered by the LC network. The transfer function from inverter-side current to grid-side current is:
$$
G_{i2ig}(s) = \frac{1}{LCs^2 + CRs + 1}
$$
For typical parameters (L=4mH, C=66μF, R=0.5Ω), the Bode plot shows a resonant peak near 300 Hz, which amplifies the 5th (250Hz) and 7th (350Hz) harmonics caused by the overlap-time. Therefore, the grid-side current exhibits significant 5th and 7th harmonic distortion.
Proposed Overlap-Time Compensation Method
My compensation scheme uses the control structure shown in the original paper. It consists of an outer DC-link current loop and an inner grid-side current loop in the d-q rotating frame. The overlap-time compensation block operates as follows: at each carrier cycle, sample the three capacitor voltages, pass them through a high-precision digital filter to extract the fundamental component, determine the voltage magnitude relationship, look up Table I to obtain Δia, Δib, Δic, transform to d-q quantities Δid and Δiq, and subtract them from the current controller outputs before SVPWM.
The digital filter is designed to extract the fundamental wave accurately without phase delay. Its z-domain transfer function is:
$$
G_R(z) = \frac{40\omega_n T_s (1-z^{-2})}{40\omega_n^2 T_s^2 + 4\omega_n T_s + 4 + (2\omega_n T_s – 4 – 40\omega_n^2 T_s^2)z^{-1} + (40\omega_n^2 T_s^2 – 4\omega_n T_s)z^{-2}}
$$
where ωn=100π rad/s, Ts is the sampling period. For Ts=1ms, the filter effectively removes ripple and retains the fundamental without phase shift, as verified in simulation.
Simulation Validation
I built a simulation model in MATLAB/Simulink. The DC-link current reference was set to 15A, switching frequency 10kHz, and overlap-time varied from 0 to 3μs. Without overlap-time (tov=0), the grid-side current THD was only 0.43%. With 3μs overlap-time, the grid-side current THD increased to 5.77%, with 5th harmonic of 4.52% and 7th harmonic of 3.56%. The inverter-side current fundamental amplitude dropped from 9.90A to 9.474A, and THD increased from 96.53% to 100.88% (the high THD is due to the inherent square-wave nature of inverter-side current). Table II and Table III show the inverter-side current harmonics for different overlap-time values without and with compensation.
| tov (μs) | Fundamental (A) | 5th (A) | 7th (A) | THD (%) |
|---|---|---|---|---|
| 0 | 9.90 | 0.005 | 0.003 | 96.53 |
| 0.5 | 9.835 | 0.037 | 0.025 | 97.20 |
| 1 | 9.776 | 0.069 | 0.049 | 97.89 |
| 1.5 | 9.713 | 0.098 | 0.074 | 98.61 |
| 2 | 9.656 | 0.140 | 0.097 | 99.35 |
| 2.5 | 9.592 | 0.175 | 0.122 | 100.09 |
| 3 | 9.543 | 0.213 | 0.148 | 100.88 |
| tov (μs) | Fundamental (A) | 5th (A) | 7th (A) | THD (%) |
|---|---|---|---|---|
| 0.5 | 9.897 | 0.005 | 0.003 | 96.55 |
| 1 | 9.896 | 0.009 | 0.005 | 96.56 |
| 1.5 | 9.896 | 0.017 | 0.009 | 96.57 |
| 2 | 9.890 | 0.028 | 0.018 | 96.57 |
| 2.5 | 9.890 | 0.041 | 0.027 | 96.57 |
| 3 | 9.876 | 0.068 | 0.049 | 96.65 |
The simulation results confirm that the proposed compensation effectively restores the fundamental amplitude and suppresses the 5th and 7th harmonics. For example, at tov=3μs, the grid-side current THD dropped from 5.77% to 1.25%, and fundamental amplitude recovered to 10.15A (close to the ideal 10.16A).
Experimental Verification
I conducted experiments on a CSI prototype. The system parameters are listed in Table IV.
| Component | Part Number | Value |
|---|---|---|
| AC voltage simulator | Chroma 61830 | 100V |
| DC input | DS1020 | 50V |
| Controller | TMS320F28335+CPLD | – |
| Voltage sensor | LV28-P | – |
| Current sensor | LA200-p | – |
| Switching devices | FF100R12RT4 | – |
| Diodes | MEA75-12DA | – |
| DC-link inductor | – | 8mH |
| AC-side inductor | – | 4mH |
| AC-side capacitor | – | 66μF |
| AC-side resistor | – | 0.5Ω |
With tov=3μs and no compensation, the grid-side current THD was 5.93%, 5th harmonic 0.451A, 7th harmonic 0.356A. After applying the proposed compensation, the THD reduced to 1.65%, 5th harmonic to 0.119A, 7th harmonic to 0.097A. The fundamental amplitude increased from 9.69A to 9.95A. The results are consistent with simulations.
I also tested the importance of the digital filter. Without the filter, the voltage samples contain ripple that leads to erroneous look-up decisions, resulting in a THD of 2.65% – worse than with the filter. Finally, I compared the proposed method with a conventional stationary-frame compensation method at a lower carrier frequency of 1kHz. At tov=3μs, the proposed method achieved a THD of 3.95%, while the stationary-frame method gave 5.22% due to angle errors in the coordinate transformation. This demonstrates the advantage of the rotating-frame approach.
Dynamic Performance
The dynamic response was tested by stepping the DC-link current reference from 10A to 15A. The settling time was about 80ms both with and without compensation, confirming that the proposed method does not affect the closed-loop dynamics.
Conclusion
In this work, I have systematically analyzed the overlap-time effect in current source grid-connected inverters, which are a key type of solar inverter for boosting applications. I derived the relationship between current errors and capacitor voltages, and the harmonic expressions. A compensation strategy based on digital filtering of capacitor voltages and table lookup in the d-q frame was proposed. Simulations and experiments verified that the method reduces grid-side current THD from over 5% to below 2% at a 3μs overlap-time, and effectively suppresses the 5th and 7th harmonics. The compensation is robust and does not degrade dynamic performance. This work provides a practical solution for improving the power quality of CSI-based photovoltaic systems.
Future work can extend the method to handle current zero-crossing and over-modulation regions more precisely, and to apply similar ideas to other types of solar inverter topologies that experience overlap-time issues.