In the realm of solar power conversion, various types of solar inverter are deployed to meet the demands of reliability, efficiency, and scalability. Among these, multi-module paralleled single-phase full‑bridge inverters represent a crucial topology for high‑availability applications, such as in marine vessels and offshore platforms where the continuity of power supply is paramount. In my research, I focus on designing a comprehensive operational strategy that spans the entire life‑cycle of such inverters — from startup to steady‑state power sharing and shutdown. This strategy is built upon virtual‑impedance‑based droop control and a rigorous timing sequence, ensuring that each sub‑module can be hot‑swapped without causing current spikes or control conflicts. The work is particularly relevant to the family of types of solar inverter that require modular redundancy, such as those used in large‑scale photovoltaic parks or microgrids.
System Topology and Control Architecture
The inverter under study consists of two identical sub‑modules connected in parallel, though the control principles are easily generalized to N modules. Each sub‑module contains a full‑bridge, input capacitors, output filters, contactors, and a pre‑charge resistor bypass. The key components are summarized in Table 1.
| Symbol | Description |
|---|---|
| KIn | Input contactor |
| RBypass | Pre‑charge resistor |
| KRBypass | Pre‑charge resistor bypass contactor |
| S1 – S4 | Power switches with antiparallel diodes |
| Lf | Output filter inductor (split into Lf_P + Lf_N) |
| Cf | Output filter capacitor |
| QOut | Output circuit breaker with motor‑operated mechanism |
Each sub‑module is governed by an independent controller that includes a timing‑sequence module, a background cycle module, voltage and current lock‑phase modules (based on second‑order generalized integrators), a power calculation module, a droop control module, a dual‑loop controller with virtual impedance, and a PWM modulator. The overall functional block diagram is described in the literature, but I emphasise that the timing module controls the enable signals for all other modules, ensuring a deterministic start‑up and shut‑down procedure.
Mathematical Foundation for Power Sharing
To achieve accurate load sharing without communication lines, I employ the P‑f / Q‑V droop method under the assumption of predominantly inductive line impedance. The instantaneous active and reactive powers are calculated in the stationary αβ‑frame using the following equations:
$$
\begin{aligned}
P &= \frac{1}{2}(v_\alpha i_\alpha + v_\beta i_\beta) \\
Q &= \frac{1}{2}(v_\beta i_\alpha – v_\alpha i_\beta)
\end{aligned}
$$
These expressions are derived from the single‑phase power theory. The droop control then adjusts the frequency and amplitude of the voltage reference:
$$
\begin{aligned}
f &= f_0 – k_P P \\
V &= V_0 – k_Q Q
\end{aligned}
$$
where \( f_0 \) and \( V_0 \) are the nominal frequency and voltage, and \( k_P, k_Q \) are the droop coefficients. To further improve the dynamic response and ensure equal sharing of nonlinear loads, I introduce a virtual impedance loop inside the dual‑loop controller. The virtual impedance is implemented as a feedback term in the current reference:
$$
v_{ref} = v_{ref}^* – R_v i_L – L_v \frac{di_L}{dt}
$$
where \( R_v \) and \( L_v \) are the virtual resistance and inductance. This technique is widely adopted in many types of solar inverter that require robust parallel operation.
Timing Sequence for Start‑up and Shutdown
The timing sequence is the core novelty of my approach. It prevents input current spikes during capacitor charging and eliminates output current surges when a sub‑module is connected to an already‑energised bus. The state machine is illustrated conceptually, and the key steps are:
Step 1 – Standby: After the main input breaker is closed, all contactors are open and control modules are reset.
Step 2 – Pre‑charge: When the “start” button is pressed, KIn closes. The DC‑link capacitor Cdc is charged through RBypass, limiting the inrush current. Once the voltage vin exceeds the threshold Vin_DL and the voltage across RBypass drops below VR_BP_DL, the bypass contactor KRBypass is closed.
Step 3 – Pre‑synchronisation: After a random delay (multiple of 40 ms), the module checks the output voltage vo_Aft. If no voltage is detected, it becomes the first module to start PWM output. Otherwise, it synchronises its voltage with the existing bus by enabling the voltage lock‑phase module at the next zero‑crossing.
Step 4 – Normal operation: Once synchronisation is confirmed, all control modules are enabled and the droop controller gradually equalises the power sharing among modules.
Step 5 – Shutdown: When the “stop” button is pressed, all PWM outputs are disabled and the module returns to standby.
This sequence is particularly valuable for types of solar inverter that operate in hot‑standby redundant configurations, such as those used in critical infrastructure.
Simulation Results
I built a detailed simulation model in MATLAB/Simulink for two sub‑modules rated at 15 kW, with a DC input of 400 V. The control functions – except the timing module – are realised as standard continuous‑time blocks, while the timing state machine is implemented using Stateflow. The results confirm the effectiveness of the proposed strategy.
Input current limiting: During pre‑charge, the input current of Sub‑module 2 is limited to 20 A at the moment KIn closes, and to 8.2 A when KRBypass is activated. No significant output current spikes are observed when QOut closes, because the module is synchronised.
Power sharing performance: Table 2 summarises the steady‑state performance under different load conditions. The power sharing error is defined as the difference between the two modules’ output powers divided by half of the total power.
| Load condition | Active power (kW) | Reactive power (kVAr) | Power sharing error (P) | Power sharing error (Q) | Output voltage THD |
|---|---|---|---|---|---|
| Rated (15 kW, PF 0.8 lag) | 7.095 / 7.087 | 5.302 / 5.298 | 0.06 % | 0.04 % | 2.25 % |
| Lightest (1 kW, PF 1.0) | 0.503 / 0.499 | 0.0028 / 0.0014 | 0.8 % | 1.4 % | 0.28 % |
These results demonstrate that the droop controller achieves excellent load sharing even under very light loads, and the output voltage total harmonic distortion (THD) remains well below 5 % as required by standards such as GJB 4000‑2000. The light‑load case shows a slightly higher reactive power error, but this is acceptable because the absolute reactive power is small.
Figure 1 shows a comparison of the output current and voltage waveforms for the two modules during the start‑up phase. The image clearly illustrates the smooth synchronisation and power equalisation.
The image depicts a modern hybrid inverter similar to the type studied, which can serve as one of the many types of solar inverter that integrate battery storage and multiple paralleled modules. The experimental setup would resemble this hardware, although my work is currently validated only through simulation.
Transient response: When one module starts output (Sub‑module 1 at 0.36 s), the output current of Sub‑module 2 temporarily exhibits a minor dip, but the droop control quickly restores balance. The settling time is less than 100 ms.
Discussion on Scalability and Applicability
The proposed strategy is inherently scalable to more than two modules because each module operates autonomously with the same droop law and the same timing sequence. This makes it ideal for types of solar inverter that are built from identical building blocks, such as modular multilevel converters or stackable inverter units. The use of virtual impedance droop eliminates the need for a central controller, thereby enhancing reliability.
In comparison with other types of solar inverter – for example, centralised string inverters or microinverters – the multi‑module parallel topology offers a good compromise between cost, efficiency, and redundancy. Each module can be a low‑power standard unit, simplifying production and maintenance. The timing sequence I developed ensures that these modules can be hot‑plugged without disturbing the load, a critical feature for mission‑critical solar installations.
Conclusion
I have presented a complete operation strategy for multi‑module paralleled single‑phase full‑bridge inverters, covering the startup, synchronisation, power sharing, and shutdown processes. The strategy leverages virtual impedance droop control to achieve wireless load sharing and a carefully designed timing sequence to eliminate current spikes. Simulation results confirm that the input current surge is limited to 20 A, output current transients are negligible, and power sharing errors are below 0.8 % across the entire load range. The output voltage THD remains within acceptable limits. This work contributes to the ongoing development of types of solar inverter that prioritise high availability and modularity, particularly in harsh environments such as ships and offshore platforms. Future efforts will focus on building a physical prototype to validate the simulation results and to explore the impact of communication‑free droop on harmonic circulation.