In my research, I focus on the design, analysis, and experimental validation of non-isolated single-phase common-ground solar inverters. The central motivation is to remove the leakage current path that appears when a solar inverter has no isolation transformer, while at the same time achieving flexible voltage conversion, low harmonic distortion, and high efficiency. I treat the solar inverter as the key interface between a photovoltaic array and the utility grid, and I investigate how common-ground structures can make the solar inverter inherently safer and more compact. I also study how switched-capacitor and buck-boost principles can be embedded into the solar inverter so that a wide input voltage range can be accommodated without sacrificing output power quality.
Research Background and Motivation
Renewable energy has become a central part of modern power systems because the demand for clean electricity continues to rise. Among renewable sources, photovoltaic generation is especially attractive because it is modular, scalable, and suitable for both centralized and distributed deployment. In a photovoltaic system, the solar inverter converts the direct-current output of the photovoltaic array into alternating current that can be injected into the grid. Therefore, the performance of the solar inverter directly influences the overall energy yield, reliability, and safety of the photovoltaic installation.
Isolated solar inverters use a transformer to provide galvanic isolation between the photovoltaic array and the grid. This isolation prevents common-mode leakage current from flowing through the parasitic capacitance between the photovoltaic panels and the ground. However, the transformer increases volume, weight, cost, and loss. A non-isolated solar inverter eliminates the transformer and therefore offers higher power density, lower cost, and higher efficiency. The main challenge is that the non-isolated solar inverter lacks galvanic isolation, so a common-mode voltage can drive a leakage current through the parasitic capacitance of the photovoltaic array. This leakage current can cause electromagnetic interference, grid current distortion, device overheating, and safety hazards.
I compare the two architectures in Table 1. The comparison shows why the non-isolated solar inverter is attractive for distributed photovoltaic systems, but it also shows why leakage current suppression is the key design problem.
| Feature | Isolated solar inverter | Non-isolated solar inverter |
|---|---|---|
| Galvanic isolation | Yes, provided by transformer | No |
| Leakage current path | Strongly reduced or blocked | Present through parasitic capacitance |
| Volume and weight | Large due to transformer | Small and compact |
| Cost | Higher | Lower |
| Efficiency | Reduced by transformer loss | Higher in many cases |
| Power density | Lower | Higher |
| Main design challenge | Transformer design and loss | Leakage current and common-mode voltage |
The leakage current problem is not only a power quality issue. It is also a safety issue. International standards specify strict limits for leakage current in transformerless photovoltaic systems. If the leakage current exceeds the limit, the solar inverter must disconnect from the grid within a very short time. I summarize representative limits in Table 2.
| Leakage current detection value | Required action time |
|---|---|
| 30 mA | 0.3 s |
| 60 mA | 0.15 s |
| 100 mA | 0.04 s |
My research therefore starts from the following question: how can a single-phase solar inverter remain transformerless, compact, and efficient while keeping the common-mode voltage constant or zero? The answer I develop is based on common-ground topologies. In a common-ground solar inverter, the negative terminal of the photovoltaic array is directly connected to the neutral point of the grid. As a result, the common-mode voltage is theoretically clamped to zero, and the leakage current path through the parasitic capacitance is eliminated. I then integrate additional voltage conversion and multilevel output capability into the common-ground solar inverter so that it can handle wide input voltage variations and produce high-quality grid current.
Leakage Current Generation and Common-Mode Modeling
To understand leakage current in a non-isolated solar inverter, I begin with the parasitic capacitance between the photovoltaic array and the ground. A photovoltaic panel contains cells, glass, encapsulant, backsheet, and a metal frame. The panel is mounted outdoors, often on a grounded metal support. This arrangement creates a capacitance between the photovoltaic terminals and the ground. The value of this parasitic capacitance depends on panel area, mounting structure, humidity, dust, and environmental conditions. In dry conditions it may be relatively small, but in wet or dirty conditions it can increase significantly. The parasitic capacitance provides a path for common-mode current when the solar inverter switches at high frequency.
The common-mode voltage of a single-phase solar inverter can be defined from the two bridge output nodes. Let the inverter output nodes be A and B, and let N be a reference node on the DC side. The common-mode voltage is
$$U_{cm}=\frac{U_{AN}+U_{BN}}{2}$$
and the differential-mode voltage is
$$U_{dm}=U_{AN}-U_{BN}$$
From these definitions, the two node voltages can be expressed as
$$U_{AN}=U_{cm}+\frac{U_{dm}}{2}$$
$$U_{BN}=U_{cm}-\frac{U_{dm}}{2}$$
For a grid-connected solar inverter, the grid frequency is much lower than the switching frequency, so the grid can be approximated as a short circuit for high-frequency common-mode analysis. Using a Thevenin equivalent of the filter and grid, the simplified common-mode voltage can be written as
$$U_{ccm}=U_{CM}+U_{CD}\frac{L_1-L_2}{2(L_1+L_2)}$$
where \(L_1\) and \(L_2\) are the filter inductances and \(U_{CD}\) is the voltage difference between the equivalent terminals. If the filter is symmetrical, that is, \(L_1=L_2\), then the second term vanishes and
$$U_{ccm}=\frac{U_{AN}+U_{BN}}{2}$$
The leakage current through the parasitic capacitance is
$$i_{cm}=C_{pv}\frac{dU_{ccm}}{dt}$$
This equation is the core of the leakage current problem. It shows that even if the parasitic capacitance \(C_{pv}\) cannot be removed, the leakage current can be suppressed by keeping the common-mode voltage constant. If \(U_{ccm}\) is constant, its derivative is zero, and the leakage current is ideally zero. In a common-ground solar inverter, the negative terminal of the photovoltaic array is connected directly to the grid neutral point, so \(U_{BN}=0\) and the common-mode voltage is clamped to zero. Therefore, the common-ground solar inverter is theoretically immune to common-mode leakage current.
I summarize the leakage current behavior of different topology classes in Table 3. The comparison highlights why common-ground structures are superior for leakage current suppression.
| Topology class | Common-mode voltage behavior | Leakage current suppression | Main limitation |
|---|---|---|---|
| Full-bridge with unipolar modulation | High-frequency variation | Poor | Large leakage current |
| Full-bridge with bipolar modulation | Constant at half of DC bus | Good | High harmonic distortion |
| H5, H6, HERIC and derivatives | Partially clamped during freewheeling | Moderate to good | Additional switches and complex modulation |
| Half-bridge NPC and T-type | Naturally constant | Good | Low voltage gain and high device count |
| Common-ground solar inverter | Theoretically zero | Excellent | Requires special topology and control |
Review of Existing Suppression Methods for the Solar Inverter
Before I present my proposed topologies, I review the main families of non-isolated solar inverter topologies. This review helps me identify the advantages and disadvantages that motivate my design choices.
Full-Bridge Solar Inverter Topologies
The full-bridge solar inverter is widely used because it has a symmetric structure and high DC voltage utilization. A basic full-bridge solar inverter with unipolar modulation produces a three-level output voltage, which reduces harmonic distortion. However, unipolar modulation also produces a high-frequency common-mode voltage, which generates a large leakage current. Bipolar modulation can keep the common-mode voltage nearly constant, but the output voltage has only two levels and therefore requires a larger filter and produces higher harmonic distortion.
To overcome this trade-off, several improved full-bridge solar inverter topologies have been proposed. The H5 topology adds an extra switch on the DC side to decouple the photovoltaic array from the grid during freewheeling. The H6 topology adds two switches and can be implemented with either AC-side or DC-side decoupling. The HERIC topology adds two switches on the AC side and creates a freewheeling path that separates the DC side from the AC side. These topologies reduce leakage current, but they do not always keep the common-mode voltage perfectly constant. The residual voltage variation caused by switch parasitic capacitance and dead time can still produce leakage current. In addition, the extra switches increase cost and conduction loss.
Another approach is the T-type five-level full-bridge solar inverter. This topology combines a full bridge with a T-type neutral-point-clamped branch. It produces five output levels, which reduces harmonic distortion and filter size. The common-mode voltage is partially clamped, but it still changes between positive and negative half cycles and can fluctuate with the DC bus. Therefore, the leakage current is reduced but not completely eliminated.
I summarize the full-bridge family in Table 4.
| Topology | Output levels | Common-mode voltage | Leakage current | Main drawback |
|---|---|---|---|---|
| Basic full bridge, unipolar | 3 | High-frequency variation | High | Large leakage current |
| Basic full bridge, bipolar | 2 | Constant | Low | High THD and large filter |
| H5 | 3 | Clamped during freewheeling | Moderate | Extra switch and loss |
| H6 | 3 | Clamped during freewheeling | Moderate | More switches and complex control |
| HERIC | 3 | Clamped during freewheeling | Moderate | AC-side switches and loss |
| T-type five-level full bridge | 5 | Partially clamped | Moderate | Many switches and residual leakage |
Half-Bridge Solar Inverter Topologies
The half-bridge solar inverter has a natural advantage for leakage current suppression because its common-mode voltage is inherently constant. The basic half-bridge solar inverter connects the grid neutral point to the midpoint of the DC bus capacitor. The common-mode voltage remains at half of the DC bus voltage, so the leakage current is small. However, the half-bridge solar inverter has only two output levels, and its output voltage is limited to half of the DC bus voltage. This means that the DC input voltage must be very high, which is not always compatible with photovoltaic arrays.
The neutral-point-clamped half-bridge solar inverter extends the basic half-bridge to three levels. The NPC topology reduces the voltage stress of each switch to half of the DC bus voltage. However, the diode clamping branch causes unequal loss distribution. The active NPC topology replaces diodes with active switches and improves loss distribution, but it increases control complexity and risk of shoot-through. The T-type NPC solar inverter uses four active switches and produces a three-level output. It has lower conduction loss than the NPC topology, but it still lacks voltage boost capability. The stacked NPC topology combines the advantages of the I-type and T-type structures and can balance losses better, but it requires more devices and more complex modulation.
In general, half-bridge solar inverter topologies are well suited for medium and high voltage systems because their conduction loss decreases as the voltage level increases. However, they are not ideal for low-voltage photovoltaic arrays because they cannot boost the voltage. I summarize the half-bridge family in Table 5.
| Topology | Output levels | Voltage stress | Leakage current | Voltage gain | Main drawback |
|---|---|---|---|---|---|
| Basic half bridge | 2 | \(V_{dc}\) | Low | 0.5 | Low output voltage and high THD |
| NPC half bridge | 3 | \(V_{dc}/2\) | Low | 0.5 | Unequal loss and no boost |
| Active NPC half bridge | 3 | \(V_{dc}/2\) | Low | 0.5 | More switches and dead-time risk |
| T-type NPC half bridge | 3 | \(V_{dc}/2\) | Low | 0.5 | No boost and four active switches |
| Stacked NPC half bridge | 3 | \(V_{dc}/2\) | Low | 0.5 | Complex structure and many devices |
Common-Ground Solar Inverter Topologies
Common-ground solar inverter topologies connect the negative terminal of the photovoltaic array directly to the grid neutral point. This connection forces the common-mode voltage to zero and eliminates the leakage current path. Common-ground topologies can be divided into capacitive and inductive types.
Capacitive common-ground solar inverters use an intermediate capacitor to store energy and provide voltage support during the negative half cycle. Some designs use only four switches and produce a single-phase three-level output. However, the storage capacitor must handle a large voltage ripple, and the positive and negative half cycles may not be symmetric. Other designs use a virtual DC bus or high-frequency charging of the intermediate capacitor, which reduces the required capacitance but can increase the current stress of some switches. Active switch replacement of diodes can optimize the freewheeling path and reduce current stress, but the control complexity increases.
Inductive common-ground solar inverters use an inductor as the intermediate energy transfer element. This approach can provide buck-boost capability, which is useful for wide input voltage ranges. Some designs integrate the intermediate inductor with the filter capacitor to form a Buck-Boost structure. Others use a nonlinear PWM strategy to reduce output voltage harmonics. A dual-DC symmetric structure can operate symmetrically in the positive and negative half cycles, but capacitor voltage imbalance can cause output asymmetry. Overall, common-ground topologies are the most promising for leakage current elimination, but they require careful design to achieve voltage gain, capacitor voltage balance, and low harmonic distortion.
I summarize the common-ground family in Table 6.
| Common-ground type | Energy storage element | Voltage gain | Leakage current | Main challenge |
|---|---|---|---|---|
| Capacitive type | Intermediate capacitor | Limited | Theoretically zero | Large capacitor and asymmetry |
| Inductive type | Intermediate inductor | Buck-boost | Theoretically zero | Efficiency and current stress |
| Switched-capacitor type | Capacitor network | Multilevel boost | Theoretically zero | Capacitor voltage balance |
Proposed Three-Level Common-Ground Solar Inverter with Buck-Boost Capability
I propose a three-level common-ground solar inverter that can operate in both buck and boost modes. The topology includes a switching-boost-buck module, four switches, and an LC filter. The switching-boost-buck module contains one inductor, one capacitor, and one diode. It allows the solar inverter to handle a wide input voltage range and to perform maximum power point tracking. The common-ground structure connects the negative terminal of the photovoltaic array to the grid neutral point, so the common-mode voltage is clamped to zero and the leakage current is theoretically eliminated.
The topology has the following features:
- It eliminates common-mode leakage current by using a common-ground structure.
- It provides both buck and boost operation for wide input voltage variation.
- It has a soft-charging capability for the DC bus capacitor, which reduces current stress.
- It has good symmetry between positive and negative half cycles.
- It requires a small filter because the output is three-level.
I define the main operating modes of the three-level common-ground solar inverter in Table 7. The inverter has three modes in each half cycle.
| Mode | Active switches | Inductor \(L_1\) state | Output voltage | Description |
|---|---|---|---|---|
| Mode 1 | \(S_{in1}, S_2, S_4\) | Charging from \(v_{in}\) | Positive | PV array charges \(L_1\); \(C_{in}\) supplies the grid |
| Mode 2 | \(S_1, S_4\) | Discharging to \(C_{in}\) | Positive | \(L_1\) transfers energy to \(C_{in}\) |
| Mode 3 | \(S_1, S_4\) | Zero current | Positive | Freewheeling stage |
| Mode 4 | \(S_{in1}, S_1, S_3\) | Charging from \(v_{in}\) | Negative | PV array charges \(L_1\); negative half cycle |
| Mode 5 | \(S_2, S_3\) | Discharging to \(C_{in}\) | Negative | \(L_1\) transfers energy to \(C_{in}\) |
| Mode 6 | \(S_2, S_3\) | Zero current | Negative | Freewheeling stage |
The inductor current in the discontinuous conduction mode can be written as follows. During Mode 1,
$$i_{L1}(t)=\frac{v_{in}}{L_1}(t-t_0)$$
During Mode 2,
$$i_{L1}(t)=i_{L1}(t_1)-\frac{V_{Cin}}{L_1}(t-t_1)$$
During Mode 3,
$$i_{L1}(t)=0$$
The negative half cycle has the same equations with opposite current direction. The input and output currents are symmetric in the positive and negative half cycles.
Control Design for the Three-Level Solar Inverter
I use a proportional-resonant controller to achieve zero steady-state error for the sinusoidal grid current. The transfer function is
$$G_{PR}(s)=K_P+\frac{K_R s}{s^2+\omega_0^2}$$
where \(K_P\) is the proportional gain, \(K_R\) is the resonant gain, and \(\omega_0\) is the grid angular frequency. I tune the controller so that it tracks the reference current with good dynamic response and low steady-state error. The modulation stage compares the controller output with a triangular carrier to generate the PWM signals for the switches. The control logic is simple because the common-ground structure does not require complex common-mode voltage regulation.
Component Selection for the Three-Level Solar Inverter
The input inductor \(L_1\) is selected from the current ripple requirement. In the buck-boost module,
$$\Delta i_{L1}=\frac{d_1 v_{in}}{L_1 f_s}$$
Therefore,
$$L_1=\frac{(1-d_1)^2 R}{2 f_s \gamma}$$
where \(f_s\) is the switching frequency, \(R\) is the equivalent load resistance, and \(\gamma\) is the current ripple ratio. I choose \(d_1=0.5\), \(R=50\,\Omega\), and \(L_1=100\,\mu H\) for discontinuous conduction operation.
The output inductor \(L_2\) is selected from the output current ripple requirement:
$$\Delta i_{L2}=\frac{(1-d)V_{Cin}}{L_2 f_s}$$
I choose \(L_2=100\,\mu H\) for the experimental prototype.
The DC bus capacitor \(C_{in}\) is selected from the voltage ripple requirement:
$$\Delta V_{Cin}=\frac{d(t)|i_g(t)|}{C_{in} f_s}$$
I design the maximum voltage ripple to be less than five percent of the DC bus voltage.
Loss Analysis for the Three-Level Solar Inverter
I divide the losses into conduction loss, switching loss, inductor core loss, and capacitor loss. The conduction loss of a semiconductor device is
$$P_{cond}=i_{ds}(t)V_{ds}(t)=i_{ds}^2(t)R_{ds}$$
The switching loss is
$$P_{sw}=f_s I_d V_{ds}\frac{t_r+t_f}{2}$$
The inductor core loss is
$$P_{core}=a \Delta B^b f^c$$
where \(a\), \(b\), and \(c\) are core loss coefficients, \(\Delta B\) is the flux density variation, and \(f\) is the frequency. The capacitor loss is
$$P_C=\frac{1}{T}\int_0^T i_C^2(t)R_{ESR}\,dt$$
I summarize the loss distribution for a 300 W output in Table 8. The results show that the switch \(S_1\) has relatively high loss because its body diode conducts during the negative half cycle.
| Component | Loss contribution |
|---|---|
| \(S_{in1}\) | Moderate |
| \(S_1\) | High |
| \(S_2\) | Moderate |
| \(S_3\) | Moderate |
| \(S_4\) | Moderate |
| \(D_1\) | Moderate |
| \(L_1\) and \(L_2\) | Low to moderate |
| \(C_{in}\) and \(C_o\) | Low |
Simulation and Experimental Results for the Three-Level Solar Inverter
I built a simulation model and a 300 W experimental prototype. The parameters are listed in Table 9.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Output power | 300 W | Inductor \(L_2\) | 2 mH |
| Switching frequency | 20 kHz | Capacitor \(C_{in}\) | 220 \(\mu F\) |
| Line frequency | 50 Hz | Capacitor \(C_o\) | 1.5 \(\mu F\) |
| Inductor \(L_1\) | 100 \(\mu H\) | Load | 100 \(\Omega\) |
The simulation results show that the inductor current \(i_{L1}\) operates in discontinuous conduction mode and is symmetric in the positive and negative half cycles. The DC bus capacitor voltage \(V_{Cin}\) has a small ripple, which confirms the soft-charging capability. The output voltage and current are sinusoidal with a THD of 1.39 percent. When the load changes from 100 \(\Omega\) to 130 \(\Omega\), the output current settles quickly to a new steady state. When the input voltage steps from 75 V to 100 V, the output current also settles quickly without oscillation. These results confirm that the control strategy is robust.
In the experimental prototype, the input voltage was stepped from 60 V to 100 V. The grid current responded quickly and maintained a THD below 3.7 percent. The solar inverter also provided reactive power support. It injected about 300 W of active power before the reference change and about 150 VAR of reactive power after the reference change. The measured leakage current was only about 4 mA, which is far below the standard limit. The efficiency remained above 94.2 percent over the 200 W to 400 W range, with a peak efficiency of 97.9 percent.
Proposed Five-Level Common-Ground Solar Inverter with Switched-Capacitor Network
I also propose a five-level common-ground solar inverter that uses a switched-capacitor network. The topology combines a Boost stage with a switched-capacitor network. The switched-capacitor network contains two capacitors. By changing the series-parallel connection of the two capacitors, the solar inverter produces five output voltage levels. This reduces the harmonic content of the output voltage, lowers the voltage stress of the devices, improves electromagnetic immunity, and reduces the size of the output filter. The negative terminal of the photovoltaic array is connected directly to the grid neutral point, so the common-mode voltage is zero and the leakage current is theoretically eliminated.
The topology contains eight switches, one diode, two capacitors, and an LC filter. The switch states are listed in Table 10. The switches \(S_1\) and \(S_7\) have the same driving signal, and \(S_4\) and \(S_5\) have the same driving signal. The switches \(S_2\) and \(S_3\), \(S_5\) and \(S_6\), and \(S_7\) and \(S_8\) are complementary.
| Mode | \(S_1\) | \(S_2\) | \(S_3\) | \(S_4\) | \(S_5\) | \(S_6\) | \(S_7\) | \(S_8\) | \(v_g\) |
|---|---|---|---|---|---|---|---|---|---|
| M1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | \(V_{Cin}\) |
| M2 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | \(V_{Cin}/2\) |
| M3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| M4 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| M5 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | \(-V_{Cin}/2\) |
| M6 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | \(-V_{Cin}\) |
The ideal output voltages for the six modes are
$$v_g = V_{Cin} \quad \text{in M1}$$
$$v_g = \frac{V_{Cin}}{2} \quad \text{in M2}$$
$$v_g = 0 \quad \text{in M3 and M4}$$
$$v_g = -\frac{V_{Cin}}{2} \quad \text{in M5}$$
$$v_g = -V_{Cin} \quad \text{in M6}$$
When device voltage drops are considered, the output voltage in each mode can be adjusted by the on-state voltage of the switches and diodes. For example, in M1,
$$v_g = V_{Cin} – 2V_{ON-S} – V_{ON-VD} \quad \text{for } i_g > 0$$
$$v_g = V_{Cin} + 2V_{ON-VD} \quad \text{for } i_g < 0$$
In M2,
$$v_g = \frac{V_{Cin}}{2} – 2V_{ON-S} – V_{ON-VD} \quad \text{for } i_g > 0$$
$$v_g = \frac{V_{Cin}}{2} + 2V_{ON-S} + V_{ON-VD} \quad \text{for } i_g < 0$$
These equations show that each mode can support both positive and negative output current, so the solar inverter can provide reactive power to the grid.
Feedforward Space Vector Modulation for the Five-Level Solar Inverter
In practice, the capacitor voltages are not exactly equal to half of the DC bus voltage because the capacitors have finite capacitance and voltage ripple. If a conventional space vector modulation scheme assumes perfect capacitor voltage balance, the output voltage will be distorted. To solve this problem, I propose a feedforward space vector modulation strategy. The strategy detects the capacitor voltages, determines the correct voltage vector region, and adjusts the duty cycles so that the output voltage is decoupled from the capacitor voltage ripple.
I define the reference output voltage as
$$v_{g-ref}(t)=d(t)V_{Cin}$$
$$d(t)=A_m \sin(\omega t)$$
where \(A_m\) is the modulation coefficient. The duty cycles of two adjacent vectors are obtained from
$$
\begin{bmatrix}
d_M(t) \\
d_N(t)
\end{bmatrix}
=
\begin{bmatrix}
V_M & V_N \\
1 & 1
\end{bmatrix}^{-1}
\begin{bmatrix}
v_{g-ref}(t) \\
1
\end{bmatrix}
$$
where \(V_M\) and \(V_N\) are the output voltages of the adjacent switching vectors. For example, if the reference voltage is in region R4, the duty cycles of M1 and M2 are
$$
\begin{bmatrix}
d_1(t) \\
d_2(t)
\end{bmatrix}
=
\begin{bmatrix}
V_{Cin} & \frac{V_{Cin}}{2} \\
1 & 1
\end{bmatrix}^{-1}
\begin{bmatrix}
v_{g-ref}(t) \\
1
\end{bmatrix}
$$
The duty cycles of the switches are then calculated from the region. The duty cycles for \(S_1\), \(S_2\), and \(S_4\) in different regions are listed in Table 11.
| Region | \(d_{S1}\) | \(d_{S2}\) | \(d_{S4}\) |
|---|---|---|---|
| R1 | 1 | 0 | \(\frac{V_{Cin}+d(t)V_{Cin}}{2V_C}\) |
| R2a | 1 | 1 | \(\frac{V_{Cin}+d(t)V_{Cin}}{V_C}\) |
| R2b | \(\frac{V_{Cin}-d(t)V_C}{V_{Cin}-V_C}\) | 0 | \(\frac{V_{Cin}-d(t)V_C}{V_{Cin}-V_C}\) |
| R3a | 1 | 1 | \(\frac{V_{Cin}(d(t)-1)}{2V_C}\) |
| R3b | \(\frac{V_{Cin}(d(t)+1)}{V_{Cin}-V_C}\) | \(\frac{V_{Cin}(d(t)+1)}{V_{Cin}-V_C}\) | \(\frac{V_{Cin}(d(t)+1)}{V_{Cin}-V_C}\) |
| R4 | \(\frac{V_{Cin}(d(t)-1)}{V_C}\) | 1 | \(\frac{V_{Cin}(d(t)-1)}{V_C}\) |
The region selection is based on the reference voltage and the measured capacitor voltage. The controller chooses between redundant pairs R2a/R2b and R3a/R3b according to the input voltage error and the output current direction. This selection minimizes the output voltage harmonic distortion.
Control Strategy for the Five-Level Solar Inverter
The overall control strategy includes maximum power point tracking, a voltage loop, a phase-locked loop, and a current loop. The maximum power point tracking block generates the reference DC bus voltage. The voltage loop uses a PI controller to regulate the DC bus voltage and generate the current amplitude reference. The phase-locked loop synchronizes the output current with the grid voltage. The current loop uses a proportional-resonant controller to track the sinusoidal current reference. The transfer functions are
$$G_{PI}(s)=K_P+\frac{K_I}{s}$$
$$G_{PR}(s)=K_P+\frac{2K_R s}{s^2+\omega_g^2}$$
where \(K_P\) is the proportional gain, \(K_I\) is the integral gain, \(K_R\) is the resonant gain, and \(\omega_g\) is the resonant frequency. The control strategy ensures stable operation, low harmonic distortion, and reactive power capability.
Gain and Loss Analysis for the Five-Level Solar Inverter
The voltage gain of the five-level common-ground solar inverter can be derived from the volt-second balance of the Boost inductor. The result is
$$G=\frac{V_g}{V_{Cin}}=\frac{1+\sqrt{1+\frac{2A_m^2 R}{L_1 f_s}}}{2}$$
This equation shows that the voltage gain increases with the modulation coefficient \(A_m\) and the load resistance \(R\). For a given load, the gain can be adjusted by \(A_m\). In my design, I keep the peak gain below six to ensure a safe margin.
The total loss includes switching loss, conduction loss, inductor core loss, and capacitor loss. The switching loss is
$$P_{sw}=f_s i_d(t)u_{ds}(t)\,dt + f_s Q_g U_{gate}$$
The conduction loss of the high-frequency switches and low-frequency switches is
$$P_{cond-S1,4-8}=\frac{2}{3\pi}I_m^2 R_{ds}$$
$$P_{cond-S2,3}=\left(\frac{1}{4}-\frac{2}{3\pi}\right)I_m^2 R_{ds}$$
The inductor conduction loss is
$$P_{C-L}=I_{s}^2 R_{L-dc}+0.5 I_{f}^2 R_{L-ac}$$
These equations help me select devices and design the thermal management of the solar inverter.
Comparison of the Proposed Five-Level Solar Inverter with Other Topologies
I compare the proposed five-level common-ground solar inverter with other multilevel topologies in Table 12. The proposed topology uses eight switches, one diode, and three capacitors. It provides voltage boost, common-mode current elimination, and reactive power capability. In contrast, NPC and cascaded H-bridge topologies require more devices or do not provide boost capability. Flying-capacitor topologies require fewer devices, but they often lack reactive power capability or voltage boost. The proposed topology achieves a good balance between device count, functionality, and performance.
| Topology | Switches | Diodes | Capacitors | DC sources | Voltage boost | Common-mode current | Reactive power |
|---|---|---|---|---|---|---|---|
| NPC | 8 | 20 | 4 | 1 | No | Low | No |
| Cascaded H-bridge | 7 | 12 | 0 | 2 | No | High | No |
| Diode-clamped five-level | 8 | 14 | 7 | 2 | Yes | High | No |
| Flying-capacitor five-level | 8 | 1 | 3 | 1 | No | Low | No |
| Previous common-ground five-level | 8 | 1 | 3 | 1 | No | None | No |
| Proposed five-level common-ground solar inverter | 8 | 1 | 3 | 1 | Yes | None | Yes |
Simulation and Experimental Results for the Five-Level Solar Inverter
I built a simulation model and a 1 kW experimental prototype. The parameters are listed in Table 13.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Input voltage | 60–100 V | Inductor \(L_1\) | 70 \(\mu H\) |
| Output voltage | 120–240 V AC | Filter inductor \(L_2\) | 2 mH |
| Switching frequency | 20 kHz | Switches | TO-220 devices |
| Line frequency | 50 Hz | Diode | Fast recovery diode |
| Capacitor \(C_1\) | 250 \(\mu F\)/450 V | Capacitor \(C_2\) | 250 \(\mu F\)/450 V |
In the simulation, the DC bus inductor current operates in discontinuous conduction mode. The capacitor voltages \(V_{C1}\) and \(V_{C2}\) are nearly equal, which confirms the self-balancing capability of the switched-capacitor network. The unfiltered output voltage has five levels and is symmetric. The output current is sinusoidal with a THD of 2.52 percent. The efficiency is above 96.1 percent over a wide output voltage range and above 96.5 percent for output power between 650 W and 1.3 kW.
In the experimental prototype, the DC-side inductor current and switch \(S_1\) driving signal show that the input current is symmetric and the switch operates in discontinuous conduction mode. The capacitor voltages \(V_{C1}\) and \(V_{C2}\) are approximately equal, and the unfiltered output voltage is a five-level staircase wave with good symmetry. The leakage current test shows that the proposed common-ground solar inverter reduces the leakage current to nearly zero. By contrast, a H5 solar inverter has a peak leakage current of about 350 mA, and a HERIC solar inverter has a peak leakage current of about 70 mA. The proposed solar inverter maintains the common-mode voltage at zero in both steady state and dynamic conditions.
I also tested the dynamic performance of the five-level solar inverter. When the input voltage steps from 60 V to 100 V and back, the output current settles quickly, and the THD remains below 2.56 percent. The solar inverter can also provide reactive power. It operates stably at power factors of -0.9 and +0.9. The measured output current THD is 1.89 percent, and the output voltage THD is 2.52 percent, both of which satisfy the IEC-61000-3-2 requirement. The maximum efficiency is 97.4 percent.
Comparative Discussion and Practical Considerations
The two proposed common-ground solar inverters address different application needs. The three-level common-ground solar inverter is suitable for low-to-medium power applications where a wide input voltage range and simple control are important. It uses fewer switches and has a straightforward modulation scheme. The five-level common-ground solar inverter is suitable for higher power applications where low harmonic distortion, high voltage gain, and reactive power capability are required. It uses more switches but produces a five-level output, which reduces filter size and improves electromagnetic compatibility.
I summarize the main performance indicators of the two proposed solar inverters in Table 14.
| Indicator | Three-level common-ground solar inverter | Five-level common-ground solar inverter |
|---|---|---|
| Output levels | 3 | 5 |
| Leakage current | Theoretically zero | Theoretically zero |
| Voltage gain | Buck-boost | Boost, up to 6 |
| Reactive power capability | Yes | Yes |
| Output current THD | 3.7% maximum | 2.52% maximum |
| Maximum efficiency | 97.9% | 97.4% |
| Main advantage | Simple structure and wide input range | Low harmonic distortion and high gain |
| Main challenge | Capacitor voltage ripple | Device count and thermal design |
From a practical point of view, I also consider component stresses, thermal management, and capacitor selection. In the three-level solar inverter, the DC bus capacitor experiences a small voltage ripple because of the soft-charging operation. However, the capacitor voltage is not perfectly constant, so long-term operation may affect device lifetime. Future work can optimize the intermediate energy transfer control to reduce the capacitor voltage ripple. In the five-level solar inverter, the number of active devices is relatively high, so device selection and heat dissipation must be carefully designed. The capacitors should be selected for high reliability, high temperature tolerance, humidity tolerance, and long lifetime.
Another important consideration is the modulation strategy. In the three-level solar inverter, the proportional-resonant controller and simple PWM modulation provide good steady-state and dynamic performance. In the five-level solar inverter, the feedforward space vector modulation decouples the output voltage from the capacitor voltage ripple. Without this feedforward strategy, the output current would be distorted by the capacitor voltage ripple. The feedforward strategy therefore plays a critical role in achieving low THD and stable operation.
I also note that the common-ground structure eliminates the leakage current path but does not eliminate the need for careful grounding and insulation design. The photovoltaic array, the solar inverter enclosure, and the grid interface must still follow safety standards. The common-ground connection must be properly implemented to avoid ground loops and electromagnetic interference. In addition, the grid current control must be designed to handle grid voltage distortion and frequency variation.
Conclusions from My Research
In my research, I studied non-isolated single-phase common-ground solar inverters for photovoltaic grid-connected systems. I first analyzed the cause of leakage current in transformerless solar inverters and established a common-mode equivalent circuit. I showed that the leakage current is proportional to the derivative of the common-mode voltage and the parasitic capacitance. I then reviewed full-bridge, half-bridge, and common-ground topologies and confirmed that common-ground structures have an inherent advantage because they clamp the common-mode voltage to zero.
I proposed a three-level common-ground solar inverter with buck-boost capability. The topology uses a switching-boost-buck module to handle wide input voltage variations and to perform maximum power point tracking. It has a soft-charging capability, good symmetry, and simple control. Simulation and experimental results showed that the solar inverter eliminates common-mode leakage current, provides buck-boost operation, and supports reactive power. The maximum efficiency was 97.9 percent, and the maximum output current THD was 3.7 percent.
I also proposed a five-level common-ground solar inverter with a switched-capacitor network. The topology uses two capacitors in a series-parallel network to produce five output levels. It provides high voltage gain, low harmonic distortion, and reactive power capability. I developed a feedforward space vector modulation strategy to decouple the output voltage from the capacitor voltage ripple. Simulation and experimental results showed that the solar inverter has self-balancing capacitor voltages, a maximum voltage gain of six, and a maximum output current THD of 2.52 percent. The maximum efficiency was 97.4 percent. The common-ground structure reduced the leakage current to nearly zero, and the solar inverter operated stably at power factors of ±0.9.
Overall, my work shows that common-ground solar inverter topologies can simultaneously solve the leakage current problem and provide flexible voltage conversion and high power quality. The three-level topology is suitable for simple, low-to-medium power applications with wide input voltage range. The five-level topology is suitable for higher power applications that require low harmonic distortion and reactive power support. Both topologies contribute to safer, more efficient, and more compact photovoltaic grid-connected systems. In future work, I plan to optimize the capacitor voltage ripple, improve thermal design, and investigate advanced control methods for wider grid compatibility and higher reliability.