In the realm of renewable energy systems, solar inverters play a pivotal role in converting DC power from photovoltaic panels into AC power for grid integration. As solar power plants scale up to megawatt levels, the demand for efficient, high-power inverters has intensified. Among various topologies, the three-level neutral-point-clamped (NPC) inverter has emerged as a preferred choice for medium-voltage, high-power applications due to its reduced voltage stress on switches, lower total harmonic distortion (THD), and improved output waveform quality. However, a persistent challenge in three-level NPC solar inverters is the imbalance in the neutral-point potential, which can degrade performance and reliability if left unaddressed.
To enhance efficiency, discontinuous pulse-width modulation (DPWM) strategies are often employed in solar inverters, as they reduce switching losses by one-third compared to continuous PWM (CPWM) methods. This reduction allows for higher effective switching frequencies or lower losses, making DPWM particularly attractive for high-power solar inverter systems. Nonetheless, traditional neutral-point balancing techniques, when applied to DPWM-based inverters, disrupt the clamping characteristics that define DPWM’s low-loss advantage. This article presents a novel balancing method tailored for three-level DPWM solar inverters, ensuring neutral-point stability while preserving the benefits of DPWM.
The core of the issue lies in the inherent behavior of the three-level NPC solar inverter. The DC-link is split into two capacitors, creating a neutral point that can fluctuate due to the switching states. In DPWM, each phase leg is clamped to either the positive or negative DC bus for a portion of the fundamental cycle, minimizing switch transitions. However, this clamping action inherently affects the neutral-point current, leading to potential imbalances. Over time, these imbalances can cause DC offsets and low-frequency oscillations in the neutral-point voltage, jeopardizing the solar inverter’s output quality and component lifespan.
Let us delve into the mathematical representation of the three-level NPC solar inverter. The output phase voltages can assume three levels: $+U_{dc}/2$, $0$, and $-U_{dc}/2$, corresponding to switching states denoted as $1$, $0$, and $-1$, respectively. For a three-phase system, the space vector diagram comprises 27 vectors, categorized into zero vectors, small vectors, medium vectors, and large vectors. The neutral-point current $i_o$ is influenced by these vectors, as summarized in Table 1.
| Vector Type | Magnitude | Example Switching States | Neutral-Point Current $i_o$ |
|---|---|---|---|
| Zero Vector | 0 | [000], [111], [-1-1-1] | 0 |
| Small Vector (Positive) | $U_{dc}/3$ | [100] | $-i_a$ |
| Small Vector (Negative) | $U_{dc}/3$ | [0-1-1] | $i_a$ |
| Medium Vector | $\sqrt{3}U_{dc}/3$ | [10-1] | $i_b$ |
| Large Vector | $2U_{dc}/3$ | [1-1-1] | 0 |
From Table 1, it is evident that positive small vectors cause current to flow into the neutral point, raising its potential $v_o$, while negative small vectors draw current out, lowering $v_o$. Medium vectors can either raise or lower $v_o$ depending on the phase currents, and large vectors have no effect. In a solar inverter operating at unity power factor, the phase currents are sinusoidal and in phase with the grid voltage. For DPWM strategies like DPWMA, only one of the redundant small vector pairs is used per switching cycle, leading to an inherent asymmetry in neutral-point current over a fundamental period.
The neutral-point potential $v_o$ is defined as the difference between the voltages of the lower and upper DC-link capacitors:
$$ v_o = U_{dc2} – U_{dc1} $$
where $U_{dc1}$ and $U_{dc2}$ are the voltages across the upper and lower capacitors, respectively. Under DPWM, $v_o$ exhibits a triple-frequency oscillation superimposed on a possible DC offset. The DC offset arises if the average neutral-point current over a fundamental cycle is non-zero, which can occur due to asymmetries in the DPWM clamping pattern. This is critical for solar inverters, as sustained offsets can overstress capacitors and distort output currents.
Traditional neutral-point balancing methods, such as zero-sequence voltage injection in CPWM solar inverters, adjust the duty cycles of positive and negative small vectors within each switching cycle. However, in DPWM solar inverters, this approach disrupts the clamping intervals, effectively converting DPWM into CPWM and nullifying its low-loss benefits. Consider the DPWMA strategy, where the modulation waves are modified by adding a zero-sequence component $V_z$ to the original phase modulation signals $u_a$, $u_b$, and $u_c$:
$$ u’_a = u_a + V_z $$
$$ u’_b = u_b + V_z $$
$$ u’_c = u_c + V_z $$
In CPWM, $V_z$ is calculated to balance the neutral-point current by redistributing the small vector times. But in DPWM, injecting such a $V_z$ can force a phase leg out of its clamped state, increasing switching actions. For instance, if a phase is clamped to zero in DPWMA, injecting a negative $V_z$ might require it to switch to negative states, breaking the clamping sequence. Thus, a dedicated method for DPWM solar inverters is essential.
We propose a clamping-based neutral-point balancing technique that leverages the DPWM structure without adding extra switch transitions. The principle is straightforward: when the neutral-point potential $v_o$ exceeds a positive threshold $\Delta$, we clamp the phase leg closest to the negative DC level to that level, effectively increasing the action time of negative small vectors. Conversely, when $v_o$ falls below a negative threshold $-\Delta$, we clamp the phase leg closest to the positive DC level to that level, enhancing positive small vector action. This is achieved by computing an appropriate zero-sequence voltage $V_z$ that modifies the modulation waves only during imbalance conditions.
The algorithm operates as follows. First, measure $v_o$ using voltage sensors across the DC-link capacitors. Then, compare $v_o$ with the thresholds $\pm \Delta$. If $v_o > \Delta$, calculate $V_z$ as:
$$ V_z = -1 – \min(u_a, u_b, u_c) $$
This ensures that the phase with the minimum modulation wave is clamped to $-1$. If $v_o < -\Delta$, compute:
$$ V_z = 1 – \max(u_a, u_b, u_c) $$
which clamps the phase with the maximum modulation wave to $+1$. For $-\Delta \leq v_o \leq \Delta$, use the standard DPWMA zero-sequence injection to maintain normal clamping. The modified modulation waves $u’_x$ are then compared with a triangular carrier to generate gate signals for the solar inverter’s switches.
To illustrate, consider a solar inverter operating in sector I of the space vector diagram. The DPWMA pattern clamps phase B to zero for part of the cycle. If $v_o$ becomes too high, the algorithm identifies phase C as closest to the negative level and injects $V_z$ to clamp it to $-1$. The switching sequence changes from [10-1][100][000][100][10-1] to [1-1-1][10-1][00-1][10-1][1-1-1], increasing the dwell time of the negative small vector [00-1] and reducing $v_o$ without additional switching.
The effectiveness of this method hinges on proper selection of $\Delta$. A small $\Delta$ minimizes neutral-point ripple but may lead to frequent clamping interventions, potentially increasing common-mode voltage in the solar inverter. A larger $\Delta$ reduces interventions but allows more ripple. In practice, $\Delta$ is set to limit the peak-to-peak ripple to within 5% of the DC-link voltage, which is acceptable for most solar inverter applications.
We validated the proposed method through extensive simulations and hardware-in-the-loop (HIL) experiments. The solar inverter parameters are listed in Table 2, reflecting a typical medium-power setup.
| Parameter | Value |
|---|---|
| Grid Frequency | 50 Hz |
| DC-Link Voltage $U_{dc}$ | 572 V |
| DC-Link Capacitors $C_1$, $C_2$ | 24,000 μF each |
| Switching Frequency (Carrier) | 8 kHz |
| Output LCL Filter Capacitor $C_3$ | 120 μF |
| Output LCL Filter Inductors $L_1$, $L_2$ | 270 μH, 40 μH |
In simulation, we modeled the solar inverter in Simulink under two scenarios: without neutral-point control and with the proposed clamping method. Without control, $v_o$ showed a DC offset of about 40 V and a triple-frequency oscillation with significant amplitude. Applying traditional CPWM-based balancing disrupted the DPWM clamping, increasing switch transitions and harmonic distortion. With our method, $v_o$ stabilized within 0.07 seconds, and the DC offset was eliminated while maintaining low switching loss.
For HIL testing, we used a Quanser Q8 board to emulate the solar inverter plant and a DSP controller (TMS320F28335) to implement the DPWM and balancing algorithm. The results confirmed that the proposed method effectively removes DC bias and confines the neutral-point ripple to a manageable range. Figure 15 from the experiments shows that prior to balancing, $v_o$ had a peak-to-peak variation of up to 32 V; after enabling the algorithm with $\Delta = 8$ V, the ripple reduced to approximately 16 V with no offset.
The mathematical underpinnings of this approach can be further analyzed through neutral-point current modeling. The average neutral-point current over a switching period in a DPWM solar inverter depends on the phase currents and the duty cycles of small vectors. Let $d_p$ and $d_n$ denote the duty cycles of positive and negative small vectors, respectively. In DPWMA, only one type is active per cycle. For sector I, when phase B is clamped, $d_n$ is zero. The neutral-point current integral over a cycle is:
$$ \int_0^{T_s} i_o \, dt = -i_a \cdot d_p \cdot T_s $$
where $T_s$ is the switching period. Over a fundamental cycle, the net charge accumulation leads to $v_o$ drift. Our method adjusts $d_p$ and $d_n$ by clamping actions, effectively injecting a corrective charge. The required $V_z$ can be derived from the modulation wave geometry. For instance, to clamp phase C to $-1$, we set $u’_c = -1$, so from $u’_c = u_c + V_z$, we get $V_z = -1 – u_c$. Since $u_c$ is the minimum in that interval, this aligns with the formula above.
A key advantage of this method is its simplicity. Unlike complex predictive controls or virtual vector methods that require per-cycle computations, our algorithm only intervenes when $v_o$ exceeds thresholds, reducing computational load on the solar inverter’s controller. Moreover, it seamlessly integrates with existing DPWM frameworks, making it suitable for retrofitting older solar inverter designs.
In terms of performance metrics, the proposed balancing technique maintains the THD of the solar inverter’s output current below 3%, meeting grid standards. The switching loss reduction compared to CPWM is preserved, as evidenced by thermal simulations showing a 30% decrease in inverter module temperatures. This efficiency gain is crucial for solar inverters in hot climates, where cooling costs can be substantial.
We also explored the method’s robustness against parameter variations in solar inverters, such as capacitor tolerance and grid impedance changes. Through Monte Carlo simulations, we found that the balancing algorithm remains effective even with ±20% variations in DC-link capacitance, ensuring reliable operation in real-world solar installations.
Future work could extend this approach to other DPWM variants like DPWMB or DPWMC, which have different clamping patterns. Additionally, integrating the balancing algorithm with maximum power point tracking (MPPT) in solar inverters could optimize overall system efficiency. Another direction is to combine it with active filtering techniques to further suppress harmonics.
In conclusion, the clamping-based neutral-point balancing method offers a practical solution for three-level DPWM solar inverters. It addresses the inherent imbalance issue without compromising the low-switching-loss benefit of DPWM, ensuring stable and efficient operation. As solar power continues to grow, such innovations will be vital for advancing solar inverter technology and enabling higher penetration of renewable energy into the grid.