In recent years, the increasing severity of energy crises and growing environmental awareness have driven the rapid development of renewable energy sources and distributed generation (DG) technologies. As the interface between renewable generation systems and the utility grid, the solar inverter plays a critical role in ensuring stable, efficient, and reliable power conversion. Traditional solar inverter control strategies are generally designed under the assumption of a balanced three-phase grid. However, in practical power systems, grid faults, large-scale unbalanced loads, and various disturbances frequently lead to voltage asymmetry at the point of common coupling. Under such asymmetric grid conditions, the negative-sequence voltage component can cause severe problems, including power oscillations, DC-link voltage ripple, overcurrent, and degraded power quality. Therefore, it is of great significance to investigate advanced control strategies for solar inverters under asymmetric grid faults, with the specific aim of suppressing negative-sequence voltage effects and improving fault ride-through capability.
This article presents a comprehensive design, analysis, and experimental evaluation of control strategies for solar inverters operating under asymmetric grid faults. The focus is placed on two distinct control frameworks: one based on the synchronous reference frame and the other based on the stationary reference frame. The three fundamental building blocks of the control system—grid synchronization, power control, and current regulation—are thoroughly examined and compared for both frameworks. The implementation details, working principles, and performance characteristics of each strategy are described with the support of mathematical derivations, simulation studies, and experimental validation on a laboratory prototype based on the TMS320F28335 digital signal processor. The findings demonstrate that the stationary-frame control strategy not only offers superior dynamic performance and steady-state accuracy but also simplifies the overall control structure compared to its synchronous-frame counterpart.
1. Introduction
Solar photovoltaic (PV) generation has become one of the most prominent renewable energy technologies due to its scalability, environmental compatibility, and decreasing system costs. Solar inverters, as the power electronic interfaces between PV arrays and the grid, must handle a wide range of operating scenarios. Among these, unbalanced grid faults such as single-phase-to-ground, two-phase-to-ground, and two-phase voltage sags are common events that significantly affect inverter performance. During such faults, the grid voltage contains both positive- and negative-sequence components. If the inverter control system only acts on the positive-sequence component, the negative-sequence voltage induces second-harmonic ripple in the DC-link voltage and negative-sequence currents in the AC output, which may trip the inverter protection or damage the semiconductor devices.
To overcome these issues, researchers have proposed various advanced control methods. Early approaches relied on notch filters or band-pass filters to extract the positive-sequence component before applying conventional synchronous-frame proportional-integral (PI) controllers. However, such filters introduce substantial phase lag and reduce system bandwidth. Later, the decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL) was introduced to simultaneously detect and decouple the positive- and negative-sequence components in a rotating frame. This method enables accurate grid synchronization even under highly unbalanced conditions. Alternatively, the dual second-order generalized integrator frequency-locked loop (DSOGI-FLL) operates in the stationary frame, directly estimating the grid frequency using an orthogonal signal generator, which avoids the need for complex coordinate transformations.
In addition to grid synchronization, power control under unbalanced conditions is a key issue. The instantaneous active and reactive power injected by the inverter contain oscillatory terms caused by the interaction between voltage and current sequences. The power synchronization control (PSC) and the positive/negative-sequence control (PNSC) strategies have been developed to regulate the average power and to minimize oscillations. The choice of current controller also plays a decisive role. In the synchronous frame, dual PI controllers operating in the positive and negative dq frames require the decomposition of the measured currents and separate control loops, as well as cross-coupling compensation. In contrast, proportional-resonant (PR) controllers in the stationary frame can directly track sinusoidal references without sequence decomposition, thereby simplifying the control architecture and improving robustness to frequency variations.
This work systematically addresses the design and comparative evaluation of two complete control systems for solar inverters under asymmetric grid faults. The main contributions are as follows:
- A detailed comparison of the DDSRF-PLL and DSOGI-FLL synchronization techniques, including their dynamic response and frequency detection accuracy under unbalanced voltage sags.
- A derivation of the instantaneous power equations under unbalanced conditions, highlighting the influence of negative-sequence components and presenting the PNSC-based reference current generation.
- A design and performance analysis of dual PI current controllers in the synchronous frame versus dual PR current controllers in the stationary frame, including their frequency-domain characteristics and tracking errors.
- Comprehensive simulation and experimental results obtained from a custom-built solar inverter prototype, which validate the superiority of the stationary-frame control strategy.
2. System Architecture and Control Framework
The overall control system of the solar inverter under investigation is illustrated conceptually in Figure 1 (not shown for brevity). The system comprises a DC voltage source, a three-phase voltage source inverter (VSI), an LC filter, and the utility grid. The control structure consists of three main modules: grid synchronization, power control, and current control. The grid synchronization module provides the phase angle and frequency of the grid voltage. The power controller generates the reference currents based on the desired active and reactive power setpoints. The current controller regulates the actual grid currents to follow the references and produces the PWM switching signals.
Two different implementations of this control system are studied. The first implementation is based on the synchronous reference frame (SRF). In this scheme, the grid voltages and currents are transformed into the positive and negative dq frames. The DDSRF-PLL is used for grid synchronization, dual PI controllers are employed for current regulation, and the reference currents are calculated using the PNSC method. The second implementation is based on the stationary reference frame (αβ). Here, the DSOGI-FLL provides the grid frequency and orthogonal components, and dual PR controllers directly regulate the αβ currents.
The key parameters of the system are summarized in Table 1.
| Parameter | Symbol | Value |
|---|---|---|
| Grid input voltage (RMS, line-to-neutral) | \(U_g\) | 57.4 V |
| Grid frequency | \(f_g\) | 50 Hz |
| Grid-side filter inductance | \(L_f\) | 7 mH |
| DC-link voltage reference | \(U_{dc}^*\) | 150 V |
| DC-link capacitance | \(C_{dc}\) | 1980 μF |
| DC resistive load | \(R_{load}\) | 60 Ω |
| Switching frequency | \(f_{sw}\) | 10 kHz |
3. Grid Synchronization Techniques
3.1 Decoupled Double Synchronous Reference Frame PLL
The DDSRF-PLL is designed to handle unbalanced grid voltages by separating the positive- and negative-sequence components. In the stationary frame, the grid voltage vector \(\boldsymbol{U}\) can be expressed as:
\[
\boldsymbol{U} = \boldsymbol{U}^{+} + \boldsymbol{U}^{-} = U^{+} e^{j(\omega t + \phi^{+})} + U^{-} e^{-j(\omega t + \phi^{-})}
\]
where \(U^{+}\) and \(U^{-}\) are the amplitudes of the positive- and negative-sequence voltages, \(\omega\) is the grid angular frequency, and \(\phi^{+}\) and \(\phi^{-}\) are the corresponding initial phase angles.
The DDSRF-PLL rotates both sequence components into their own synchronous frames, yielding two sets of dq quantities. However, due to the rotation, the negative-sequence component appears as a second-harmonic disturbance in the positive dq frame and vice versa. Therefore, a decoupling network is required to remove these cross-couplings. The decoupling equations for the positive dq frame are:
\[
\begin{aligned}
U_{d}^{+} &= \tilde{U}_{d}^{+} – \cos(2\omega t) \tilde{U}_{d}^{-} – \sin(2\omega t) \tilde{U}_{q}^{-} \\
U_{q}^{+} &= \tilde{U}_{q}^{+} + \sin(2\omega t) \tilde{U}_{d}^{-} – \cos(2\omega t) \tilde{U}_{q}^{-}
\end{aligned}
\]
where \(\tilde{U}_{d}^{+}, \tilde{U}_{q}^{+}\) are the directly measured dq components in the positive frame, and \(\tilde{U}_{d}^{-}, \tilde{U}_{q}^{-}\) are those in the negative frame. After the decoupling network, a low-pass filter (LPF) removes any residual high-frequency content, and a standard SRF-PLL locks onto the positive-sequence phase angle.
The transfer function of the LPF used in the DDSRF-PLL is defined as:
\[
H_{LPF}(s) = \frac{\omega_{LPF}}{s + \omega_{LPF}}
\]
where \(\omega_{LPF}\) is the cutoff frequency. The design of the loop filter (PI) determines the bandwidth and settling time of the PLL. The PI controller gains \(k_p\) and \(k_i\) for the SRF-PLL are tuned to obtain a phase margin around 45° and a bandwidth of approximately 30 Hz. The resulting dynamic performance is acceptable for balanced conditions, but under asymmetric faults the second-harmonic rejection depends heavily on the decoupling network and the LPF characteristics. Furthermore, the phase-angle output can still contain some ripple if the decoupling is imperfect.
3.2 Dual Second-Order Generalized Integrator FLL
The DSOGI-FLL operates exclusively in the stationary frame and avoids any phase-angle feedback loop. Instead, it directly estimates the grid frequency using a frequency-locked loop. The core of this method is the second-order generalized integrator (SOGI), which generates two quadrature signals from a single input voltage. For a given input \(v\), the SOGI produces the in-phase output \(v’\) and the orthogonal output \(q v’\), with the following transfer functions:
\[
\frac{v’}{v}(s) = \frac{k \omega_0 s}{s^2 + k \omega_0 s + \omega_0^2}
\]
\[
\frac{qv’}{v}(s) = \frac{k \omega_0^2}{s^2 + k \omega_0 s + \omega_0^2}
\]
where \(k\) is the damping factor, typically set to \(\sqrt{2}\), and \(\omega_0\) is the resonant frequency. In the DSOGI-FLL, two SOGI blocks are used for the α and β voltage components, which are obtained via Clarke’s transformation of the three-phase grid voltages. The FLL adjusts the resonant frequency \(\omega_0\) based on the error signal produced by the quadrature outputs. The frequency adaptation law is given by:
\[
\frac{d\omega_0}{dt} = -\gamma \left[ (v_{\alpha} – v’_{\alpha}) qv’_{\alpha} + (v_{\beta} – v’_{\beta}) qv’_{\beta} \right]
\]
where \(\gamma\) is the FLL gain. This formulation provides a direct measure of the grid frequency without any phase-angle locking. The DSOGI-FLL has several advantages: it does not require a coordinate transformation, it does not contain a PI regulator, and it offers a faster and smoother frequency tracking response during unbalanced faults. Moreover, the orthogonal components generated by the SOGI can be directly used for instantaneous power calculations and for the PR current controllers.
Table 2 compares the structural and performance characteristics of the two synchronization methods.
| Feature | DDSRF-PLL | DSOGI-FLL |
|---|---|---|
| Coordinate frame | Synchronous (dq) | Stationary (αβ) |
| Controlled variable | Phase angle | Frequency |
| Decoupling network | Required | Not required |
| Regulator type | PI | Integral (FLL gain) |
| Frequency ripple under fault | Moderate | Low |
| Dynamic response speed | Relatively slow | Fast |
| Structural complexity | High | Low |
4. Power Control Under Asymmetric Faults
When the grid voltage is unbalanced, the instantaneous active power \(p(t)\) and reactive power \(q(t)\) can be expressed in terms of the positive- and negative-sequence components of voltage and current. In the stationary frame, the voltage and current vectors can be decomposed as:
\[
\boldsymbol{U} = \boldsymbol{U}^{+} + \boldsymbol{U}^{-}, \quad \boldsymbol{I} = \boldsymbol{I}^{+} + \boldsymbol{I}^{-}
\]
where \(\boldsymbol{U}^{+}, \boldsymbol{U}^{-}, \boldsymbol{I}^{+}, \boldsymbol{I}^{-}\) are complex phasors. The instantaneous power is:
\[
p(t) = P_0 + P_{c2} \cos(2\omega t) + P_{s2} \sin(2\omega t)
\]
\[
q(t) = Q_0 + Q_{c2} \cos(2\omega t) + Q_{s2} \sin(2\omega t)
\]
Here, \(P_0\) and \(Q_0\) are the average active and reactive powers, while \(P_{c2}, P_{s2}, Q_{c2}, Q_{s2}\) are the amplitudes of the double-frequency oscillations. Expressions for these coefficients, based on sequence components, are:
\[
P_0 = \frac{3}{2} \left( U_d^{+} I_d^{+} + U_q^{+} I_q^{+} + U_d^{-} I_d^{-} + U_q^{-} I_q^{-} \right)
\]
\[
P_{c2} = \frac{3}{2} \left( U_d^{+} I_d^{-} + U_q^{+} I_q^{-} + U_d^{-} I_d^{+} + U_q^{-} I_q^{+} \right)
\]
\[
P_{s2} = \frac{3}{2} \left( U_q^{+} I_d^{-} – U_d^{+} I_q^{-} – U_q^{-} I_d^{+} + U_d^{-} I_q^{+} \right)
\]
To attenuate the oscillatory power components, one can adopt the positive and negative sequence control (PNSC) strategy. The core idea of PNSC is to design the reference currents such that the undesirable oscillatory terms are cancelled. For example, if the goal is to suppress the active power oscillation, the reference currents must satisfy specific constraints. Assuming that the reactive power reference is set to zero and the average active power is regulated by the DC-link voltage controller, the reference currents in the positive and negative dq frames can be calculated as follows:
\[
\begin{bmatrix} I_d^{+*} \\ I_q^{+*} \\ I_d^{-*} \\ I_q^{-*} \end{bmatrix}
= \frac{2}{3} \frac{P_0}{(U_d^{+})^2 + (U_q^{+})^2 – (U_d^{-})^2 – (U_q^{-})^2}
\begin{bmatrix}
U_d^{+} – U_d^{-} \\
U_q^{+} – U_q^{-} \\
-(U_d^{+} – U_d^{-}) \\
-(U_q^{+} – U_q^{-})
\end{bmatrix}
\]
This formulation ensures that the power oscillatory coefficients are zero while the average power remains equal to \(P_0\). In the stationary frame, the reference currents can be obtained directly using the orthogonal components of the voltage. Let \(u_{\alpha}^{+}, u_{\beta}^{+}\) and \(u_{\alpha}^{-}, u_{\beta}^{-}\) denote the positive- and negative-sequence components in the αβ frame. Then the PNSC reference currents are:
\[
i_{\alpha}^{*} = P_0 \frac{u_{\alpha}^{+} – u_{\alpha}^{-}}{(u_{\alpha}^{+})^2 + (u_{\beta}^{+})^2 – (u_{\alpha}^{-})^2 – (u_{\beta}^{-})^2}
\]
\[
i_{\beta}^{*} = P_0 \frac{u_{\beta}^{+} – u_{\beta}^{-}}{(u_{\alpha}^{+})^2 + (u_{\beta}^{+})^2 – (u_{\alpha}^{-})^2 – (u_{\beta}^{-})^2}
\]
This stationary-frame formulation avoids repeated coordinate transformations and is therefore more computationally efficient. It also works naturally with the DSOGI-FLL because the positive- and negative-sequence voltage components are readily available from the SOGI outputs.
5. Current Control Strategies
5.1 Synchronous-Frame Dual PI Control
In the synchronous-frame implementation, the measured grid currents are first decomposed into positive- and negative-sequence components. Each sequence frame has its own PI controller. The typical control block diagram contains two parallel PI regulators: one acting on the positive dq currents and another acting on the negative dq currents. The control equation for the positive sequence, including the cross-coupling and feedforward terms, is:
\[
U_{d}^{+*} = \left(k_{p} + \frac{k_{i}}{s}\right) \left(I_{d}^{+*} – I_{d}^{+}\right) – \omega L_f I_{q}^{+} + U_{d}^{+}
\]
\[
U_{q}^{+*} = \left(k_{p} + \frac{k_{i}}{s}\right) \left(I_{q}^{+*} – I_{q}^{+}\right) + \omega L_f I_{d}^{+} + U_{q}^{+}
\]
Similarly, the negative-sequence controller outputs are:
\[
U_{d}^{-*} = \left(k_{p} + \frac{k_{i}}{s}\right) \left(I_{d}^{-*} – I_{d}^{-}\right) + \omega L_f I_{q}^{-} + U_{d}^{-}
\]
\[
U_{q}^{-*} = \left(k_{p} + \frac{k_{i}}{s}\right) \left(I_{q}^{-*} – I_{q}^{-}\right) – \omega L_f I_{d}^{-} + U_{q}^{-}
\]
The output voltages in the dq frames are then transformed back to the abc frame via inverse Park transformations. Despite its effectiveness, this method entails significant complexity: it requires separate measurements, sequence decomposition, four PI controllers, and a large number of coordinate transformations. In addition, the dual PI controllers are sensitive to phase errors introduced by the PLL, and any delay in the decoupling path may degrade the transient response.
5.2 Stationary-Frame Dual PR Control
In contrast, the stationary-frame implementation uses PR controllers that directly regulate the αβ currents. The transfer function of an ideal PR controller is:
\[
G_{PR}(s) = k_p + \frac{2 k_r \omega_0 s}{s^2 + 2 \omega_0 s + \omega_0^2}
\]
where \(k_p\) is the proportional gain, \(k_r\) is the resonant gain, and \(\omega_0\) is the resonant frequency (set to the grid frequency). The non-ideal PR controller is more commonly used because it provides a finite gain at the resonant frequency, which eases the implementation and enhances robustness against frequency variations. Its transfer function is:
\[
G_{PR}(s) = k_p + \frac{2 k_r \omega_c s}{s^2 + 2 \omega_c s + \omega_0^2}
\]
where \(\omega_c\) is the bandwidth around the resonant frequency. In this study, the dual PR controllers are designed with \(\omega_0 = 2\pi \times 50 \, \text{rad/s}\), \(k_p = 200\), \(k_r = 30\), and \(\omega_c = 2\pi \times 5 \, \text{rad/s}\). The controller outputs are directly applied to the reference voltages for the PWM modulator:
\[
u_{\alpha}^{*} = G_{PR}(s) \left(i_{\alpha}^{*} – i_{\alpha}\right) + u_{\alpha}
\]
\[
u_{\beta}^{*} = G_{PR}(s) \left(i_{\beta}^{*} – i_{\beta}\right) + u_{\beta}
\]
Here, \(u_{\alpha}, u_{\beta}\) are the grid voltage feedforward terms. Since the PR controller provides an infinite (or very high) gain at \(\omega_0\), it can track sinusoidal references with zero steady-state error. No additional coordinate transformations are required, and the structure is greatly simplified.
Table 3 lists the parameters of the current controllers used in the comparative study.
| Controller type | Parameter | Symbol | Value |
|---|---|---|---|
| PI (synchronous) | Proportional gain | \(k_p^{PI}\) | 150 |
| Integral gain | \(k_i^{PI}\) | 20 | |
| PR (stationary) | Proportional gain | \(k_p^{PR}\) | 200 |
| Resonant gain | \(k_r^{PR}\) | 30 |
6. Simulation Studies
To validate the theoretical analysis, a detailed simulation model of the solar inverter was built in MATLAB/Simulink using the SimPowerSystems toolbox. The system parameters are given in Table 1. The control parameters are listed in Table 4. Two different control strategies were implemented: (i) the synchronous-frame strategy comprising DDSRF-PLL, PNSC power control, and dual PI current controllers; and (ii) the stationary-frame strategy comprising DSOGI-FLL, PNSC power control, and dual PR current controllers. The same PNSC algorithm was employed in both strategies to ensure a fair comparison of the synchronization and current control blocks.
| Control block | Parameter | Symbol | Value |
|---|---|---|---|
| DDSRF-PLL | Proportional gain | \(k_p^{PLL}\) | 0.7 |
| Integral gain | \(k_i^{PLL}\) | 30 | |
| DSOGI damping | SOGI gain | \(k\) | 1.41 |
| FLL gain | Frequency adaptation | \(\gamma\) | 100 |
In the simulation, a two-phase voltage sag was applied at \(t = 2 \, \text{s}\). The grid voltages dropped to 60% of their nominal amplitude in phases A and B, while phase C remained unchanged. This creates a significant negative-sequence voltage component.
6.1 Synchronization Performance
The simulation results clearly indicate differences between the two synchronization methods. With the DDSRF-PLL, the estimated frequency fluctuated with a peak-to-peak deviation of approximately 2.5 Hz around the nominal 50 Hz during the fault, and the settling time was about 30 ms. The phase-angle output also contained noticeable second-harmonic ripple. In contrast, the DSOGI-FLL exhibited a frequency deviation of only 0.8 Hz and settled within 10 ms. The smoother frequency estimation is attributed to the absence of a phase-locked loop and the direct frequency adaptation mechanism. Such a precise frequency estimate is particularly beneficial for the PR current controllers, which rely on the resonant frequency for zero steady-state error tracking.
6.2 Current Control Performance
Both current control strategies successfully regulated the grid currents during the fault. However, the stationary-frame PR controllers outperformed the synchronous-frame PI controllers in several aspects. The total harmonic distortion (THD) of the grid currents was measured at 3.2% with the PR controller, whereas the PI controller produced a THD of 5.6%. The DC-link voltage ripple was also reduced in the PR-based system: the peak-to-peak ripple was approximately 4 V compared to 7 V with the PI-based system. These improvements stem from the fact that the PR controller directly tracks the AC reference without the need for coordinate transformations or phase-angle locking. The simulation waveforms demonstrate that the stationary-frame strategy achieves not only better steady-state performance but also faster dynamic response during the fault application and recovery.
Table 5 summarizes the comparative simulation results under the two-phase voltage sag condition.
| Performance metric | Synchronous-frame (DDSRF-PLL + PI) | Stationary-frame (DSOGI-FLL + PR) |
|---|---|---|
| Frequency settling time | ~30 ms | ~10 ms |
| Frequency peak deviation | 2.5 Hz | 0.8 Hz |
| Current THD | 5.6% | 3.2% |
| DC-link ripple (peak-to-peak) | 7 V | 4 V |
| Structure complexity | High | Low |
7. Experimental Verification
To further validate the simulation findings, an experimental prototype was constructed based on a TMS320F28335 DSP. The solar inverter was connected to an asymmetric grid fault emulator, which consisted of a voltage-source inverter controlled by a dSPACE 1104 system. The emulator was programmed to generate the same two-phase voltage sag condition as in the simulation. All control algorithms—including the DC-link voltage outer loop, the current inner loop (PI or PR), and the grid synchronization (DDSRF-PLL or DSOGI-FLL)—were implemented in real time in the DSP. The PWM carrier frequency was 10 kHz, and the SPWM (sinusoidal pulse width modulation) strategy was adopted.
7.1 Frequency Tracking Results
Figure 7 (omitted here) displays the experimental frequency and phase outputs for both synchronization schemes. When the two-phase voltage sag occurs, the DDSRF-PLL output frequency exhibits a transient fluctuation ranging from 46.25 Hz to 52.5 Hz, with a settling time of approximately 20 ms. Moreover, a persistent small ripple remains on the frequency output, indicating imperfect rejection of the negative-sequence component. In contrast, the DSOGI-FLL output frequency varies between 48.75 Hz and 50 Hz, and the settling time is only about 10 ms. The DSOGI-FLL output is also visibly smoother. These results confirm the simulation observations and demonstrate the superiority of the DSOGI-FLL for grid synchronization under asymmetrical faults.
7.2 Current Control Results
The experimental grid current waveforms for both controllers are shown in Figure 7 (not referenced in detail). The stationary-frame PR controller produced nearly sinusoidal currents with a THD below 4%, whereas the synchronous-frame PI controller introduced noticeable distortion and amplitude imbalance. The DC-link voltage ripple was also larger with the PI controller. The experimental results therefore support the conclusion that the stationary-frame control strategy, combining the DSOGI-FLL and PR controllers, provides better suppression of negative-sequence effects than the synchronous-frame strategy.
Table 6 compares the measured experimental results for the two control strategies under the same fault condition.
| Metric | DDSRF-PLL + PI | DSOGI-FLL + PR |
|---|---|---|
| Frequency fluctuation range | 46.25–52.5 Hz | 48.75–50 Hz |
| Frequency settling time | ~20 ms | ~10 ms |
| Steady-state frequency ripple | Present | Negligible |
| Current waveform quality | Moderate THD | Low THD |
| DC-link ripple | Higher | Lower |
8. Discussion
The comparative analysis reveals a clear trade-off between structural complexity and control performance. The synchronous-frame control strategy is mature and widely adopted in industry, but it suffers from several drawbacks when applied to asymmetric grid faults. First, the DDSRF-PLL contains a PI controller and a decoupling network that introduce additional dynamics and phase delays, making the frequency and phase estimates less accurate during transients. Second, the dual PI current controllers require the instantaneous decomposition of currents into positive and negative sequences, which is typically realized through additional filtering or decoupling networks. These operations increase the computational burden and can degrade the dynamic response. Third, the coordinate transformations and cross-coupling terms between the d and q axes make the tuning of multiple controllers a nontrivial task.
On the other hand, the stationary-frame control strategy offers a more elegant solution. The DSOGI-FLL directly estimates the grid frequency without the intermediate phase-angle loop, thereby achieving faster and smoother frequency tracking. The PR controllers naturally provide resonant peaks at the fundamental frequency, which means that no sequence decomposition is needed. The entire control system is built in the αβ frame, eliminating the need for Park and inverse Park transformations. The simulation and experimental results consistently confirm that the stationary-frame strategy achieves lower current THD, reduced DC-link voltage ripple, and faster synchronization dynamics.
The suppression of the negative-sequence voltage is inherently achieved through the combined action of the synchronization and current control loops. While the DSOGI-FLL is not specifically designed to extract sequence components, the SOGI structure generates both the in-phase and orthogonal components, which contain both sequence information. When used together with the PNSC power control, the reference currents are generated in a way that cancels the power oscillations caused by the negative-sequence voltage. The PR controllers then track these references with zero steady-state error at the tuned resonant frequency. The experimental outcomes demonstrate that the negative-sequence voltage effects are effectively mitigated, resulting in balanced and sinusoidal grid currents.
9. Conclusion
This article has presented a detailed investigation into the negative-sequence voltage suppression of solar inverters under asymmetric grid faults. Two complete control systems were designed, implemented, and compared: one based on the synchronous reference frame with DDSRF-PLL and dual PI controllers, and the other based on the stationary reference frame with DSOGI-FLL and dual PR controllers. The three major building blocks—grid synchronization, power control, and current regulation—were individually analyzed and evaluated. Through extensive simulation and experimental validations on a TMS320F28335-based prototype, the following conclusions can be drawn:
- The DSOGI-FLL provides faster and more accurate frequency estimation than the DDSRF-PLL during unbalanced voltage sags, with lower frequency ripple and shorter settling time.
- The stationary-frame PR controllers yield lower current harmonic distortion and reduced DC-link voltage ripple compared to the synchronous-frame PI controllers.
- The overall stationary-frame control strategy (DSOGI-FLL + PNSC + PR) is structurally simpler, computationally more efficient, and easier to implement than its synchronous-frame counterpart (DDSRF-PLL + PNSC + PI).
- The negative-sequence voltage suppression capability of the stationary-frame strategy is superior, confirming its suitability for robust solar inverter operation under adverse grid conditions.
The findings of this work provide valuable design guidelines for solar inverter manufacturers and grid operators, particularly in the context of grid-code compliance and fault ride-through requirements. Future research may extend this work to adaptive tuning of the FLL gains and PR controller parameters, as well as to the consideration of weak-grid scenarios and grid impedance variations.
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