In recent years, the increasing awareness of energy crises and environmental protection has driven rapid development in renewable energy and distributed generation (DG) technologies. As the interface between renewable energy generation systems and the power grid, the solar inverter plays a critical role in ensuring stable and reliable power conversion. Traditional control strategies for solar inverters are typically designed under balanced three-phase grid conditions. However, in practical systems, grid voltages often become unbalanced due to faults, large single-phase loads, or other disturbances. Under such asymmetric grid faults, negative sequence voltage components appear, leading to power oscillations, current imbalance, and potential instability. Therefore, it is essential to investigate advanced control strategies for solar inverters capable of suppressing negative sequence voltage and maintaining high performance under unbalanced grid conditions.
This paper presents a comprehensive study on the design, analysis, and experimental validation of solar inverter control strategies under asymmetric grid faults. Two distinct approaches are examined: one based on the synchronous reference frame (SRF) and the other based on the stationary reference frame (αβ). The control system involves three key aspects: grid synchronization, power control, and current regulation. For the synchronous frame approach, a decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL) is employed for grid synchronization, while dual proportional-integral (PI) regulators are used for current control. In contrast, the stationary frame approach utilizes a dual second-order generalized integrator frequency-locked loop (DSOGI-FLL) for grid synchronization, with dual proportional-resonant (PR) controllers for current regulation. A detailed comparison of these two strategies is provided, focusing on their principles, implementation complexity, and performance under asymmetric faults.
Both simulation and experimental studies are carried out on a test platform based on the TMS320F28335 digital signal processor. The results demonstrate that the stationary frame control strategy not only achieves better dynamic and steady-state performance but also features a simpler control structure and easier implementation. This work provides valuable guidelines for the design of solar inverter controllers intended for operation under unbalanced grid conditions.
System Architecture
The overall control block diagram of a solar inverter under asymmetric grid faults is shown conceptually in Figure 1 (see the experimental setup section for the hardware platform). The three-phase grid is connected to the inverter through an L-filter. The control system comprises a grid synchronization unit, a power controller, and a current controller. The grid synchronization unit extracts the frequency, phase, and amplitude of the grid voltage even under unbalanced conditions. The power controller computes the reference currents to regulate active and reactive power, aiming to eliminate power oscillations. The current controller forces the actual grid currents to track the references, generating PWM signals for the inverter switches.
Grid Synchronization
Accurate grid synchronization is crucial for solar inverter control, especially during faults that cause sudden changes in voltage amplitude, phase, and frequency. Two major synchronization methods are compared in this work: the DDSRF-PLL (synchronous frame) and the DSOGI-FLL (stationary frame).
DDSRF-PLL
The DDSRF-PLL is an improved version of the conventional synchronous reference frame PLL. In an unbalanced three-phase system, the grid voltage vector contains both positive-sequence and negative-sequence components rotating in opposite directions. The DDSRF-PLL performs two coordinate transformations—one for the positive-sequence dq frame rotating at ωt and one for the negative-sequence dq frame rotating at −ωt. By applying decoupling networks and low-pass filters, the positive and negative sequence components are separated. The positive-sequence d-axis voltage is then regulated to zero via a PI controller, which yields the grid frequency and phase angle.
The transformation matrix from the αβ frame to the positive and negative dq frames is:
$$
T_{dq}^{+} = \begin{bmatrix} \cos\theta & \sin\theta \\ -\sin\theta & \cos\theta \end{bmatrix}, \quad T_{dq}^{-} = \begin{bmatrix} \cos\theta & -\sin\theta \\ \sin\theta & \cos\theta \end{bmatrix}
$$
The structure of the DDSRF-PLL includes a decoupling unit, low-pass filters, and PI regulators. The main advantage is the ability to track the positive-sequence phase even under severe imbalance. However, the presence of PI controllers and decoupling loops introduces complexity and tuning difficulties, and the output frequency may exhibit oscillations during transients.
DSOGI-FLL
The DSOGI-FLL operates directly in the stationary αβ frame. It employs two second-order generalized integrators (SOGIs) to generate orthogonal signals for the α and β components of the grid voltage. The SOGI structure is shown conceptually in the block diagram. The outputs of the SOGIs, v’ and qv’, are used to compute the positive and negative sequence components via simple algebraic operations. A frequency-locked loop (FLL) then adjusts the resonant frequency of the SOGIs to match the grid frequency. The FLL directly controls the frequency error, rather than the phase error, making it faster and more robust under phase jumps.
The transfer function of a SOGI is:
$$
G_{SOGI}(s) = \frac{k \omega’ s}{s^2 + k \omega’ s + \omega’^2}
$$
where ω’ is the estimated frequency and k is the damping factor. The DSOGI-FLL block diagram consists of two such SOGIs for the α- and β-axis voltages. Compared to the DDSRF-PLL, the DSOGI-FLL eliminates the need for decoupling networks and reduces computational complexity. It also exhibits faster frequency tracking dynamics and lower steady-state ripples under unbalanced conditions.
Power Control
Under asymmetric grid faults, both the grid voltage and current contain positive and negative sequence components. The instantaneous active and reactive power will oscillate at twice the grid frequency unless the control strategy specifically addresses these oscillations. The positive-negative sequence control (PNSC) strategy is adopted here. The PNSC strategy calculates the reference currents such that either the active power oscillation or the reactive power oscillation is eliminated, depending on the control objective. In this work, only active power transfer is considered, and the reactive power reference is set to zero. The active power reference is generated by the DC-link voltage controller.
According to the PNSC principle, the reference current vector in the stationary αβ frame is given by:
$$
\vec{i}^{*} = \frac{P^{*}}{|\vec{v}^{+}|^2} \vec{v}^{+} + \frac{P^{*}}{|\vec{v}^{-}|^2} \vec{v}^{-}
$$
where \(\vec{v}^{+}\) and \(\vec{v}^{-}\) are the positive and negative sequence voltage vectors, respectively, and \(P^{*}\) is the active power reference. This expression ensures that the instantaneous active power is constant (oscillation-free) under unbalanced grid conditions. The resulting three-phase reference currents are generally unbalanced, which is acceptable for the inverter as long as the current limits are respected.
Current Regulation
Two current control schemes are designed and compared: a dual PI controller in the synchronous frame and a dual PR controller in the stationary frame.
Dual PI Current Controller (Synchronous Frame)
In this scheme, the grid currents are first transformed into positive and negative synchronous dq frames. For the positive sequence, the dq components are DC quantities; for the negative sequence, they are also DC in the negative dq frame. Two separate PI controllers are used for the d-axis and q-axis currents of each sequence. However, to avoid steady-state errors, cross-coupling terms and feedforward voltage compensations are required. This increases the control complexity. The block diagram includes decoupling units and multiple coordinate transformations. Moreover, the PI controllers rely on the accurate phase angle from the DDSRF-PLL, which may have residual errors during faults.
Dual PR Current Controller (Stationary Frame)
In the stationary αβ frame, the grid currents are sinusoidal at the fundamental frequency. A proportional-resonant (PR) controller achieves infinite gain at the resonant frequency, enabling zero steady-state error for sinusoidal references. The transfer function of an ideal PR controller is:
$$
G_{PR}(s) = K_p + \frac{2 K_i s}{s^2 + \omega_0^2}
$$
where ω₀ is the grid frequency. Two PR controllers are employed, one for the α-axis current and one for the β-axis current. No coordinate transformation is needed, and the controller directly processes the measured αβ currents. The resonant frequency is provided by the DSOGI-FLL, which is robust to frequency variations. This scheme is simpler and avoids the cross-coupling and decoupling issues inherent in the synchronous frame approach.
Simulation Studies
Simulations were conducted using MATLAB/Simulink to evaluate the two control strategies under asymmetric fault conditions. The system parameters are listed in Table 1. The grid voltage was set to 57.4 V (line-to-line RMS), frequency 50 Hz, grid-side inductance 7 mH, DC-link voltage 150 V, DC-link capacitor 1980 μF, and load resistance 60 Ω. The control parameters were tuned based on system transfer functions and iterative simulation adjustments.
| Parameter | Value |
|---|---|
| Grid voltage (peak phase) | 57.4 V |
| Grid frequency | 50 Hz |
| Grid-side inductor | 7 mH |
| DC-link voltage reference | 150 V |
| DC-link capacitor | 1980 μF |
| Load resistance | 60 Ω |
| PWM switching frequency | 10 kHz |
| DDSRF-PLL: k_p | 0.7 |
| DDSRF-PLL: k_i | 30 |
| DSOGI-FLL: k | 1.41 |
| DSOGI-FLL: τ | 100 |
| PI controller: k_p | 150 |
| PI controller: k_i | 20 |
| PR controller: K_p | 200 |
| PR controller: K_i | 30 |
A two-phase voltage dip was applied at t = 2 s. The simulation results for the DDSRF-PLL and DSOGI-FLL synchronization outputs are compared in terms of frequency detection. The DDSRF-PLL showed a frequency overshoot of about ±3.75 Hz around the nominal value and required approximately 20 ms to settle. The DSOGI-FLL exhibited a smaller deviation (±1.25 Hz) and settled within about 10 ms. This superior performance is attributed to the direct frequency control of the FLL, which avoids the phase loop delay.
For the current control comparison, the dual PI controller (synchronous frame) and the dual PR controller (stationary frame) were evaluated under the same fault. Both schemes successfully regulated the grid currents and maintained the DC-link voltage. However, the synchronous frame PI controller required more complex decoupling and coordinate transformations, leading to higher steady-state current ripple and slower transient response. In contrast, the stationary frame PR controller achieved smoother currents with lower total harmonic distortion (THD) and faster recovery after the fault. The simulation results confirm that the stationary frame strategy is more effective for solar inverter operation under unbalanced grid conditions.
Experimental Validation
To validate the simulation findings, an experimental platform was built using a TMS320F28335 DSP as the main controller. All control algorithms, including the outer DC-link voltage loop, inner current loops (PI and PR), and grid synchronization blocks, were implemented in real time. The switching frequency was 10 kHz with sinusoidal PWM (SPWM). Because obtaining a real faulted grid voltage is impractical, a separate voltage source inverter controlled by a dSPACE DS1104 was used to generate the unbalanced grid voltage profile. The experimental results are summarized in Table 2.
| Metric | DDSRF-PLL + PI (Synchronous Frame) | DSOGI-FLL + PR (Stationary Frame) |
|---|---|---|
| Frequency overshoot under fault | ±3.75 Hz | ±1.25 Hz |
| Settling time of frequency | ~20 ms | ~10 ms |
| Steady-state frequency ripple | Small but visible | Negligible |
| Current THD during fault | Higher (approx. 5-6%) | Lower (approx. 2-3%) |
| Controller complexity | High (multiple transforms, decoupling) | Low (direct αβ control) |
| Ease of tuning | Difficult | Simple |
The experimental waveforms show that when a two-phase voltage dip occurs, the DDSRF-PLL output frequency fluctuates between about 46.25 Hz and 52.5 Hz, while the DSOGI-FLL output remains within 48.75 Hz to 50 Hz. The currents under the PI controller exhibit more distortion and a slightly longer recovery time. In contrast, the PR controller produces nearly sinusoidal currents with fast dynamic response. These experiments confirm that the stationary frame control strategy (DSOGI-FLL + PR) outperforms the synchronous frame approach (DDSRF-PLL + PI) in terms of both dynamic performance and steady-state accuracy. Furthermore, the stationary frame structure is simpler, requiring fewer computational resources and less tuning effort, which makes it highly attractive for practical solar inverter applications.
Conclusion
This paper has presented a comprehensive design, analysis, and experimental comparison of two control strategies for solar inverters operating under asymmetric grid faults. The first strategy relies on the synchronous reference frame, using a DDSRF-PLL for grid synchronization and dual PI controllers for current regulation. The second strategy adopts the stationary reference frame, employing a DSOGI-FLL and dual PR controllers. Both strategies are capable of suppressing negative sequence voltage effects and maintaining stable operation during unbalanced faults. However, the stationary frame approach offers several advantages: faster and more accurate frequency tracking, simpler control architecture, easier parameter tuning, and lower current distortion. Simulation and experimental results validate these conclusions. Therefore, the stationary frame control strategy is recommended as the preferred solution for modern solar inverter designs requiring robust performance under unbalanced grid conditions.
Future work will focus on extending the strategy to handle voltage sags with phase jump and harmonics, as well as integrating advanced current limiting techniques to protect the inverter during severe faults.