In this paper, I present a comprehensive modeling and control strategy for a capacitor voltage reduced quasi Z-source three-level inverter. The proposed topology belongs to a special family among various types of solar inverters, combining the advantages of impedance networks and multilevel topologies. I first analyze the basic operating principles of the inverter, then derive the small-signal model of the DC-side quasi Z-source network using state-space averaging and perturbation techniques. Based on the derived transfer functions, I design a voltage-current dual-loop control system that indirectly regulates the DC bus voltage while maintaining constant output voltage. Simulation results validate the correctness of the small-signal model and the effectiveness of the proposed controller under steady-state and transient conditions. The study provides a systematic framework for modeling and controlling this emerging topology, contributing to the development of high-performance types of solar inverters for renewable energy applications.
Keywords: quasi Z-source three-level inverter; quasi Z-source network; neutral-point-clamped; small-signal model; voltage-current dual-loop control
1. Introduction
The rapid growth of photovoltaic systems has spurred the development of various types of solar inverters, each aiming to improve efficiency, power density, and reliability. Among these, the Z-source inverter (ZSI) introduced by Peng has attracted considerable attention due to its unique ability to perform voltage boost and inversion in a single stage, while allowing shoot-through states that eliminate dead-time issues. Over the past two decades, numerous variants of ZSI have been proposed for different application scenarios, including quasi Z-source inverters (qZSI), switched-inductor ZSI, and cascaded ZSI. Meanwhile, multilevel inverters, particularly the neutral-point-clamped (NPC) three-level topology, are widely adopted in medium- and high-power applications because they offer lower harmonic distortion, reduced device voltage stress, and improved electromagnetic compatibility. Integrating impedance networks with multilevel topologies creates advanced topologies that represent promising types of solar inverters for future grid-connected systems.
The capacitor voltage reduced quasi Z-source three-level inverter (CVR-qZSI-NPC) is a recently developed topology that significantly lowers the voltage stress on the Z-source capacitors compared to conventional qZSI-NPC inverters. This reduction enhances the reliability and reduces the cost of the passive components. However, the dynamic behavior of the DC-side network in this inverter has not been thoroughly investigated. Understanding the small-signal characteristics is crucial for designing closed-loop controllers that ensure stable DC bus voltage and high-quality AC output. In this work, I address this gap by establishing a small-signal model of the quasi Z-source network and deriving the transfer function from shoot-through duty cycle to capacitor voltage. Based on the model, I propose a voltage-current dual-loop control scheme that indirectly regulates the DC bus voltage by controlling the capacitor voltage and inductor current. The controller achieves good steady-state accuracy and fast dynamic response against input voltage disturbances and load changes. The study not only provides insights into the intrinsic dynamics of this topology but also offers a practical control design methodology applicable to similar types of solar inverters.
2. Basic Principle of the Capacitor Voltage Reduced Quasi Z-Source Three-Level Inverter
The topology of the CVR-qZSI-NPC inverter is shown in Fig. 1 (link inserted later). It consists of a DC voltage source, a quasi Z-source network composed of four inductors (L1–L4), four capacitors (C1–C4), and two diodes (VD1, VD2), followed by a standard NPC three-level inverter bridge. The quasi Z-source network enables the inverter to operate in shoot-through states, boosting the DC bus voltage. Compared with conventional Z-source NPC inverters, this structure halves the peak voltage across each capacitor, hence the name “capacitor voltage reduced”.
There are three operational states: non-shoot-through (NST), upper shoot-through (UST), and lower shoot-through (LST). During NST, both diodes conduct, and the inductors and capacitors are in parallel. For a symmetric network where all inductances are L and all capacitances are C, the following relationships hold:
$$
U_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L, \quad U_{C1}=U_{C2}=U_{C3}=U_{C4}=U_C
$$
Applying KVL yields:
$$
U_i = U_{dc} + 4U_C, \quad U_L = -U_C
$$
During UST and LST, the equivalent circuits differ. For UST:
$$
U_L = U_{dc}/4, \quad U_i = U_{dc}/2 + 2U_C
$$
Similarly for LST. In one switching period Ts, both UST and LST are applied for T0 each (total shoot-through time 2T0). The volt-second balance on each inductor gives:
$$
U_L T_s = -U_C (T_s – 2T_0) + \frac{U_{dc}}{4} T_0 + \frac{U_{dc}}{4} T_0 = 0
$$
From this, the steady-state capacitor voltage is:
$$
U_C = \frac{D_0 U_{dc}}{2(1 – 2D_0)}
$$
where D0 = T0/Ts is the shoot-through duty ratio. The DC bus voltage in non-shoot-through and shoot-through states are:
$$
U_i = \begin{cases}
\frac{U_{dc}}{1-2D_0}, & \text{NST} \\[4pt]
\frac{U_{dc}}{2(1-2D_0)}, & \text{UST/LST}
\end{cases}
$$
The inverter output phase voltage peak is:
$$
U_x = M \cdot \frac{U_{dc}}{2(1-2D_0)} = M B \frac{U_{dc}}{2}
$$
with boost factor B = 1/(1-2D0) > 1. Thus the topology belongs to the family of boost types of solar inverters.
3. DC-Side Modeling
To analyze the dynamic behavior of the quasi Z-source network, I separate the DC side (impedance network) from the AC side. Using state-space averaging, I define the state vector x = [iL1, iL2, uC1, uC2]T, and input vector u = [udc, iload1, iload2]T. For each switching state, the state equations are derived.
Non-shoot-through state (matrix A1, B1):
$$
A_1 = \begin{bmatrix}
0 & 0 & -1/L & 0 \\
0 & 0 & 0 & -1/L \\
1/C & 0 & 0 & 0 \\
0 & 1/C & 0 & 0
\end{bmatrix}, \quad
B_1 = \begin{bmatrix}
0 & 0 & 0 \\
0 & 0 & 0 \\
0 & -1/C & 0 \\
0 & 0 & -1/C
\end{bmatrix}
$$
Upper shoot-through state (A2, B2):
$$
A_2 = \begin{bmatrix}
0 & 0 & -1/L & 0 \\
0 & 0 & 0 & 1/L \\
1/C & 0 & 0 & 0 \\
0 & -1/C & 0 & 0
\end{bmatrix}, \quad
B_2 = \begin{bmatrix}
0 & 0 & 0 \\
1/(2L) & 0 & 0 \\
0 & 0 & -1/C \\
0 & 0 & 0
\end{bmatrix}
$$
Lower shoot-through state (A3, B3):
$$
A_3 = \begin{bmatrix}
0 & 0 & 1/L & 0 \\
0 & 0 & 0 & -1/L \\
-1/C & 0 & 0 & 0 \\
0 & 1/C & 0 & 0
\end{bmatrix}, \quad
B_3 = \begin{bmatrix}
1/(2L) & 0 & 0 \\
0 & 0 & 0 \\
0 & 0 & 0 \\
0 & -1/C & 0
\end{bmatrix}
$$
Averaging over one switching period with duty cycle d0 (dynamic) yields the averaged state-space model:
$$
\dot{x} = A x + B u
$$
where
$$
A = (1-2d_0)A_1 + d_0A_2 + d_0A_3
= \begin{bmatrix}
0 & 0 & \frac{2d_0-1}{L} & 0 \\
0 & 0 & 0 & \frac{2d_0-1}{L} \\
\frac{1-2d_0}{C} & 0 & 0 & 0 \\
0 & \frac{1-2d_0}{C} & 0 & 0
\end{bmatrix}
$$
$$
B = (1-2d_0)B_1 + d_0B_2 + d_0B_3
= \begin{bmatrix}
\frac{d_0}{2L} & 0 & 0 \\[4pt]
\frac{d_0}{2L} & 0 & 0 \\[4pt]
0 & \frac{2d_0-1}{C} & -\frac{d_0}{C} \\[4pt]
0 & -\frac{d_0}{C} & \frac{2d_0-1}{C}
\end{bmatrix}
$$
Introducing small perturbations around a steady-state operating point (D0, Udc, Iload), I linearize the system. The steady-state conditions give:
$$
I_L = \frac{1-D_0}{1-2D_0} I_{load}, \quad
U_C = \frac{D_0}{2(1-2D_0)} U_{dc}
$$
The small-signal model is derived as:
$$
\frac{d\hat{i}_{L1}}{dt} = \frac{2D_0-1}{L} \hat{u}_{C1} + \frac{D_0}{2L} \hat{u}_{dc} + \left( \frac{2U_C}{L} + \frac{U_{dc}}{2L} \right) \hat{d}_0
$$
$$
\frac{d\hat{u}_{C1}}{dt} = \frac{1-2D_0}{C} \hat{i}_{L1} + \frac{2D_0-1}{C} \hat{i}_{load1} – \frac{D_0}{C} \hat{i}_{load2} + \left( -\frac{2I_L}{C} + \frac{I_{load}}{C} \right) \hat{d}_0
$$
Due to symmetry, I consider only one side. Applying Laplace transform and simplifying, the transfer function from shoot-through duty cycle d0(s) to capacitor voltage uC(s) is:
$$
G_{ud}(s) = \frac{u_C(s)}{d_0(s)} = \frac{I_1 L s + U_1 (1-2D_0)}{L C s^2 + (1-2D_0)^2}
$$
where
$$
I_1 = I_{load} – 2I_L, \quad U_1 = \frac{U_{dc} + 4U_C}{2}
$$
This transfer function has one right-half-plane zero, indicating non-minimum phase behavior common in boost-derived types of solar inverters. The presence of the RHP zero limits achievable bandwidth and must be considered in controller design.
4. DC Bus Voltage Controller Design
The DC bus voltage of the CVR-qZSI-NPC inverter is a high-frequency pulsating square wave that is difficult to measure directly. However, the capacitor voltage uC is continuous and easily measurable. From steady-state relations, I derive:
$$
\frac{U_i}{U_C} = \frac{1}{D_0}
$$
During transients, the relationship between small perturbations is:
$$
\frac{u_i(s)}{d_0(s)} = \frac{1}{D_0} \frac{u_C(s)}{d_0(s)} + U_i
$$
Substituting the capacitor voltage transfer function yields:
$$
\frac{u_i(s)}{d_0(s)} = \frac{U_i L C s^2 + I_1 L s + U_i (1-2D_0)^2 + U_1 (1-2D_0)}{D_0 [L C s^2 + (1-2D_0)^2]}
$$
I adopt a voltage-current dual-loop control structure as shown in the block diagram (similar to Fig. 4 of the reference). The inner loop regulates the inductor current iL using a proportional controller (Kip). The inner plant transfer function is:
$$
\frac{i_L(s)}{d_0(s)} = \frac{U_1 C s + I_1 (1-2D_0)}{L C s^2 + (1-2D_0)^2}
$$
The closed-loop inner transfer function becomes:
$$
\frac{u_i(s)}{i_L(s)} = \frac{K_{ip} [U_1 (1-2D_0) – I_1 L s – U_i L C s^2]}{D_0 [L C s^2 + K_{ip} U_1 C + K_{ip} U_i C (1-2D_0)] s + K_{ip} I_1 (1-2D_0) + (1-2D_0)^2}
$$
The outer loop uses a PI controller (Kvp, Kvi) on the DC bus voltage error. The complete control system block diagram is shown below (insert link here). The reference voltage Ui_ref is set to the desired shoot-through state DC bus voltage.
This control strategy is applicable to various types of solar inverters that employ impedance networks, as it provides a systematic way to stabilize the DC bus voltage without direct measurement of the pulsating bus.
5. Simulation Analysis
I verify the theoretical analysis and control design through MATLAB/Simulink simulations. The system parameters are listed in Table I.
| Parameter | Symbol | Value |
|---|---|---|
| DC input voltage | Udc | 300 V |
| Quasi Z-source inductance | L | 5 mH |
| Quasi Z-source capacitance | C | 2200 μF |
| Shoot-through duty ratio (initial) | D0 | 0.167 |
| Modulation index | M | 0.85 |
| AC filter inductance | Lf | 30 mH |
| AC filter capacitance | Cf | 50 μF |
| Load resistance | Rload | 10 Ω |
| Switching frequency | fs | 2.5 kHz |
| Inner loop gain | Kip | 2.3×10⁻⁴ |
| Outer loop PI (proportional) | Kvp | 1.15 |
| Outer loop PI (integral) | Kvi | 3.6×10⁻⁴ |
First, I test the system without closed-loop control. The shoot-through duty ratio is fixed at 0.167. According to theory, the non-shoot-through DC bus voltage should be 450 V and shoot-through voltage 225 V. The simulation shows fluctuations between 442–447 V and 220–226 V respectively, confirming the need for closed-loop regulation.
With the dual-loop controller enabled, the steady-state DC bus voltage waveform exhibits sharp square edges: the non-shoot-through level is exactly 450 V, and the shoot-through level is exactly 225 V, accurately tracking the reference Ui_ref = 225 V (the shoot-through level). The capacitor voltage is about 37.5 V with small ripple; inductor current is about 14.5 A. The output phase voltage peak is 225 V and line voltage peak is 450 V, matching theoretical calculations.
To test transient performance, I introduce a step decrease in DC input voltage from 300 V to 290 V at t=0.32 s. The DC bus voltage dips briefly but recovers to 450 V within a few milliseconds, demonstrating robust disturbance rejection. The controller maintains the output voltage constant without overshoot.
The simulation confirms that the proposed modeling and control method is effective for this topology, and the methodology can be extended to other types of solar inverters that share similar impedance network dynamics.
6. Conclusion
In this work, I have derived a small-signal model for the capacitor voltage reduced quasi Z-source three-level inverter, revealing a right-half-plane zero in the control-to-capacitor-voltage transfer function. Based on the model, I designed a voltage-current dual-loop controller that indirectly regulates the pulsating DC bus voltage via capacitor voltage and inductor current control. Simulation results validate the model accuracy and demonstrate excellent steady-state and dynamic performance under input voltage disturbance. The control strategy is generalizable to a wide range of types of solar inverters that incorporate impedance networks, particularly those requiring boost capability and multilevel output. Future work will focus on experimental validation and extension to grid-connected applications with power factor control.