In recent years, the rapid development of renewable energy sources, such as solar power, has led to their large-scale integration into power systems to address the depletion of fossil fuels. To ensure grid security, high requirements are imposed on the voltage support capability of solar power plants during system operation and voltage faults. According to national standards, solar power stations must possess low-voltage ride-through (LVRT) capability, requiring them to inject reactive power into the grid during voltage faults to support the point of common coupling (PCC) voltage. However, during the fault recovery stage, transient reactive power imbalances caused by faults like commutation failures or pole blockages in HVDC systems can lead to severe overvoltage issues. For solar farms, this is primarily manifested in the rapid reactive power retraction capability of solar inverters. If solar inverters cannot quickly retract reactive power during fault clearance, reactive overcompensation occurs, resulting in overvoltage at the PCC.
The speed of reactive power retraction in solar systems during voltage recovery is closely related to the dynamic characteristics of the phase-locked loop (PLL). During LVRT, grid voltage often undergoes phase jumps at the occurrence and recovery of faults, causing the PLL to enter a new dynamic process, which adversely affects the phase-locking accuracy and output characteristics of solar systems. Additionally, since solar power plants are typically connected to the grid through multiple step-up transformers, the grid exhibits weak grid characteristics, impacting the stability and dynamics of the PLL. Research shows that in weak grids, as the short-circuit ratio (SCR) decreases, the system stability region gradually shrinks, necessitating a reduction in PLL bandwidth and an increase in control loop time constants to maintain stability. This slows down the response speed of control loops during LVRT recovery, potentially leading to delayed reactive power retraction, reactive overcompensation, and transient overvoltage.
Current improvements in PLL control under weak grid conditions mainly focus on two aspects: optimization of PLL control parameters and optimization of PLL control loops. For parameter optimization, methods based on phase margin and small-signal models have been proposed, but they often neglect the interaction between the PLL and other control loops. For control loop optimization, techniques such as adding low-pass filters or band-pass filters have been employed, but these may degrade transient performance. Other approaches include phase compensation to decouple the PLL from grid impedance and feedforward control methods. However, most studies focus on steady-state small-signal models and do not extensively discuss the response characteristics under large disturbances like LVRT.
Given the limited research on PLL dynamic response during voltage fault recovery and the slow reactive power retraction of solar inverters in weak grids, this paper analyzes the impact of phase jumps at the PCC on the transient voltage-reactive power characteristics of solar inverters during fault recovery. Based on this analysis, an improved control strategy for rapid reactive power retraction using PLL phase compensation is proposed. Theoretical analysis and simulation verification demonstrate that the proposed strategy effectively enhances the speed and accuracy of reactive power support during LVRT fault recovery.
Mathematical Model and Control Strategy of Solar Systems
The solar system is equivalent to a single-machine model, with the centralized solar inverter represented by an equivalent model and control strategy. The circuit topology of the solar inverter is a conventional two-level structure, employing current vector control, and connected to the grid via a transmission line. The solar inverter uses a dual-loop voltage and current control strategy. The PLL locks the phase of the PCC voltage, which is then used for d-q decomposition and coordinate transformation. The output of the dual-loop control is added to the PCC feedforward voltage signal to generate the internal voltage signal at the solar inverter output, which is input to the PWM generator to produce modulation signals and output the internal voltage $e_{abc}$, enabling grid current control.
When the system experiences an LVRT fault, the solar grid-connected system switches from normal operation control mode to LVRT control mode, i.e., single current loop control. When the terminal voltage of the solar unit drops below 0.9 p.u., the inverter control system directly inputs current reference values to the reactive current loop based on the detected grid voltage drop. The specific command calculation is as follows:
$$ I_d = \sqrt{I_N^2 – I_q^2} $$
$$ I_q = k(0.9 – U_s)I_N \quad \text{for} \quad U_s < 0.9 $$
where $I_d$ and $I_q$ are the active and reactive current reference values that the inverter needs to provide to the grid during the voltage dip, respectively. $I_q$ is positive when the inverter provides capacitive reactive power and negative for inductive reactive power. $I_N$ is the rated current of the solar inverter, $k$ is an empirical coefficient for reactive current calculation (ranging from 1.5 to 2.5), $U_s$ is the per-unit voltage during the LVRT fault, and $U_N$ is the grid rated voltage.
When the fault recovers and the terminal voltage rises above 0.9 p.u., the solar inverter switches back to normal operation control mode. As the terminal voltage recovers to the rated value, the voltage phase also jumps, causing the PLL to enter a dynamic process. The following sections analyze the impact of the PLL dynamic process on the reactive power characteristics of the solar system during fault recovery.
Analysis of Reactive Overcompensation Mechanism During Fault Recovery
Analysis of PCC Voltage and Reactive Power Characteristics
The transient characteristic phasor diagram of the solar system during the voltage fault recovery stage is illustrated below. During the voltage fault, the PLL can stably lock the phase. $\vec{I_s}$ is the current output by the solar system to the grid based on the LVRT control strategy, and $\vec{E_s}$ is the phasor of the internal voltage $e_{abc}$ at the solar inverter output, with an angle $\phi$ to the d-axis. Neglecting the filter resistance component, we have:
$$ \vec{E_s} = \vec{U_s} + j\omega L_f \vec{I_s} $$
where $L_f$ is the filter inductance and $\omega$ is the grid angular frequency.
During the voltage recovery stage, since short-circuit faults are typically resistive, the PLL phase lags behind the PCC voltage phase. The PCC voltage recovers from $\vec{U_s}$ to $\vec{U_{s0}}$, with a voltage jump magnitude $\Delta \vec{U}$ and a phase jump angle $\Delta \theta$. At this point, the PLL has not yet tracked the phase jump. For $\vec{E_s}$, the internal voltage position is determined by the PLL and the voltage jump. According to the inverter control strategy, the current loop includes the PCC voltages $U_d$ and $U_q$ as feedforward compensation terms. Therefore, during voltage recovery, due to the increase in PCC voltage by $\Delta \vec{U}$, the internal voltage also increases by $\Delta \vec{U}$ to $\vec{E_{s0}}$, with the internal voltage phase changing to $\phi_0$. Based on the phasor positions of the internal voltage and PCC voltage, the inverter output current $\vec{I_{s0}}$ can be obtained. The phase relationship between $\vec{U_{s0}}$ and $\vec{I_{s0}}$ indicates that $\vec{I_{s0}}$ exhibits characteristics of supplying reactive power and absorbing active power to the grid. Although the solar inverter switches back to normal control mode with the reactive current reference typically set to zero, it still requires a dynamic adjustment process involving the PLL and current loop to fully retract reactive power. Before the control returns to steady state, the voltage jump causes reactive overcompensation at the PCC, increasing the risk of overvoltage.
The empirical relationship between voltage change, reactive overcompensation, and short-circuit capacity is given by:
$$ \Delta U_s = \frac{\Delta Q_s}{S_{\text{SCR}}} $$
where $\Delta U_s$ is the transient voltage rise at the terminal, $\Delta Q_s$ is the reactive power surplus from the inverter, and $S_{\text{SCR}}$ is the short-circuit capacity of the solar system. In per-unit systems, the short-circuit capacity is inversely proportional to the grid equivalent impedance:
$$ S_{\text{SCR}} = \frac{1}{Z_g} $$
where $Z_g$ is the per-unit value of the power system equivalent impedance. This equation shows that when the grid equivalent impedance is larger, the short-circuit capacity of the solar system is smaller, indicating a weaker grid. Under the same reactive overcompensation, the transient voltage rise at the terminal is larger,更容易导致过电压现象。
Impact of PLL on Solar System Dynamic Characteristics
Grid-connected control of solar systems typically uses vector control strategies, where the PLL follows the grid voltage for decoupling. The most widely used PLL structure is the synchronous reference frame PLL (SRF-PLL). During voltage fault occurrence and recovery, along with changes in voltage magnitude, the PCC voltage phase also jumps. Voltage phase jumps cause the PLL to re-enter the dynamic process of tracking the voltage phase. In weak grids, the PLL has a large time constant, slow response, and reduced dynamic performance, resulting in a longer dynamic response time due to phase jumps. This prolongs the phase deviation of the solar system, significantly affecting its transient characteristics. Since LVRT requires substantial reactive power compensation, a prolonged dynamic process of the PLL and current loop during voltage recovery can lead to delayed reactive power retraction, causing transient overvoltage at the PCC.
Therefore, both the voltage-reactive power characteristics during fault recovery and the dynamic process of the PLL in weak grids contribute to reactive overcompensation.
Improved Control Strategy for PLL
Phase Compensation Method for PLL
Based on the analysis in the previous section, the phase relationship between the internal voltage $\vec{E_{s0}}$ and the PCC voltage $\vec{U_{s0}}$ directly affects the power output characteristics of the solar system. The phase of $\vec{E_{s0}}$ is determined by the PLL phase. Therefore, by compensating the PLL phase, the output phase of the PLL can be altered, instantaneously changing the phase of $\vec{E_{s0}}$ (its magnitude remains unchanged at the moment of compensation). If the compensation phase is appropriate, the position of the internal voltage in the phasor diagram can be adjusted rapidly to achieve fast reactive power retraction, without going through the conventional control loop dynamic adjustment process. Since the compensation phase provides an initial position for $\vec{E_{s0}}$, the subsequent adjustment dynamics still rely on the performance of each control loop. Therefore, this phase compensation strategy does not affect the original design of voltage loop, current loop, and PLL parameters. It enhances the speed of reactive power retraction control during fault recovery on the basis of the original control. If the parameters of the original control loops are optimized and then this control strategy is applied, the control effect can be further improved on the basis of parameter optimization, enhancing the transient performance of the PLL and facilitating engineering applications.
The phase compensation control strategy is shown in the figure below. During the voltage recovery stage, when the terminal voltage is detected to recover to 0.9 p.u., a phase compensation angle $\beta$ is added, which is a constant. The phase compensation control remains engaged until the system is detected to be in steady state (stable for more than 5 seconds), after which it is withdrawn. The subsequent phase angle adjustment process is automatically regulated by the PLL PI loop to track the voltage phase angle.
The phase compensation angle $\beta$ effectively adds an initial value to the output phase of the PLL. This initial value can reposition the output internal voltage of the solar inverter to achieve rapid reactive power adjustment. With appropriate compensation, fast reactive power retraction can be achieved, reducing the risk of overvoltage at the PCC and improving system performance.
Determination of Phase Compensation Amount
The transient characteristic phasor diagram of the PLL after phase compensation is shown below. After adding the phase compensation angle $\beta$, the internal voltage becomes $\vec{E’_{s0}}$ ($\vec{E’_{s0}}$ has the same magnitude as $\vec{E_{s0}}$ but a different angle). The PLL locking coordinates are $d’-q’$, and the angle between the internal voltage and the PLL locking remains unchanged. Therefore, after phase compensation, the $d-q$ coordinate system obtained by PLL locking rotates by $\beta$, and the internal voltage phase jumps by $\beta$. To make the reactive power zero at this point, it is required that the difference phasor $Z_f \vec{I’_{s0}}$ between $\vec{E’_{s0}}$ and $\vec{U_{s0}}$ is perpendicular to $\vec{U_{s0}}$. The corresponding current phasor $\vec{I’_{s0}}$ is in the same direction as $\vec{E’_{s0}}$, with no reactive component. When the internal voltage $\vec{E’_{s0}}$ and the PCC voltage $\vec{U_{s0}}$ form a right triangle with an angle $\alpha$, the inverter neither supplies nor absorbs reactive power. In practical engineering, this requires $\vec{E_{s0}} \geq \vec{U_{s0}}$. If $\vec{E_{s0}} < \vec{U_{s0}}$, the solar system always absorbs reactive power, and overvoltage issues generally do not occur. Thus, the phase angle $\beta$ that the PLL needs to compensate is:
$$ \beta = \alpha + \Delta \theta – \phi_0 $$
where $\Delta \theta$ is the phase jump angle of the PCC voltage, with $\vec{U_{s0}} = |U_{s0}| \angle \Delta \theta$, and $\phi_0$ is the phase angle of the internal voltage $\vec{E_{s0}}$ before compensation.
The phase jump angle $\Delta \theta$ of the PCC voltage can be calculated by zero-crossing detection, comparing the instantaneous AC voltage zero-crossing time $T_1$ before the fault and the zero-crossing time $T_2$ after the fault. The phase jump angle is calculated using the time difference and grid voltage frequency:
$$ \Delta \theta = \left( \frac{(T_2 – T_1) \mod T}{T} \right) \times 2\pi $$
where $T$ is the unit cycle of the grid voltage.
$\alpha$ is the angle between $\vec{E’_{s0}}$ and $\vec{U_{s0}}$, and $\phi_0$ is the phase angle of the internal voltage $\vec{E_{s0}}$ before compensation, which is a variable related to the terminal voltage and internal voltage. The magnitude and phase of the internal voltage and terminal voltage can be determined from the voltage transient characteristic phasor diagram.
$$ \Delta \vec{U} = \vec{U_{s0}} – \vec{U_s} $$
$$ \vec{E_{s0}} = \vec{E_s} + \Delta \vec{U} \angle \phi_0 $$
where $\vec{E_s}$ is the internal voltage during the fault occurrence phase, determined by the compensation current and fault terminal voltage. Therefore, $\alpha$ and $\phi_0$ can be determined by the voltage dip degree and phase jump angle. Combining the equations and assuming $U_{s0} = 1$ p.u., the relationship between $\alpha$, $\phi_0$, and the voltage dip degree and phase jump angle can be obtained.
$$ \alpha = \cos^{-1} \left( \frac{1}{\sqrt{E_d^2 + E_q^2}} \right) $$
$$ \phi_0 = \tan^{-1} \left( \frac{E_q}{E_d} \right) $$
$$ E_d = \cos(\Delta \theta) + \omega L_f k(0.9 – U_s) $$
$$ E_q = \sin(\Delta \theta) + \omega L_f \left( I_N – k(0.9 – U_s) \right) $$
Substituting these into the equation for $\beta$, the phase compensation angle can be calculated. From the relational expressions, it can be seen that the phase compensation angle $\beta$ is related to both the voltage magnitude and phase jump angle during the fault. The relationship between $\beta$ and the voltage jump angle and dip degree is shown in the table below.
| Voltage Dip Degree (p.u.) | Phase Jump Angle (degrees) | Compensation Angle $\beta$ (degrees) |
|---|---|---|
| 0.2 | 30 | 15.2 |
| 0.2 | 50 | 25.4 |
| 0.4 | 30 | 12.8 |
| 0.4 | 50 | 22.1 |
| 0.6 | 30 | 10.5 |
| 0.6 | 50 | 18.9 |
From the above formulas and table, by measuring the terminal voltage phase angle and voltage dip degree during the fault phase, the PLL phase compensation angle for the improved strategy can be determined.
Application of Improved PLL Control in Asymmetric Faults
In addition to three-phase symmetric faults, power systems may experience asymmetric faults such as single-phase ground faults and two-phase short-circuit faults. When an asymmetric fault occurs in the power system, the synchronous reference frame PLL will be interfered with by harmonic components and cannot work normally. Therefore, in practical applications, the PLL usually adopts a decoupled double synchronous reference frame PLL (DDSRF-PLL), which first decouples the voltage into positive and negative sequences, and then locks the phase of the positive sequence voltage component, achieving synchronous signal extraction under asymmetric faults.
In asymmetric fault scenarios, the reactive power output characteristics of the solar inverter are as follows:
$$ Q_s = Q_0 + Q_1 \cos(2\omega t) + Q_2 \sin(2\omega t) $$
where $Q_s$ is the reactive power output of the solar inverter, $Q_0$ is the DC component of the reactive power output, and $Q_1$, $Q_2$ are the cosine and sine components of the double-frequency reactive power output, respectively.
When the asymmetric fault is cleared and the LVRT enters the fault recovery stage, the grid voltage returns to a three-phase symmetric state, and the negative and zero sequence components of the PCC voltage are zero. The proposed control method performs phase compensation on the PLL during the voltage recovery stage. Therefore, in the event of an asymmetric fault, the proposed control strategy will be applied to the positive sequence voltage control of the DDSRF-PLL to improve the characteristics of the positive sequence voltage component, thereby improving the DC component of the reactive power output of the solar inverter.
Simulation Verification
Verification of Improved PLL Control
This section verifies the improved method of PLL phase compensation. The grid fault is set to the same scenario as in the previous section, with a grid strength SCR of 2.4. The simulation parameters are shown in the table below.
| Parameter | Value |
|---|---|
| DC side voltage $U_{dc}$ (V) | 1500 |
| Grid side line voltage RMS $U_{line}$ (V) | 630 |
| Rated capacity $P_N$ (kW) | 1100 |
| Switching frequency $f_s$ (kHz) | 5 |
| Filter inductance 1 $L_1$ (μH) | 160 |
| Filter inductance 2 $L_2$ (μH) | 40 |
| Filter capacitor $C$ (μF) | 441 |
| PCC short-circuit ratio | 2.4 |
| Three-phase short-circuit ground fault dip degree $U_s$ (p.u.) | 0.55 |
| PLL proportional gain $K_{PLL}$ | 50 |
| PLL time constant $T_{PLL}$ | 0.05 |
The simulation results comparing the solar system without improved PLL control and with phase compensation control strategy are shown below. The PLL output phase comparison shows that during the voltage recovery stage, the PLL phase with the improved control strategy leads the PCC voltage phase. The reactive power characteristics comparison shows that with the phase compensation improved control strategy, the reactive power can retract to zero within 15 ms, compared to 40 ms without the improved control strategy, significantly speeding up reactive power retraction. The PCC voltage characteristics comparison shows that with the phase compensation control strategy, the voltage drops below 1.1 p.u. within 15 ms, effectively suppressing PCC overvoltage.
The impact of the improved PLL control strategy on the grid-connected stability of the solar system under different grid strengths is verified using time-domain analysis. The PCC voltage characteristics under different grid strengths are shown in the table below. Under different grid strengths, the improved PLL control strategy based on phase compensation can suppress the transient overvoltage of the solar system PCC and accelerate the voltage reaching the allowable value. When the SCR is 1.4, due to the excessively weak grid, the traditional grid-following LVRT control strategy may exhibit voltage oscillations during the voltage dip phase. In this scenario, the proposed control strategy can also effectively suppress transient overvoltage during the fault recovery stage.
| SCR | Without Compensation Overvoltage (p.u.) | With Compensation Overvoltage (p.u.) | Recovery Time (ms) |
|---|---|---|---|
| 1.4 | 1.25 | 1.12 | 20 |
| 2.4 | 1.18 | 1.08 | 15 |
| 3.0 | 1.15 | 1.05 | 10 |
Effect Verification of Improved PLL Control Strategy in Multiple Scenarios
Considering some practical scenarios faced in the application of the control strategy, the effect of the proposed improved control strategy is investigated in two scenarios: asymmetric faults and post-fault line switching.
Asymmetric Fault Scenario
When an asymmetric fault occurs in the system, both positive and negative sequence components need to be considered. The positive and negative sequence voltage and current extraction method based on numerical calculation is used, and the proposed improved control strategy is applied to the positive sequence component control loop, while the negative sequence component adopts a negative sequence current suppression control strategy. This section mainly verifies and analyzes the LVRT of single-phase and two-phase short-circuit faults. The simulation parameters are the same as the above example.
When the system experiences a phase-A ground fault and a phase-AB two-phase short-circuit fault, the positive sequence voltage, transient reactive power comparison waveforms, and terminal voltage comparison during the recovery stage are shown in the tables below. In the simulation of two asymmetric fault types, during the fault clearance stage, the use of PLL phase compensation has a reactive power absorption effect on the positive sequence component, speeding up the transient reactive power retraction, and the terminal transient overvoltage phenomenon is also alleviated to some extent. Although the impact of single-phase and two-phase short-circuit faults is smaller compared to three-phase short-circuit ground faults, and the overvoltage performance is not significant, it can still be observed that the phase compensation method has a certain effect on suppressing terminal overvoltage and can speed up reactive power retraction within ten to twenty milliseconds.
| Fault Type | Without Compensation Reactive Overshoot (p.u.) | With Compensation Reactive Overshoot (p.u.) | Voltage Peak (p.u.) |
|---|---|---|---|
| Single-Phase Ground | 0.15 | 0.05 | 1.12 |
| Two-Phase Short | 0.12 | 0.04 | 1.10 |
Post-Fault Line Switching Scenario
For actual system faults, the grid side may experience partial line switching and withdrawal from operation. Due to line withdrawal, there is a deviation in the PCC voltage phase before and after the fault, meaning the phase angle compensation amount $\Delta \theta$ cannot be accurately obtained. Through simulation, the PCC voltage phase changes after line switching under different grid strengths are obtained, as shown in the table below. The weaker the grid strength (smaller SCR), the larger the phase difference before and after line switching.
| SCR Change | Pre-Fault Voltage Phase | Fault Phase | Post-Fault Phase Without Line Switching | Post-Fault Phase With Line Switching |
|---|---|---|---|---|
| 3→2.4 | 0° | -49.3° | 0° | 10.1° |
| 5→3.3 | 0° | -54.8° | 0° | 5.4° |
| 10→8.7 | 0° | -57.2° | 0° | 3.9° |
Set the fault scenario as follows: SCR is 3, the system experiences a voltage fault at 3 s, a line is switched due to the fault at 3.2 s, and the fault is cleared at 4 s. The simulation results show that compared to the fault scenario without line switching, with line withdrawal, there is a deviation in the compensation phase. Although the reactive power retraction speed and PCC voltage drop speed slow down, the PCC voltage can still drop below 1.1 p.u. within 15 ms, and the reactive power retracts to zero within 10 ms, also having a good effect on suppressing PCC overvoltage.
Experimental Verification
Based on the RT-Lab hardware-in-the-loop simulation platform, the proposed improved PLL control strategy is experimentally verified. The RT-Lab hardware-in-the-loop simulation platform consists of an upper computer, a real-time simulator, a signal conversion board, a controller, and a wave recorder. In the upper computer, the circuit model and control model are built using Simulink, and the FPGA model is compiled and downloaded to the real-time simulator; the real-time simulator is responsible for receiving signals, solving the circuit, and outputting voltage and current.
Set the grid fault to the same scenario as in the previous section, with a grid strength SCR of 2.4. The experimental results are basically the same as the simulation results, further verifying the effectiveness of the control strategy. The key performance metrics from the experiment are summarized in the table below.
| Metric | Without Compensation | With Compensation |
|---|---|---|
| Reactive Power Retraction Time (ms) | 40 | 15 |
| Overvoltage Peak (p.u.) | 1.18 | 1.08 |
| Stability Time (ms) | 50 | 20 |
Conclusion
This paper analyzes the impact of the PLL on the dynamic response characteristics of solar systems during the voltage fault recovery stage and proposes an improved control strategy based on PLL phase compensation and feedforward compensation. Through simulation of the voltage fault characteristics of the solar system, the effectiveness of the proposed control strategy is verified. The main conclusions are as follows.
1. During the voltage fault recovery stage, the PCC voltage phase jumps, affecting the dynamic response characteristics of the solar system. By analyzing the voltage phasor diagram of the solar system, this paper explains the mechanism by which PCC voltage phase jumps lead to reactive overcompensation and PCC overvoltage in solar systems.
2. An improved PLL control strategy based on phase compensation is proposed. The proposed control strategy enables the solar system to achieve rapid reactive power retraction during fault recovery in various fault scenarios, effectively suppressing overvoltage.
3. The RT-Lab hardware-in-the-loop simulation platform is used to experimentally verify the improved PLL control strategy, further verifying the effectiveness of the proposed control strategy.
The proposed control strategy enhances the rapid reactive power retraction capability of solar inverters, effectively suppressing transient overvoltage issues during the low-voltage fault recovery stage. This is particularly important for the stable operation of solar power systems in weak grids. Future work could focus on optimizing the compensation angle calculation for real-time applications and extending the strategy to other types of inverters and grid conditions.