With the rapid advancement of renewable energy technologies, solar power generation has become a cornerstone of the global energy structure. Solar inverters, serving as critical energy conversion interfaces between photovoltaic arrays and the grid, directly influence grid stability and energy conversion efficiency. Research indicates that when data acquisition delays exceed the 5 ms threshold, system energy conversion efficiency drops by 2–3 percentage points; if sampling accuracy decreases by 0.5%, the total harmonic distortion (THD) deteriorates to 1.8 times the grid standard limit. Therefore, there is an urgent need to develop data acquisition systems with high real-time performance and precision for solar inverters.
Current research on solar inverter data acquisition systems faces challenges in balancing real-time performance and accuracy. For instance, systems based on BP neural networks can reduce data errors but struggle to meet real-time requirements. X86 architecture-based systems with dual-kernel structures like Xenomai and EtherCAT achieve microsecond-level response but suffer from inherent interrupt latency and sampling jitter under high loads, leading to reduced data accuracy. Data acquisition systems utilizing Xvisor virtual machines improve real-time performance compared to traditional microcontrollers, but the virtualization layer introduces additional latency, affecting sampling accuracy and time synchronization precision. LabVIEW-based systems simplify development through graphical programming but encounter measurement deviations in high-frequency sampling or multi-channel synchronous scenarios due to underlying hardware clock synchronization limitations. FPGA-based systems employ digital phase-locked loops (DPLL) and temperature-compensated crystal oscillators (TCXO) for real-time data transmission and precise tracking, yet multi-clock domain designs pose metastability risks, potentially causing sporadic data acquisition errors.
This paper proposes a high-precision solar inverter data acquisition system based on a hybrid architecture in Linux. First, the Linux kernel is enhanced with the PREEMPT_RT mechanism, incorporating dynamic preemption decisions, lock mechanism optimizations, and interrupt response guarantees to reduce task switching time and improve system real-time performance. Second, to enhance data accuracy, a FIR-IIR cascade structure is adopted, ensuring signal phase integrity while achieving deep suppression of high-frequency noise. The system design focuses on achieving voltage measurement accuracy of 0.8%, current measurement accuracy of 1%, and a system response time of less than 5 ms, enabling stable and reliable real-time acquisition and processing of solar inverter parameters.
Overall System Design
The system employs a layered architecture consisting of four functional layers: the front-end acquisition layer, the Linux real-time system layer, the data processing layer, and the application layer. The overall framework is illustrated in the following diagram, which showcases the integration of components in a solar inverter setup.
The front-end acquisition layer utilizes HLW8110 and BL0942 metering chips to collect key parameters from solar inverters. A 24-bit analog-to-digital converter (ADC) is used for analog-to-digital conversion, with a sampling frequency of up to 250 kHz, effectively meeting high-speed data acquisition requirements. Input overvoltage protection and anti-interference designs ensure stable operation in complex grid environments.
The Linux real-time system layer is built on the Linux kernel’s real-time preemptive scheduling algorithm, managing and scheduling real-time tasks. By configuring algorithm parameters and optimizing interrupt handling mechanisms, interrupt latency is controlled within 50 μs, enhancing system real-time response and data processing continuity, thereby preventing data loss and transmission blockages.
The data processing layer employs a FIR and IIR cascade filtering algorithm, where FIR avoids phase distortion and IIR reduces high-frequency noise amplitude errors, effectively suppressing high-frequency interference and system noise to improve data accuracy. Through outlier detection and data redundancy strategies, the system performs self-checking and recovery during data acquisition anomalies, ensuring the reliability of critical data.
The application layer provides data storage, display, and control functions, supporting data storage for over 30 days. It integrates mechanisms such as breakpoint resumption, data compression, and link self-healing, enabling efficient and stable remote communication under large data volumes for solar inverters.
System Design Principles
Adaptive Real-Time Preemptive Scheduling Algorithm
PREEMPT_RT is a key technology in the Linux kernel for enhancing real-time performance. By converting the standard Linux kernel into a fully preemptive real-time operating system and reconstructing kernel synchronization mechanisms and scheduling strategies, it significantly reduces system response latency and improves determinism for solar inverter applications.
To address the limitations of traditional PREEMPT_RT—such as system jitter due to full preemption, task blocking from RCU write operation waits, and priority inversion chains from priority inheritance protocols—the adaptive real-time preemptive scheduling algorithm introduces improvements in three areas, as shown in the following conceptual diagram of RT method enhancements.
First, the dynamic preemption threshold (DPT) mechanism optimizes task scheduling efficiency. A dynamic_threshold field is added to task_struct, forming a dynamic priority tuple with the base priority prio. In the scheduler core logic, a threshold judgment condition is incorporated, triggering preemption only when the current task’s dynamic preemption threshold is lower than the requesting task’s priority, effectively reducing unnecessary context switches.
Second, modifications to the rcu_assign_pointer function in the kernel/rcu/update.c file eliminate blocking delays in RCU operations. The improved function introduces a task type awareness mechanism, using current->flags and RT_FLAG bit operations to determine the real-time attributes of the current task. For identified real-time tasks, the system checks for Intel TSX instruction set support and transitions to a newly designed fast path if available.
Third, the criticality-aware priority inheritance protocol (CPIP) mechanism resolves priority inversion chains. The mutex lock data structure is enhanced by adding a chained owner management field chained_owner to the rt_mutex structure in kernel/lock/rtmutex_common.h, enabling the mutex to track and maintain complete lock dependency chains. By modifying the rt_mutex_prio function in kernel/lock/rtmutex.c, recursive priority elevation is achieved, implementing chained priority inheritance. A comparison of improved RT method performance versus traditional RT methods is summarized in Table 1.
| Metric | Standard RT | Improved RT | Improvement (%) |
|---|---|---|---|
| Maximum Scheduling Latency (μs) | 152 | 89 | 41.4 |
| RCU Write Latency (μs) | 48 | 21 | 56.3 |
| Task Switches (times/s) | 12300 | 7150 | 41.9 |
| Priority Inversion Incidence (%) | 2.1 | 0 | 100 |
As shown in Table 1, the improved real-time scheduling algorithm significantly enhances Linux real-time performance: maximum scheduling latency is reduced by 41.4%, RCU operation latency is decreased by 56.3%, task switching frequency is lowered by 41.9%, and priority inversion is completely eliminated, thereby improving system real-time performance for solar inverters.
Hybrid Filter Design Principles
In the proposed hybrid filter cascade architecture, FIR processes the signal, and IIR suppresses high-frequency noise interference, enhancing the accuracy of collected data from solar inverters. The output voltage on the AC side of a solar inverter can be expressed as:
$$ v_{ac}(t) = V_1 \sin(2\pi f_1 t) + \sum_{h=3,5,7} V_h \sin(2\pi f_h t) + n_{high}(t) $$
where \( f_1 = 50 \) Hz is the fundamental frequency, \( f_h \) are the odd harmonic frequencies (h = 3, 5, 7), and \( n_{high}(t) \) is the high-frequency noise component.
Based on power system stability and power quality requirements, multi-dimensional filtering performance indicators are established: the passband characteristic must ensure passband ripple does not exceed 0.2 dB in the 45–55 Hz frequency range; the stopband characteristic requires at least 40 dB of attenuation, with suppression of no less than 50 dB for high-frequency components above 1 kHz.
FIR Filter
A 65th-order low-pass filter based on the Kaiser window function (parameter β = 5) is employed, ensuring high-frequency suppression while optimizing the filter’s phase response characteristics. The impulse response is:
$$ h_{FIR}(n) = \frac{\sin(2\pi f_c (n – M))}{\pi (n – M)} \cdot w(n), \quad f_c = 60 \text{ Hz}, \quad M = 32 $$
where the cutoff frequency \( f_c \) is set to 60 Hz, and the half-filter length M is 32. The discrete time index variable n ranges from M to 2M. A comparison of key parameters for FIR filters using Kaiser, Blackman, and rectangular windows is shown in Table 2.
| Parameter | Passband Ripple (dB) | Stopband Attenuation (dB) | Group Delay Fluctuation |
|---|---|---|---|
| Kaiser | 0.18 | 51.2 | 0.0 |
| Blackman | 0.21 | 42.1 | 0.5 |
| Rectangular | 0.25 | 40.5 | 1.0 |
As seen in Table 2, the FIR filter designed with the Kaiser window (β = 5) reduces passband ripple by approximately 14% compared to the rectangular window; stopband attenuation is improved by 8–10 dB, effectively suppressing harmonic interference; and group delay fluctuation is zero, achieving perfect linear phase and avoiding signal time-domain distortion for solar inverters.
IIR Filter
For specific harmonics such as 150, 250, and 350 Hz, a second-order direct-form band-stop filter group is used. The transfer function for each IIR unit is defined as:
$$ H_{IIR,h}(z) = \frac{1 – 2\cos(\omega_h) z^{-1} + z^{-2}}{1 – 2\rho\cos(\omega_h) z^{-1} + \rho^2 z^{-2}} $$
where \( \omega_h \) is the normalized angular frequency, and ρ is the pole radius control parameter. Compared to traditional Butterworth band-stop filters, frequency selectivity is improved by approximately 25%; it allows flexible adjustment of suppression characteristics for each harmonic center frequency, enabling the system to adaptively suppress dynamic harmonic components in solar grid-connected environments.
Cascade Hybrid Architecture
The signal processing flow of the cascade hybrid filter structure is illustrated in the following diagram, depicting the three-stage cascade filtering architecture for high-precision signal reconstruction in solar inverters.
First, the collected raw signal is input to a 65th-order FIR low-pass filter designed with the Kaiser window function (β = 5), achieving strict linear phase preservation and preliminary suppression of high-frequency noise above 60 Hz through time-domain convolution operations. Then, the signal passes sequentially through three IIR band-stop filters targeting specific harmonic frequencies (150, 250, 350 Hz), each using an optimized second-order direct-form I structure (ρ = 0.95), achieving high-selectivity suppression of target harmonics through recursive calculations. Finally, through cyclic buffer management and zero-phase processing, the system minimizes boundary effects and compensates for phase distortion, outputting high-accuracy signals. A comparison of key performance parameters for the three filter types is shown in Table 3.
| Parameter | Total Harmonic Distortion (%) | Stopband Attenuation (dB) | Processing Delay Time (μs) | Fundamental Phase Retention (%) |
|---|---|---|---|---|
| FIR | 0.85 | 51.2 | 320 | 97.10 |
| IIR | 0.42 | 42.7 | 100 | 96.80 |
| FIR-IIR | 0.26 | 55.1 | 60 | 99.85 |
As shown in Table 3, the FIR-IIR structure reduces THD by 69.4% and 38.1% compared to single filters (FIR and IIR), indicating a superlinear gain effect in harmonic suppression for solar inverters. Through the combination of a front-end FIR and a back-end IIR efficient recursive structure, the processing delay time is reduced from 320 μs to 60 μs, verifying that the hybrid architecture achieves a Pareto optimal balance between algorithm complexity and filtering performance. The zero-phase processing algorithm effectively compensates for the nonlinear phase characteristics of IIR, resulting in a fundamental phase retention of 99.85% in the hybrid structure, overcoming the inherent limitations of traditional recursive structures in phase response. The synergistic optimization of the FIR-IIR hybrid cascade structure across all key metrics enables multi-dimensional accuracy improvement while maintaining high computational efficiency for solar inverter data.
System Hardware Design
Common IoT master MCU chips include IMX6ULL, Nordic, and TI. Compared to the others, IMX6ULL demonstrates significant advantages in data transmission, handling complex tasks, and high-demand applications for solar inverters. This chip operates at up to 800 MHz, integrates LCD controllers, CAN bus, I2C, SPI, and UART peripherals. In terms of power consumption, IMX6ULL implements dynamic voltage and frequency scaling (DVFS) and multiple low-power modes, balancing power consumption and performance in industrial control, human-machine interfaces, and IoT applications. For Linux system support, the IMX6ULL processor is fully supported by the Linux kernel, including key components such as device trees, power management, and peripheral drivers, reducing system development complexity. Moreover, IMX6ULL is fully compatible with PREEMPT_RT, reducing maximum system response latency from milliseconds to microseconds, meeting stringent timing requirements in industrial control for solar inverters. The overall structure of the main control circuit is depicted in the following topology diagram.
Data Acquisition Module
The data acquisition module collects current and voltage data from both the DC and AC sides of the solar inverter. In this study, the system uses metering chips HLW8110 and BL0942 to collect data from the DC input side and AC output side of the solar inverter, respectively. The acquisition flow is illustrated in the following node diagram.
The HLW8110 chip operates with a power consumption of less than 30 mW and can completely save cumulative energy data in power-off conditions. The BL0942 chip uses a patented single-wire UART communication protocol, integrating voltage, current, power, and energy measurement functions, with a sampling frequency of up to 8 kHz, effectively capturing fast load change characteristics. A comparison of various metering chip performances is shown in Table 4.
| Chip | Accuracy (%) | Power Consumption (mW) | Integration (%) | Data Refresh (kHz) | Operating Temperature (°C) | Unit Price ($) |
|---|---|---|---|---|---|---|
| HLW8110 | ±0.1 | 20 | 85 | 1 | -40 to +105 | 1.2 |
| BL0942 | ±0.2 | 25 | 80 | 1 | -40 to +85 | 1.5 |
| ATM90 | ±0.5 | 75 | 40 | 200 | -20 to +75 | 2.0 |
As shown in Table 4, chips HLW8110 and BL0942 are the optimal choices balancing accuracy, stability, power consumption, and cost, providing a reliable data acquisition foundation for the hybrid filter system in solar inverters.
The system uses a TFT-LCD module as the core human-machine interaction module, enabling real-time visualization of voltage and current parameters and alarm functions in emergencies. This display module, based on active matrix driving technology, achieves device lightweight design, significantly reduces power consumption indicators, and optimizes battery life for portable devices. Additionally, the module connects to the main controller via standard communication interfaces, supporting multiple data transmission formats.
Data Processing Module
The current and voltage data measured by the metering chips undergo ADC conversion, followed by FIR and IIR digital filters to eliminate noise and suppress harmonics, resulting in processed data. The data processing flow is illustrated in the following flowchart.
ADC Conversion Circuit
The ADC circuit, together with the FIR and IIR digital filters, forms the digital signal processing chain. This study selects the high-performance successive approximation analog-to-digital converter ADS7822, providing 12-bit accuracy while maintaining a high conversion rate of 200 kSPS, with integral nonlinearity error controlled within ±1 LSB.
Filter Implementation Circuit
The XC7A35T chip is used to implement the FIR and IIR digital filters. Its built-in 90 DSP48E1 slices provide efficient 25×18-bit multiplication operations with single-cycle multiply-accumulate characteristics; distributed RAM resources efficiently store filter coefficients and state variables, reducing external memory access latency. Additionally, this chip offers good stability and anti-interference capabilities, ensuring accurate data processing in complex environments for solar inverters.
The filter node schematic is depicted in the following diagram. The FIR filter adopts a transposed structure, where each tap coefficient is multiplied by the corresponding delayed input. Multiplier units implement 18×16-bit fixed-point multiplication operations; 16 multiplication results are accumulated through a 4-stage pipelined adder tree network, achieving high-throughput parallel computation. The circuit includes N-stage shift registers, N custom multipliers, N-1 adders, and control logic. Coefficient storage is achieved through distributed ROM, overcoming the storage challenges posed by the asymmetric characteristics of the Kaiser window. The IIR filter is based on the direct-form II canonical structure, forming a compact feedback loop design. The circuit core includes two state registers, five parallel multipliers, and multi-stage addition and subtraction units, constituting a complete second-order section.
Data Transmission Module
The data transmission module serves as a bridge for information transfer between various modules of the solar inverter and between hardware and the host computer. The data acquisition module connects to the solar inverter via the industrial bus interface RS485, reading real-time data such as voltage and current from monitoring nodes, then transmits the data to the data processing module via CAN, and finally packages the data using Transmission Control Protocol (TCP) for sending to the host computer. The transmission module framework is illustrated in the following diagram.
RS485 is a serial communication protocol suitable for long-distance communication, using differential signal transmission to reduce electromagnetic interference effects on signals and improve transmission signal stability. Its hardware circuit is shown in the following schematic.
CAN is a serial communication protocol specifically applied to real-time data communication, allowing multiple nodes to communicate on the same network without a central controller, where each node can be both a sender and a receiver. Moreover, CAN uses differential signal transmission, offering strong anti-interference capabilities, enhancing transmission stability for solar inverters.
System Software Design
Solar Inverter Data Acquisition Parameters
After node power-on, the system completes initialization tasks such as serial communication modules and timers. The HLW8110 current channel is set to differential mode (Config |= 0x0002), gain is adjusted to 2x (Gain |= 0x02), and the digital high-pass filter is turned off (CTRL_REG &= ~0x01). The BL0942 current channel is selected as the IA channel (IA_CHSEL = 0x01), gain is set to 2x (GAIN_CTRL = 0x02), and the high-pass filter is disabled via HPF_CTRL &= ~0x01. The timer triggers data acquisition tasks at a 1-second period, and the acquisition node reads data from the HLW8110 and BL0942 chip registers via the serial protocol for calculation and parsing. When the acquisition node sends instructions, the data transmission node generates an interrupt and sends the data stored in the temporary buffer to the host computer node for data processing.
Data Processing Node
FIR Filter Parameters
The core of implementing the Kaiser window (β=5) FIR filter lies in setting the Compiler IP core parameters. In the filter specification definition phase, Transpose is used for optimal area-speed trade-off, and the Reload option is enabled for dynamic coefficient update capability.
The order N is set to 31, and the parameter β is set to 5, ensuring good sidelobe suppression and moderate frequency resolution while maintaining low computational complexity. The input data width is set to 16 bits, coefficient width to 18 bits, and a fixed-point format with 16 fractional bits is adopted to ensure operational precision and numerical stability. By enabling DSP slices, utilizing hardware multiply-accumulate units, setting a 4-stage pipeline to enhance timing performance, and selecting the Transpose architecture for efficient data paths, the FIR filter is optimized for solar inverters. The parameter configuration flow is illustrated in the following flowchart.
IIR Filter Design
For implementing the second-order direct-form II structure IIR filter, the feedforward coefficients (b0, b1, b2) and feedback coefficients (a1, a2) are first uniformly quantized to Q2.16 fixed-point format, balancing computational accuracy with hardware resource constraints. Then, dual state registers w1 and w2 are used to store the previous two intermediate state values, constructing the basic direct-form II structure framework. Finally, a saturation logic function saturate is introduced into the state update path to ensure stable filter operation for solar inverters. The IIR configuration flowchart is depicted in the following diagram.
Data Transmission Node
The collected data, after processing by the FIR and IIR filters, yields high-accuracy voltage and current data. To enable data exchange between the data processing node and the host computer display end, an Ethernet connection with the TCP protocol is used to establish a bidirectional data transmission channel. The communication flow is illustrated in the following diagram.
First, the server (display interface) creates a socket via socket(), then executes bind() to bind the port, listen() to request connection listening, and accept() to accept connections. The client (data transmission module) creates a socket and directly calls connect() to initiate a connection request. After the connection is established, both parties exchange data using read() and write() functions.
The data received by the host computer display end is stored in the SQLite database. By analyzing historical data, the performance of each node is evaluated, thereby optimizing the operating parameters of the solar inverter and improving system operational efficiency and stability. The database storage data flow is illustrated in the following flowchart.
Qt Display Interface
Qt is a comprehensive cross-platform application development framework based on C++, widely used for graphical user interface (GUI) design and backend system integration. Architecturally, Qt employs a signal-slot event-driven mechanism, supporting loose coupling asynchronous communication between components, significantly enhancing system module scalability and maintainability. Its core functional components include a GUI rendering engine, network communication stack, multi-thread scheduler, and XML/JSON parser, meeting the development needs of complex systems for solar inverters. The acquisition display interface is shown in the following schematic.
System Testing
Real-Time Performance Testing
This study quantifies the optimization effects of the improved Linux kernel PREEMPT_RT based on a standard test environment, focusing on three key time-domain parameters: real-time response time, interrupt latency, and data transmission time. The test platform uses an x86_64 architecture processor, with a measurement thread at real-time priority (SCHED_FIFO, priority 90). During measurement, memory locking technology (mlockall option) is applied to eliminate random delays caused by memory paging. The experiment uses the hackbench tool to precisely control system load levels and the cyclictest tool to capture timing. Figure 1 shows a comparison of real-time response times under system loads from 0% to 100%.
To quantitatively analyze the impact of resource competition on real-time performance, system load levels are divided into five grades: light load (CPU utilization 10%–20%), medium load (30%–50%), heavy load (60%–75%), overload (80%–90%), and peak load (close to 100%), representing progressive increases in system resource competition intensity. Interrupt response time and data transmission time under different load levels are measured using the cyclictest tool, as shown in Figure 2 and Figure 3, respectively.
From the peak load data in Figures 1–3, real-time response time is reduced from a maximum of 14.5 ms to 6.2 ms, a decrease of 53.8%; interrupt latency is reduced from 55 μs to 28 μs, a reduction of 49.1%; total system delay is optimized from 7.5 ms to 3.5 ms, achieving a 53.3% improvement, with delay time less than 5 ms for solar inverters.
Accuracy Testing
Since the AC side of the solar inverter requires grid connection, accuracy analysis must compare against the standard 220 V AC voltage. Using a random sampling strategy with metering chips, 1000 sets of original current and voltage experimental data are collected. The raw data are processed using IIR, FIR, and FIR-IIR filters to obtain sample data. To reduce the impact of random errors, the grouped average method is used to process the sample data: the 1000 sets of sample data are evenly divided into 10 groups according to the time series, each containing 100 consecutive sampling points, and the arithmetic mean of each group is calculated as the representative value for that group. The results are shown in Table 5.
| Voltage (V) | Standard | IIR Filter | FIR Filter | Hybrid Filter |
|---|---|---|---|---|
| Measurement 1 | 220.0 | 224.05 | 210.23 | 218.75 |
| Measurement 2 | 220.0 | 226.05 | 232.10 | 219.45 |
| Measurement 3 | 220.0 | 228.70 | 232.10 | 222.20 |
| Measurement 4 | 220.0 | 225.06 | 232.10 | 221.65 |
| Measurement 5 | 220.0 | 218.40 | 232.90 | 219.45 |
| Measurement 6 | 220.0 | 227.70 | 208.23 | 221.10 |
| Measurement 7 | 220.0 | 224.05 | 231.00 | 218.90 |
| Measurement 8 | 220.0 | 218.95 | 231.00 | 219.45 |
| Measurement 9 | 220.0 | 218.40 | 208.23 | 218.35 |
| Measurement 10 | 220.0 | 217.85 | 208.23 | 217.80 |
| Mean | 220.0 | 226.05 | 223.68 | 221.67 |
From the data in Table 5, the data after IIR and FIR filtering show significant errors. In contrast, FIR-IIR filtering, through its cascade structure combining the linear phase characteristics of FIR and the high-frequency attenuation advantages of IIR, results in smaller errors and closer approximation to standard data for solar inverters. Current measurement data are shown in Table 6.
| Current (A) | Before Filtering | IIR Filter | FIR Filter | Hybrid Filter |
|---|---|---|---|---|
| Measurement 1 | 9.32 | 9.53 | 9.99 | 9.39 |
| Measurement 2 | 9.45 | 9.65 | 10.00 | 9.54 |
| Measurement 3 | 9.78 | 10.00 | 10.00 | 9.84 |
| Measurement 4 | 9.61 | 9.87 | 10.00 | 9.70 |
| Measurement 5 | 9.23 | 9.51 | 9.87 | 9.31 |
| Measurement 6 | 9.89 | 10.00 | 10.00 | 9.97 |
| Measurement 7 | 9.15 | 9.42 | 9.94 | 9.23 |
| Measurement 8 | 9.67 | 9.99 | 10.00 | 9.75 |
| Measurement 9 | 9.38 | 9.70 | 9.96 | 9.44 |
| Measurement 10 | 9.55 | 9.85 | 10.00 | 9.64 |
| Mean | 9.50 | 9.75 | 9.97 | 9.58 |
From Table 6, it can be seen that the current data after hybrid filter filtering have high restoration, and the collected information is more accurate for solar inverters. A comparison of the means and errors of measurement data under different filtering methods is shown in Table 7, where the error is the percentage of the difference between the collected data and the standard data divided by the standard data.
| Mean | Voltage (V) | Error (%) | Current (A) | Error (%) |
|---|---|---|---|---|
| Standard Data | 220.00 | — | 9.50 | — |
| IIR Filter | 226.05 | 2.75 | 9.75 | 2.63 |
| FIR Filter | 224.07 | 1.85 | 9.97 | 4.94 |
| Hybrid Filter | 221.67 | 0.76 | 9.58 | 0.84 |
The data in the table show that the hybrid filtering technology achieves voltage and current errors of 0.76% and 0.84%, respectively, successfully controlling voltage error within 0.8% and current error within 1% for solar inverters.
Conclusion
This research addresses the limitations of traditional solar inverter data acquisition systems in real-time performance and measurement accuracy by proposing an innovative solution that integrates Linux kernel real-time scheduling strategies with FIR-IIR collaborative filtering mechanisms. Experimental results demonstrate that modifying the PREEMPT_RT mechanism reduces system delay to 3.5 ms, and using the hybrid filter achieves a voltage error rate of 0.8% and a current error rate of 1%. This system can play a positive role in multiple areas. For example, in complex solar power plants with high-voltage and high-temperature areas, the system can monitor these parameters in real-time, avoiding equipment damage and personnel injury; photovoltaic array installations often involve safety risks such as high-altitude operations, and the system can help managers detect hidden dangers in advance through data anomalies. This method provides stable and reliable technical support for solar power generation systems and holds significant practical value for improving new energy utilization efficiency in solar inverters.