With the rapid expansion of renewable energy, solar inverters have become the critical interface between photovoltaic arrays and the power grid. The performance of these inverters directly affects grid stability and energy conversion efficiency. Our research reveals that when data acquisition delays exceed 5 ms, system energy conversion efficiency can drop by 2 to 3 percentage points. Moreover, a 0.5% degradation in sampling accuracy can worsen total harmonic distortion (THD) to 1.8 times the grid standard limit. Hence, a high-precision, real-time data acquisition system for solar inverters is urgently needed.
Traditional data acquisition systems for solar inverters often suffer from poor real-time performance, insufficient accuracy, and weak anti-interference capabilities. To address these issues, we propose a high-precision data acquisition system based on Linux real-time extension. The system adopts an adaptive real-time scheduling algorithm within the Linux kernel to enhance real-timeness. It employs analog-to-digital converters (ADCs) and digital filtering algorithms for data acquisition, and applies a hybrid filtering algorithm combining finite impulse response (FIR) and infinite impulse response (IIR) digital filters for data processing. Experimental results show that the system achieves voltage measurement accuracy of 0.8%, current measurement accuracy of 1%, and system response time below 5 ms.
1. Overall System Architecture
The system adopts a layered architecture consisting of four functional layers: the front-end acquisition layer, the Linux real-time system layer, the data processing layer, and the application layer. The overall framework is summarized in Table 1, which lists each layer and its primary responsibility.
| Layer | Function |
|---|---|
| Front-end acquisition | Uses HLW8110 and BL0942 metering chips for current/voltage sensing, 24-bit ADCs at 250 kHz |
| Linux real-time system | Adaptive PREEMPT_RT scheduling to reduce interrupt latency to <50 μs |
| Data processing | FIR-IIR cascaded filtering to suppress noise and harmonics |
| Application | Data storage (>30 days), display, remote communication with resume on break |
The front-end acquisition layer employs the HLW8110 and BL0942 chips to capture key parameters from the DC input and AC output of the solar inverter. Both chips feature 24-bit ADCs with sampling frequencies up to 250 kHz, enabling high-speed data capture. Input overvoltage protection and anti-interference design ensure stable operation under complex grid conditions.
The Linux real-time system layer, built upon an improved PREEMPT_RT scheduling mechanism, manages real-time task scheduling. By optimizing interrupt handling, interrupt latency is kept below 50 μs, ensuring continuous and lossless data flow.
The data processing layer implements a cascaded FIR-IIR filter architecture. FIR filters provide linear phase characteristics to avoid phase distortion, while IIR filters excel in suppressing high-frequency noise and harmonics. Together they improve data accuracy.
The application layer provides data storage, display, and control functions. It supports over 30 days of data retention, breakpoint resume, data compression, and self-healing link mechanisms for stable remote communication even under high data volume.
2. System Design Principles
2.1 Adaptive Real-Time Preemptive Scheduling Algorithm
PREEMPT_RT is a key technique for enhancing real-time performance in the Linux kernel. However, the standard version suffers from three main defects: systematic jitter due to full preemption, blocking caused by RCU write operations, and priority inversion chains from the priority inheritance protocol. Our adaptive real-time scheduling algorithm improves these aspects, as illustrated by the performance comparison in Table 2.
| Metric | Standard RT | Improved RT | Improvement (%) |
|---|---|---|---|
| Maximum scheduling delay (μs) | 152 | 89 | 41.4 |
| RCU write latency (μs) | 48 | 21 | 56.3 |
| Task switching frequency (s-1) | 12300 | 7150 | 41.9 |
| Priority inversion occurrence (%) | 2.1 | 0 | 100 |
The improvements include:
- Dynamic Preemption Threshold (DPT): A
dynamic_thresholdfield is added totask_struct. Preemption is triggered only when the requesting task’s priority exceeds the current task’s dynamic threshold, reducing unnecessary context switches. - RCU Latency Reduction: The
rcu_assign_pointerfunction is modified to detect real-time tasks viacurrent->flags & RT_FLAG. For real-time tasks, a fast path utilizing Intel TSX instructions is provided, slashing RCU write latency. - Chain Priority Inheritance Protocol (CPIP): A
chained_ownerfield is added tort_mutex, enabling the tracking of complete lock dependency chains. Thert_mutex_priofunction recursively propagates priority, eliminating priority inversion.
2.2 Hybrid Filter Design Principle
The AC output voltage of a solar inverter can be expressed as:
$$
v_{\text{ac}}(t) = V_1 \sin(2\pi f_1 t) + \sum_{h=3,5,7} V_h \sin(2\pi f_h t) + n_{\text{high}}(t)
$$
where \(f_1 = 50\) Hz is the fundamental frequency, \(f_h\) are odd harmonic frequencies (h=3,5,7), and \(n_{\text{high}}(t)\) represents high-frequency noise. Based on power quality standards, we define multi-dimensional filter performance targets: passband ripple ≤ 0.2 dB in the 45–55 Hz range, stopband attenuation ≥ 40 dB, and suppression of components above 1 kHz by ≥ 50 dB.
FIR Filter with Kaiser Window
A 65th-order FIR low-pass filter using a Kaiser window (β=5) is designed. Its impulse response is:
$$
h_{\text{FIR}}(n) = \frac{\sin(2\pi f_c (n-M))}{\pi (n-M)} \cdot w(n), \quad f_c=60\text{ Hz},\; M=32
$$
Comparison of FIR filters with different window functions is given in Table 3.
| Window | Passband ripple (dB) | Stopband attenuation (dB) | Group delay variation |
|---|---|---|---|
| Kaiser (β=5) | 0.18 | 51.2 | 0.0 |
| Blackman | 0.21 | 42.1 | 0.5 |
| Rectangular | 0.25 | 40.5 | 1.0 |
The Kaiser window reduces passband ripple by ~14% compared to the rectangular window, improves stopband attenuation by 8–10 dB, and achieves zero group delay variation, ensuring perfect linear phase.
IIR Notch Filters for Harmonic Suppression
For specific harmonics (150, 250, 350 Hz), a second-order direct-form II notch filter bank is employed. The transfer function of each unit is:
$$
H_{\text{IIR},h}(z) = \frac{1 – 2\cos(\omega_h)z^{-1} + z^{-2}}{1 – 2\rho\cos(\omega_h)z^{-1} + \rho^2 z^{-2}}
$$
where \(\omega_h\) is the normalized angular frequency, and \(\rho = 0.95\) controls the pole radius. This design provides ~25% better frequency selectivity than traditional Butterworth notch filters, allowing adaptive suppression of dynamic harmonic components in the solar inverter environment.
Cascaded FIR-IIR Architecture
The hybrid filter processes signals in three stages: first, a Kaiser-window FIR (65th order) removes high-frequency noise while preserving linear phase; second, three IIR notch filters sequentially suppress 150, 250, and 350 Hz harmonics; third, zero-phase processing compensates for any remaining phase distortion. The performance comparison among FIR, IIR, and FIR-IIR is shown in Table 4.
| Parameter | FIR | IIR | FIR-IIR |
|---|---|---|---|
| Total Harmonic Distortion (%) | 0.85 | 0.42 | 0.26 |
| Stopband attenuation (dB) | 51.2 | 42.7 | 55.1 |
| Processing delay (μs) | 320 | 100 | 60 |
| Fundamental phase preservation (%) | 97.10 | 96.80 | 99.85 |
The FIR-IIR cascaded structure reduces THD by 69.4% compared to FIR alone and 38.1% compared to IIR alone, while cutting processing delay from 320 μs to 60 μs. The zero-phase post-processing ensures 99.85% phase preservation, overcoming the inherent nonlinear phase limitation of recursive IIR filters.
3. Hardware Design
The main controller is the i.MX6ULL processor, operating at up to 800 MHz with comprehensive peripheral support (LCD, CAN, I2C, SPI, UART). It supports DVFS and multiple low-power modes, and is fully compatible with PREEMPT_RT, reducing maximum response latency from milliseconds to microseconds.
Figure 1: Solar inverter hardware setup for data acquisition testing (illustrative).
3.1 Data Acquisition Module
The acquisition module collects current and voltage from both DC input and AC output of the solar inverter. HLW8110 is used for the DC side and BL0942 for the AC side. Their key specifications are compared in Table 5.
| Chip | Accuracy (%) | Power consumption (mW) | Integration (%) | Data refresh (kHz) | Operating temp (°C) | Unit price ($) |
|---|---|---|---|---|---|---|
| HLW8110 | ±0.1 | 20 | 85 | 1 | -40~+105 | 1.2 |
| BL0942 | ±0.2 | 25 | 80 | 1 | -40~+85 | 1.5 |
| ATM90 | ±0.5 | 75 | 40 | 200 | -20~+75 | 2.0 |
HLW8110 and BL0942 offer the best balance of accuracy, stability, power efficiency, and cost for the hybrid filtering system.
3.2 Data Processing Module
The analog signals from the metering chips are digitized by a 12-bit successive approximation ADC (ADS7822) at 200 kSPS with ±1 LSB INL. Digital filtering is implemented on an XC7A35T FPGA, which provides 90 DSP48E1 slices for 25×18-bit multiply-accumulate operations in a single cycle. The FIR filter uses a transposed structure with 16 taps, 4-stage pipelined adder tree, and distributed ROM for coefficient storage. The IIR filter employs a direct-form II transposed architecture with two state registers, five parallel multipliers, and saturation logic for stability.
3.3 Data Transmission Module
Data transmission uses an RS485 bus for long-distance communication from the acquisition module to the solar inverter monitoring nodes, CAN bus for intra-system data transfer, and Ethernet TCP for uplink to the host computer. RS485 employs differential signaling to reduce electromagnetic interference, while CAN provides multi-node, collision-free communication with strong noise immunity.
4. Software Design
4.1 Data Acquisition Parameters for Solar Inverter
Upon power-up, the system initializes serial ports and timers. The HLW8110 is configured: current channel differential mode (Config|=0x0002), gain 2x (Gain|=0x02), digital HPF disabled (CTRL_REG&=~0x01). The BL0942 selects IA channel (IA_CHSEL=0x01), gain 2x (GAIN_CTRL=0x02), HPF disabled (HPF_CTRL&=~0x01). Data are read every second via UART and parsed.
4.2 Data Processing Node
FIR Filter Configuration
The FIR filter uses Compiler IP core with Kaiser window (β=5), 31 taps, 16-bit input, 18-bit coefficients, 16-bit fractional format. Transpose architecture is selected for speed-area tradeoff, with reload enabled for dynamic coefficient updates. DSP slices are used with 4 pipeline stages.
IIR Filter Configuration
For each second-order notch filter, feedforward coefficients (b0,b1,b2) and feedback coefficients (a1,a2) are quantized to Q2.16 fixed-point format. Two state registers w1, w2 store intermediate values. Saturation logic prevents overflow.
4.3 Data Transmission Node
After filtering, the processed data are transmitted to the host display via TCP sockets. The server (display side) creates a socket, binds, listens, and accepts connections. The client (transmission module) connects and exchanges data using read/write. Received data are stored in an SQLite database for historical analysis, enabling performance optimization of solar inverter operating parameters.
4.4 Qt Display Interface
The user interface is developed with Qt, using signal-slot mechanism for asynchronous communication. It displays real-time voltage, current, power, and energy values from the solar inverter, along with alerts for abnormal conditions.
5. System Testing
5.1 Real-Time Performance Test
Tests were performed on an x86_64 platform with SCHED_FIFO priority 90 and memory locking (mlockall) to eliminate page faults. System load was controlled by hackbench, and latency measured by cyclictest. Table 6 shows the average response time under various loads, Table 7 provides interrupt latency, and Table 8 presents data transmission time.
| Load level | Standard RT | Improved RT | Reduction (%) |
|---|---|---|---|
| Light (10–20%) | 1.2 | 0.8 | 33.3 |
| Medium (30–50%) | 3.5 | 2.1 | 40.0 |
| Heavy (60–75%) | 7.8 | 4.5 | 42.3 |
| Very heavy (80–90%) | 11.2 | 5.8 | 48.2 |
| Peak (~100%) | 14.5 | 6.2 | 57.2 |
| Load | Standard RT | Improved RT | Reduction (%) |
|---|---|---|---|
| Light | 18 | 10 | 44.4 |
| Medium | 28 | 16 | 42.9 |
| Heavy | 40 | 22 | 45.0 |
| Very heavy | 48 | 25 | 47.9 |
| Peak | 55 | 28 | 49.1 |
| Load | Standard RT | Improved RT | Reduction (%) |
|---|---|---|---|
| Light | 0.8 | 0.5 | 37.5 |
| Medium | 2.1 | 1.2 | 42.9 |
| Heavy | 4.5 | 2.5 | 44.4 |
| Very heavy | 6.2 | 3.2 | 48.4 |
| Peak | 7.5 | 3.5 | 53.3 |
Under peak load, the response time dropped from 14.5 ms to 6.2 ms, interrupt latency from 55 μs to 28 μs, and total transmission delay from 7.5 ms to 3.5 ms—all well within the required 5 ms threshold.
5.2 Accuracy Test
We compared the system’s voltage and current measurements against a calibrated 220 V AC standard and a 9.50 A reference current. 1000 raw samples were collected and processed through FIR, IIR, and FIR-IIR filters. The results were averaged over 10 groups of 100 samples each. Table 9 shows voltage measurements, Table 10 current measurements, and Table 11 summarizes errors.
| Group | IIR filtered (V) | FIR filtered (V) | FIR-IIR filtered (V) |
|---|---|---|---|
| 1 | 224.05 | 210.23 | 218.75 |
| 2 | 226.05 | 232.10 | 219.45 |
| 3 | 228.70 | 232.10 | 222.20 |
| 4 | 225.06 | 232.10 | 221.65 |
| 5 | 218.40 | 232.90 | 219.45 |
| 6 | 227.70 | 208.23 | 221.10 |
| 7 | 224.05 | 231.00 | 218.90 |
| 8 | 218.95 | 231.00 | 219.45 |
| 9 | 218.40 | 208.23 | 218.35 |
| 10 | 217.85 | 208.23 | 217.80 |
| Mean | 226.05 | 223.68 | 221.67 |
| Error (%) | 2.75 | 1.85 | 0.76 |
| Group | Raw (A) | IIR (A) | FIR (A) | FIR-IIR (A) |
|---|---|---|---|---|
| 1 | 9.32 | 9.53 | 9.99 | 9.39 |
| 2 | 9.45 | 9.65 | 10.00 | 9.54 |
| 3 | 9.78 | 10.00 | 10.00 | 9.84 |
| 4 | 9.61 | 9.87 | 10.00 | 9.70 |
| 5 | 9.23 | 9.51 | 9.87 | 9.31 |
| 6 | 9.89 | 10.00 | 10.00 | 9.97 |
| 7 | 9.15 | 9.42 | 9.94 | 9.23 |
| 8 | 9.67 | 9.99 | 10.00 | 9.75 |
| 9 | 9.38 | 9.70 | 9.96 | 9.44 |
| 10 | 9.55 | 9.85 | 10.00 | 9.64 |
| Mean | 9.50 | 9.75 | 9.97 | 9.58 |
| Error (%) | — | 2.63 | 4.94 | 0.84 |
| Filter type | Voltage error (%) | Current error (%) |
|---|---|---|
| IIR only | 2.75 | 2.63 |
| FIR only | 1.85 | 4.94 |
| FIR-IIR hybrid | 0.76 | 0.84 |
The hybrid filter reduces voltage error to 0.76% (within 0.8%) and current error to 0.84% (within 1%), demonstrating a significant improvement over standalone filters.
6. Conclusion
We have designed and implemented a high-precision data acquisition system for solar inverters based on Linux real-time extension. By improving the PREEMPT_RT mechanism, the system achieves a maximum response delay of 3.5 ms under peak load. The cascaded FIR-IIR hybrid filter enables voltage measurement accuracy of 0.8% and current measurement accuracy of 1%. The system reliably monitors key parameters of solar inverters in real-time, providing a robust solution for enhancing energy conversion efficiency and grid stability. Its applications extend to safety monitoring in high-voltage/high-temperature zones of photovoltaic plants, early fault detection, and prevention of hazards in elevated installations. This work offers a stable and practical technical support for the utilization of solar energy.