The transition towards sustainable energy systems has placed solar power at the forefront, with photovoltaic (PV) installations becoming ubiquitous. At the heart of these systems lie the solar inverters, responsible for converting the DC power generated by PV panels into grid-compatible AC power. Among the various topologies, transformerless solar inverters have gained significant traction due to their superior efficiency, reduced size, and lower cost compared to their galvanically isolated counterparts. However, the absence of a transformer introduces a critical challenge: the potential for significant ground leakage currents. These currents pose serious safety risks, including electric shock hazards and potential damage to equipment, necessitating strict compliance with international standards such as VDE 0126-1-1 and IEC 62109.
My analysis focuses on understanding the complex nature of these leakage currents, particularly in prevalent topologies like the single-phase Boost+HERIC configuration, and developing a robust detection methodology. The core issue stems from the parasitic capacitive coupling between the PV array and the ground, represented by capacitors \(C_{pv+}\) and \(C_{pv-}\), and the intentional or unintentional resistive paths, \(R_{pv+}\) and \(R_{pv-}\). In transformerless solar inverters, the bridge’s switching actions generate a high-frequency common-mode voltage (\(V_{CM}\)) across these impedances, driving the leakage current (\(I_{CM}\)).
The mechanism is highly dependent on the inverter’s operational mode. During the active power transfer phase, the common-mode circuit includes the filter inductors (\(L_l, L_n\)) and the PV capacitance \(C_{pv} = C_{pv+} || C_{pv-}\), leading to a lower resonant frequency:
$$f_1 = \frac{1}{2\pi \sqrt{(L_l || L_n) \cdot C_{pv}}}$$
Conversely, during the freewheeling phase, the circuit topology changes dramatically. The PV capacitance now forms a resonant tank with the much smaller parasitic switch capacitances \(C_s = C_1 || C_2 || C_3 || C_4\) and the filter inductors, resulting in a much higher, problematic resonant frequency:
$$f_2 = \frac{1}{2\pi \sqrt{(L_l || L_n) \cdot \frac{C_{pv} \cdot C_s}{C_{pv} + C_s}}}$$
This high-frequency oscillation, combined with the pulsed charging/discharging of \(C_{pv}\) during switching transitions, imbues the leakage current with rich harmonic content. The total leakage current \(I_{CM}\) is a superposition of a resistive component \(I_R\) and a capacitive component \(I_C\):
$$I_{CM} = I_R + I_C$$
The characteristics of these components are fundamentally different. The capacitive current \(I_C\) is predominantly high-frequency, peaking around the zero-crossings of the grid voltage and containing significant energy at the switching frequency and its harmonics. The resistive current \(I_R\), which represents a genuine safety hazard like a person touching a PV terminal, is primarily composed of low-frequency components. An approximate expression for the dominant part of \(I_R\) when a resistive path \(R_{pv}\) exists is:
$$I_R \approx \frac{V_{bus} – 2V_{pv}}{2R_{pv}} + \frac{V_{grid}}{R_{pv}}$$
This shows its main constituents are a DC offset and a fundamental (50/60 Hz) component in phase with the grid voltage \(V_{grid}\).
The standard approach to leakage current protection in solar inverters involves measuring the sum current in the protective earth (PE) conductor using a current transformer. However, this method faces severe limitations in the context of transformerless solar inverters:
| Limitation | Description | Consequence |
|---|---|---|
| Limited Sensor Bandwidth | Typical leakage current sensors have a bandwidth of ~8 kHz for accuracy and cost. | Severe attenuation and phase distortion of high-frequency (>8 kHz) capacitive current components. |
| Anti-Aliasing Filtering | Signal conditioning circuits use low-pass filters (~5 kHz) to prevent aliasing in the ADC. | Further attenuation of high-frequency signals before digitization. |
| Low Sampling Rate | Microcontroller ADCs often sample at rates like 16 kHz for system-level control. | Inadequate to reconstruct high-frequency components, leading to aliasing and inaccurate RMS calculation. |
| Signal Overlap | The small, hazardous resistive current is buried within the large, oscillatory capacitive current. | Impossible to reliably detect small changes in \(I_R\) (e.g., 30-60 mA) by simply observing the distorted \(I_{CM}\) signal. |
As shown in the table, the conventional measurement chain is fundamentally mismatched to the signal’s nature. The sampled signal \(I_{CM}[n]\) is a highly distorted version of the true current, making reliable protection against both continuous and sudden (touch) resistive faults challenging. Simply increasing hardware specifications (sensor bandwidth, sampling rate) is a costly and often impractical solution.
The proposed method is predicated on a harmonic extraction technique that exploits the distinct spectral and phase characteristics of \(I_R\) and \(I_C\). The goal is to algorithmically separate these components from the single, distorted measurement of \(I_{CM}\).
The fundamental resistive current is in-phase with the grid voltage. The fundamental capacitive current leads the grid voltage by approximately 90 degrees due to the dominant capacitive impedance. We can construct a reference signal \(V_{ac}\) synchronized with the grid voltage:
$$V_{ac} = \sqrt{2} \sin(\omega t)$$
where \(\omega\) is the grid angular frequency. The key calculations proceed as follows:
- Extract DC Component (Resistive Bias): The DC offset of the leakage current corresponds to the primary part of the resistive current arising from the imbalance \(V_{bus} – 2V_{pv}\). It is found by averaging over an integer number of grid cycles (\(P\) samples):
$$M_{R0} = \frac{1}{P} \sum_{k=1}^{P} I_{CM}[k]$$ - Extract Fundamental In-Phase Component (Resistive AC): The amplitude of the resistive current’s fundamental component is extracted by a synchronous demodulation (multiplication and averaging):
$$M_{R1} = \frac{2}{P} \sum_{k=1}^{P} I_{CM}[k] \cdot V_{ac}[k]$$ - Calculate Approximate Resistive Current RMS: The RMS value of the dominant part of the resistive leakage current can be approximated from the extracted components:
$$I_{R\_RMS} \approx \sqrt{M_{R0}^2 + \frac{M_{R1}^2}{2}}$$ - Calculate Capacitive Current RMS: The RMS of the total measured leakage current \(I_{CM\_RMS}\) is computed conventionally. The capacitive current’s RMS value is then derived:
$$I_{C\_RMS} = \sqrt{I_{CM\_RMS}^2 – I_{R\_RMS}^2}$$
This method effectively “demodulates” the resistive current from the noisy, distorted composite signal. A crucial final step is the compensation of the capacitive current reading. Since \(I_C\) is heavily attenuated by the hardware, the calculated \(I_{C\_RMS}\) is too low. Based on pre-characterized lab data, a non-linear correction function or piecewise linear scaling is applied to \(I_{C\_RMS}\) to obtain a more accurate estimate.
The protection logic for transformerless solar inverters can now be made robust:
- Continuous Leakage Protection: Compare the accurately extracted \(I_{R\_RMS}\) and the compensated \(I_{C\_RMS}\) against their respective safety thresholds (e.g., 300 mA).
- Sudden Leakage Protection: Monitor the extracted \(I_{R\_RMS}\) for abrupt changes. A sudden increase exceeding a threshold (e.g., 30 mA) while the inverter is operating indicates a hazardous resistive touch event, triggering a fast shutdown within the mandated time (e.g., 300 ms for 30 mA).
To validate the analysis and the proposed method, a simulation model and a 5 kW hardware prototype of a Boost+HERIC transformerless solar inverter were developed. The simulations clearly demonstrated the theoretical waveforms: pure capacitive leakage current with high-frequency ringing, pure resistive current with a low-frequency signature, and their combination. Most importantly, they showed that direct sampling of a high-frequency capacitive current leads to severe distortion, while the harmonic extraction method accurately isolated an applied step change in resistive current.
Experimental results on the prototype confirmed the practical challenges and the efficacy of the solution. The measured waveforms aligned with the theoretical and simulation predictions. The key performance validation is summarized in the following table, which compares the detection of a sudden resistive fault superimposed on a background capacitive leakage:
| Parameter | Before Fault | After Fault (Actual) | Fault Current (Actual) | Fault Detected by Harmonic Extraction | Conventional RMS Comparison Error |
|---|---|---|---|---|---|
| Test Case 1 | 0 mA | 56.2 mA | 56.2 mA | 51 mA | ~9 mA (grossly inaccurate) |
| Test Case 2 | 0 mA | 80.7 mA | 80.7 mA | 75 mA | ~9 mA (grossly inaccurate) |
The table demonstrates that while the total measured leakage current RMS value changed only marginally (making conventional detection unreliable), the harmonic extraction method successfully identified the significant step in the resistive component, enabling reliable protection. The prototype equipped with this algorithm successfully passed all requisite tests for continuous and sudden leakage current protection per relevant standards, without nuisance tripping.
The harmonic extraction method is not limited to the HERIC topology. It is applicable to any transformerless solar inverter topology where the hazardous resistive leakage current manifests as low-frequency components (DC, fundamental, or low-order harmonics) that are spectrally or phase-separable from the predominant high-frequency common-mode noise. For three-phase transformerless solar inverters, the principle remains valid. The resistive leakage current in a balanced three-phase system primarily contains a DC component and a 3rd harmonic component. A similar approach can be derived, constructing reference signals at the third harmonic to extract this component accurately from the total noisy leakage current.
Implementing this method in practical solar inverters requires careful consideration. Accurate grid synchronization (phase-locked loop) is essential. The averaging period \(P\) must cover an integer number of grid cycles to reject periodic interference. The compensation coefficients for the capacitive current are empirical and should be calibrated based on the specific hardware platform (sensor, filter characteristics). The computational load is minimal, involving mainly multiplications, additions, and a square root operation, which is easily handled by modern digital signal controllers used in solar inverters.
In conclusion, the problem of leakage current detection in transformerless solar inverters is fundamentally a signal processing challenge created by hardware limitations. By moving beyond simple RMS measurement and employing a model-based harmonic extraction technique, it is possible to accurately separate the hazardous resistive leakage current from the benign but large capacitive displacement current. This software-centric solution enhances safety and reliability without necessitating expensive hardware upgrades, fulfilling stringent international standards and facilitating the wider, safer adoption of high-efficiency transformerless solar inverters in the global photovoltaic market.