The widespread integration of renewable energy sources has propelled the battery energy storage system (BESS) to a central role in modern power grids. Its capabilities for energy shifting, frequency regulation, and enhancing grid stability are indispensable. As these systems scale towards higher voltages and larger capacities to improve efficiency and economy, ensuring their operational safety and long-term reliability becomes paramount. A critical, yet often underexplored, aspect of this reliability is the electrical interaction between the battery system and ground.
In a typical battery energy storage system installation, the metallic enclosures, racks, and frames housing the battery modules, management electronics, and cooling apparatus are directly connected to earth ground for safety. However, inherent parasitic capacitances exist between the live electrical parts (like the battery poles, busbars, and modules) and this grounded structure. These capacitances, though small in value (typically in the nanofarad to microfarad range), create a conductive path for high-frequency electrical noise. The primary source of this noise is the Power Conversion System (PCS), which uses high-frequency Pulse Width Modulation (PWM) to manage power flow between the DC battery and the AC grid. This switching action inherently generates a Common-Mode Voltage (CMV).
This CMV is a zero-sequence voltage that appears equally on all phase outputs of the PCS with respect to ground. Through the grounding network, this voltage can propagate into the DC side and impress itself across the parasitic capacitances of the battery energy storage system. This phenomenon has two direct and potentially detrimental consequences:
- Polar Voltage Fluctuation: The CMV superimposes on the DC voltage of the positive and negative battery poles relative to ground. This causes the “pole-to-ground” voltage to experience high-frequency, high-amplitude swings (high dv/dt), far exceeding the steady-state DC level.
- Common-Mode Current (CMC): The fluctuating CMV drives displacement currents through the parasitic capacitances to ground, resulting in a circulating common-mode current loop.
These effects are not merely theoretical. Sustained high dv/dt stresses can accelerate insulation aging within battery modules and connected equipment. Significant CMC can interfere with the sensitive measurements of the Battery Management System (BMS), leading to potential faults or inaccurate state estimations. Therefore, a thorough analysis of the characteristics and influencing factors of these ground-related voltages and currents is crucial for the robust design and safe operation of large-scale battery energy storage system infrastructure.
Mechanism of Common-Mode Voltage Intrusion into the Battery System
The generation of CMV is fundamentally tied to the operation of the voltage-source converter topologies used in PCS units, such as two-level or three-level Neutral Point Clamped (NPC) / Active NPC inverters. Under PWM control, the switching states of the semiconductor devices (IGBTs, MOSFETs) create pulsed phase voltages. The common-mode voltage, \(u_{cm}\), is mathematically defined as the average of these three-phase output voltages with respect to the DC-link midpoint (or a virtual ground point):
$$u_{cm} = \frac{u_{ao} + u_{bo} + u_{co}}{3}$$
where \(u_{ao}, u_{bo}, u_{co}\) are the inverter phase output voltages.
For a three-level inverter using Sine-PWM (SPWM), the combination of three 120°-shifted modulation waves with two triangular carrier waves produces phase voltage pulses at multiple levels (e.g., \(+V_{dc}/2\), \(0\), \(-V_{dc}/2\)). The arithmetic sum and averaging of these three pulsed waveforms result in a staircase-like CMV waveform. The magnitude of this \(u_{cm}\) can theoretically reach up to half of the DC-link voltage (\( \pm V_{dc}/2 \)), making it a significant high-frequency voltage source.
This CMV source is present at the AC terminals of the PCS. Since the AC grid neutral is typically grounded, and the PCS chassis/DC-link capacitors may also have grounding connections, a path exists for \(u_{cm}\) to couple into the grounding system. Crucially, the battery energy storage system rack is directly grounded. The parasitic capacitances \(C_{v1}\) (between positive pole and ground) and \(C_{v2}\) (between negative pole and ground) within the battery cluster complete the conduction path, allowing \(u_{cm}\) to intrude onto the DC bus. This establishes the mechanism by which the high-frequency PWM noise from the PCS directly impacts the internal electrical environment of the battery energy storage system.
Common-Mode Equivalent Circuit Modeling for Battery Energy Storage Systems
To quantitatively analyze the propagation and impact of CMV, a dedicated common-mode equivalent circuit model for the battery energy storage system is essential. This model focuses on the zero-sequence components and the paths to ground.
Starting from a system model that includes the PCS, an LCL filter, the grid, the DC-link, and the parasitic capacitances \(C_{v1}\) and \(C_{v2}\) of the battery system, a simplified common-mode loop can be derived using circuit theory. The key components in this loop are:
- The CMV source, \(u_{cm}\), from the PCS.
- The equivalent impedance of the grounding path between the AC and DC systems, \(Z_g = R_g + sL_g\).
- The line resistance \(R_0\) and filter inductances \(L_f\), \(L_0\).
- The combined parasitic capacitance of the battery energy storage system, \(C_v = C_{v1} + C_{v2}\).
By applying Kirchhoff’s laws and assuming a symmetrical three-phase system, the common-mode current \(i_{cm}\) can be shown to be the sum of the currents through \(C_{v1}\) and \(C_{v2}\). The voltage from the grid neutral (N) to the DC-link midpoint (o), \(u_{No}\), provides the link. After simplification and neglecting the small differential-mode voltage component from DC-link capacitor imbalance, the core common-mode circuit reduces to a classic series RLC second-order circuit driven by the voltage source \(u_{cm}\), where:
$$R = R_g + \frac{R_0}{3}, \quad L = \frac{L_f}{3}, \quad C = C_{v1} + C_{v2}$$
The voltage across the capacitor \(C\) in this model, \(u_{cmv}\), represents the common-mode voltage that appears on the battery poles relative to ground.
From this model, two critical transfer functions can be derived:
- The transfer function from the PCS CMV (\(u_{cm}\)) to the battery pole CMV (\(u_{cmv}\)):
$$H_1(s) = \frac{U_{cmv}(s)}{U_{cm}(s)} = \frac{1}{ (R_g + \frac{R_0}{3})(C_{v1}+C_{v2})s + \frac{L_f}{3}(C_{v1}+C_{v2})s^2 + 1 }$$ - The transfer function from \(u_{cm}\) to the total battery system common-mode current (\(i_{cm}\)):
$$H_2(s) = \frac{I_{cm}(s)}{U_{cm}(s)} = \frac{(C_{v1}+C_{v2})s}{ (R_g + \frac{R_0}{3})(C_{v1}+C_{v2})s + \frac{L_f}{3}(C_{v1}+C_{v2})s^2 + 1 }$$
These transfer functions form the basis for analyzing the frequency-domain characteristics and the dynamic response of the system to the switching noise.
Quantitative Analysis of Characteristics and Key Influencing Factors
Dynamic Response and Peak Values
Analyzing the response to a step change in \(u_{cm}\) (simplifying the PWM pulses) provides insight into the worst-case transient overvoltage and current peaks experienced by the battery energy storage system. The derived second-order RLC model is typically under-damped (\(0 < \zeta < 1\)). Solving the time-domain equations yields approximate peak values:
- Peak Pole-to-Ground CMV: \(u_{cmv\_max} \approx 1.025 \cdot u_{cm\_max}\). This indicates that the transient voltage stress on the battery system insulation can slightly exceed the raw CMV generated by the PCS.
- Peak Common-Mode Current: \(i_{cm\_max} \approx 0.4 \cdot (C_{v1}+C_{v2}) \cdot u_{cm\_max}\). The CMC is directly proportional to the total parasitic capacitance and the CMV magnitude, typically reaching amplitudes of several Amperes in practical systems.
Steady-State Frequency-Domain Characteristics
In steady-state, the spectral content of the voltages and currents is vital. The battery pole-to-ground voltage consists of a DC component (half the DC-link voltage) plus AC components induced by \(u_{cm}\). The expressions in the frequency domain are:
$$U_{cmv}(\omega) = \frac{U_{cm}(\omega)}{ \sqrt{ (1 – \omega^2 L C)^2 + (\omega R C)^2 } }$$
$$I_{cm}(\omega) = \frac{U_{cm}(\omega)}{ \sqrt{ R^2 + (\omega L – \frac{1}{\omega C})^2 } }$$
The spectral signature of \(u_{cm}\) itself is determined by the PWM scheme. It primarily contains a DC offset and dominant harmonic clusters centered at odd multiples of the switching frequency (\(f_{sw}\), \(3f_{sw}\), \(5f_{sw}\), etc.). Therefore, the disturbing voltage and current in the battery energy storage system will exhibit these same characteristic frequency bands.
Analysis of Key Influencing Factors
The derived models clearly show that several factors govern the severity of the CMV and CMC in the battery energy storage system.
1. Parasitic Capacitance (\(C_v = C_{v1}+C_{v2}\)):
This is a primary design-dependent parameter of the battery cluster.
- Effect on CMV: From the transfer function \(H_1(s)\) and the voltage divider effect in the RLC circuit, the magnitude of \(u_{cmv}\) is inversely related to \(C_v\). A larger parasitic capacitance acts as a stronger sink for the high-frequency CMV, reducing the voltage developed across it (i.e., lower pole-to-ground voltage swing).
- Effect on CMC: Conversely, the common-mode current \(i_{cm}\) is directly proportional to \(C_v\), as indicated by \(H_2(s)\) and the relation \(i_{cm} = C_v \cdot \frac{du_{cmv}}{dt}\). A larger capacitance provides a lower impedance path to ground for the high-frequency voltage, resulting in larger displacement currents.
This presents a design trade-off: minimizing \(C_v\) reduces leakage current but increases insulation voltage stress, and vice-versa.
2. Switching Frequency (\(f_{sw}\)):
The frequency of the PWM carrier wave directly sets the central frequency of the main CMV harmonic cluster.
- The impedance of the parasitic capacitor \(Z_C = 1 / (j\omega C_v)\) decreases with increasing frequency. Therefore, at higher \(f_{sw}\), the CMV attenuation might be less effective, but the dominant harmonics are at a higher frequency where filter inductances present higher impedance.
- The overall impact is evaluated through the frequency response of \(H_1(j\omega)\) and \(H_2(j\omega)\). There is usually a resonant frequency \(\omega_r = 1/\sqrt{LC}\) for the common-mode loop. If the switching frequency or its harmonics are close to \(\omega_r\), severe amplification of both CMV and CMC can occur.
3. PCS Topology and Modulation Strategy:
The magnitude and waveform of the source \(u_{cm}\) itself depend on the converter topology (2-level vs. 3-level) and the modulation algorithm (SPWM, SVPWM, DPWM). Advanced modulation strategies specifically designed to reduce CMV (e.g., near-state PWM, active zero-state clamping) can be highly effective in mitigating the problem at its source for the battery energy storage system.
4. Grounding Impedance (\(Z_g\)):
The resistance and inductance of the path connecting different ground points (AC neutral, PCS chassis, battery rack) form \(Z_g\). A lower impedance provides a more defined path for the common-mode current, which can sometimes help in diverting it away from sensitive parts, but it also affects the damping and resonant characteristics of the entire loop.
The following table summarizes the influence of the primary factors:
| Influencing Factor | Effect on Pole-to-Ground CMV (\(u_{cmv}\)) | Effect on Common-Mode Current (\(i_{cm}\)) | Remarks |
|---|---|---|---|
| Parasitic Capacitance (\(C_v\)) ↑ | Amplitude ↓ | Amplitude ↑ | Primary design trade-off in battery pack layout and insulation. |
| Switching Frequency (\(f_{sw}\)) ↑ | Frequency response dependent; risk of resonance. | Frequency response dependent; risk of resonance. | Requires careful evaluation relative to common-mode loop resonance. |
| PCS CMV Magnitude (\(u_{cm}\)) ↑ | Proportional ↑ | Proportional ↑ | Controlled by PCS topology and modulation strategy choice. |
| Grounding Impedance (\(Z_g\)) ↑ | Generally ↑ (due to poorer drainage) | Generally ↓ (due to higher loop impedance) | Affects overall damping and potential for ground potential rise. |
Simulation and Experimental Validation
Theoretical analysis is validated through simulation and experiment. A simulation model of a 100 kW battery energy storage system with a three-level ANPC PCS and SVPWM control can be built. External capacitors are added to the DC bus to represent the parasitic capacitances \(C_{v1}\) and \(C_{v2}\).
Key Findings from Simulation/Experiment:
- Waveform Verification: Measured pole-to-ground voltages show high-frequency oscillations with peak values significantly exceeding the DC bus voltage (e.g., +900V on the positive pole, -880V on the negative pole for a 1100V DC system), with very high dv/dt (e.g., >1 MV/s). The common-mode current waveforms show pulsed currents with amplitudes of several Amperes (e.g., 5-16 A).
- Parasitic Capacitance Influence: Experimental sweeps of \(C_v\) confirm the theoretical relationship. As \(C_v\) increases from a few nF to hundreds of nF, the peak pole-to-ground voltage decreases monotonically, while the peak common-mode current increases. The data can be plotted to illustrate this clear trade-off.
- Frequency Spectrum: Spectral analysis of the pole-to-ground voltage confirms the dominant frequency components are at the switching frequency \(f_{sw}\) and its odd multiples (3\(f_{sw}\), 5\(f_{sw}\)), with amplitudes decaying at higher harmonics, aligning perfectly with the Fourier decomposition of the CMV waveform.
$$ u_{cmv}(t) \approx \frac{V_{dc}}{2} + \frac{2V_{dc}}{3\pi} \left[ \sin(2\pi f_{sw} t) + \frac{1}{3}\sin(6\pi f_{sw} t) + \frac{1}{5}\sin(10\pi f_{sw} t) + … \right] $$ - Model Accuracy: The waveforms and trends predicted by the second-order common-mode equivalent circuit show good agreement with experimental measurements, validating its usefulness for analysis and design guidance.
Implications for Battery Energy Storage System Design and Optimization
The presence of significant high-frequency common-mode voltage and current has direct implications for the design, reliability, and safety of a battery energy storage system.
- Insulation Stress and Aging: The high dv/dt and increased voltage peaks accelerate electrical aging of insulation materials within battery modules, between cell tabs, and in associated cabling. Dielectric losses increase at high frequencies, generating heat and potentially leading to premature failure.
- BMS Interference: The common-mode current flowing through measurement shunts or creating ground loops can introduce noise into the BMS voltage and current sensing circuits, compromising state-of-charge (SOC) and state-of-health (SOH) estimation accuracy.
- Electromagnetic Compatibility (EMC): These currents are a source of conducted electromagnetic interference (EMI), which must be suppressed to meet regulatory standards and prevent interference with other equipment.
Design Recommendations:
- Enhanced Insulation Design: The insulation system within the battery cluster (e.g., between cells, modules, and the casing) must be rated not only for the DC voltage but also for the superimposed high-frequency, high-amplitude common-mode voltage stress.
- Parasitic Capacitance Management: The physical layout of the battery pack should be optimized to minimize uncontrolled parasitic capacitance to ground. This includes careful routing of high-voltage busbars, using insulation with lower dielectric constants, and increasing creepage/clearance distances strategically.
- Active Mitigation at the PCS: Employing PCS topologies or modulation strategies that inherently generate lower CMV (e.g., specific three-level modulations, active filters) is the most effective way to reduce the problem at its source for the connected battery energy storage system.
- Common-Mode Filtering: Installing common-mode chokes on the DC side of the PCS (between the PCS and the battery cluster) can present a high impedance to the common-mode current loop, effectively suppressing \(i_{cm}\) and attenuating \(u_{cmv}\).
- Grounding Strategy Review: While safety grounding is non-negotiable, the strategy for grounding the PCS DC-link midpoint or chassis can be analyzed. In some cases, a controlled high-frequency grounding impedance (e.g., an RC snubber to ground) can help damp resonances and divert harmful currents.
Conclusion
The analysis of ground electrical characteristics, specifically focusing on common-mode voltage and current effects, reveals a critical aspect of battery energy storage system design and operation. The interplay between the high-frequency switching of the Power Conversion System and the inherent parasitic capacitances within the battery cluster creates a significant stressor on the system. Key findings include the quantification of transient overvoltages and common-mode currents, the establishment of a predictive second-order equivalent circuit model, and the clear delineation of influencing factors such as parasitic capacitance and switching frequency.
Managing these effects is not optional for reliable, safe, and long-lasting grid-scale energy storage. It requires a holistic design approach encompassing the PCS modulation, the physical layout and insulation of the battery pack, and the strategic use of filtering components. By proactively addressing common-mode issues, designers can enhance the dielectric withstand capability, improve BMS measurement integrity, ensure EMC compliance, and ultimately increase the overall robustness and longevity of the battery energy storage system. This understanding provides essential technical support for the optimal design of next-generation, high-power energy storage solutions.