The global shift towards renewable energy sources like solar and wind is imperative for sustainable development. However, their inherent intermittency and variability pose significant challenges to grid stability and power quality. Battery Energy Storage Systems (BESS) have emerged as a crucial enabling technology, offering the flexibility to store excess energy and dispatch it when needed, thereby smoothing fluctuations and enhancing grid reliability. Among various power converter topologies for interfacing BESS, the Modular Multilevel Converter (MMC) and its derivatives are highly favored for medium- to high-voltage applications due to their superior waveform quality, scalability, and high efficiency.
This article focuses on a specific, promising variant: the Modular Multilevel Hybrid Converter-based Battery Energy Storage System (MMHC-BESS). It is particularly well-suited for low- to medium-voltage applications, such as distribution grids and commercial/industrial user-side energy management, offering a cost-effective solution with fewer power semiconductors compared to traditional MMC or Cascaded H-Bridge (CHB) topologies for the same output voltage level. At the heart of this system lies the distributed integration of energy storage cell units into the converter’s submodules. Each energy storage cell, typically a lithium-ion battery pack, is directly connected to a submodule capacitor, allowing for individual control and management.
The core principle involves series-connecting numerous identical submodules within each converter arm to synthesize a high-quality, stepped sinusoidal voltage. The modularity is a double-edged sword: while it enables high voltage levels with lower-rated devices, it also increases the number of potential failure points. The reliability of a system with dozens or hundreds of submodules, each containing an energy storage cell and power electronics, becomes paramount. A single submodule fault, if not managed properly, can lead to system shutdown, causing financial loss and reducing grid support functionality. Therefore, developing robust fault-tolerant control strategies that ensure continuous operation even under submodule failures is a critical research and engineering challenge.
Furthermore, the direct integration of energy storage cell units introduces the complex task of State-of-Charge (SOC) management. In a large string of series-connected energy storage cell units, imbalances are inevitable due to manufacturing variances, temperature differences, and aging. During normal operation, these imbalances can reduce the total usable capacity of the BESS, as the system must stop charging or discharging when any single energy storage cell reaches its voltage or SOC limit. During fault-tolerant operation, where phases may have unequal numbers of healthy submodules, the power imbalance can severely exacerbate SOC divergence between phases and within phases, further degrading performance and potentially leading to premature energy storage cell degradation.
This article presents a comprehensive analysis and solution set for the MMHC-BESS. First, we establish its mathematical model and analyze the limits of fault tolerance without hardware redundancy. We then propose a software-based fault-tolerant control strategy using modulation signal reconstruction. Subsequently, we address the secondary challenge by introducing a two-stage hierarchical SOC balancing strategy specifically designed for the post-fault unbalanced operating regime, aiming to maximize the utilization of every energy storage cell. Finally, the effectiveness of the proposed strategies is validated through detailed simulation studies.
Mathematical Foundation and Operational Principles of MMHC-BESS
The single-phase equivalent circuit of a three-phase MMHC-BESS connected to the grid is shown below. Each phase leg consists of ‘N’ submodules (SMs) connected in series. Each SM integrates a half-bridge converter, a DC-link capacitor, and an energy storage cell (battery pack). A bypass switch (K) is used to isolate a faulty SM. The output of each phase leg is fed through an H-bridge, which provides polarity reversal, enabling bipolar voltage generation from unipolar SM voltages.
The key variables for phase *j* (*j* ∈ {a, b, c}) are:
* $u_j$: Output voltage of the phase leg.
* $i_j$: Current flowing through the phase leg.
* $i_{g,j}$: Grid current.
* $u_{g,j}$: Grid voltage at the point of common coupling.
The governing equations for the AC side are derived from Kirchhoff’s Voltage Law (KVL):
$$ i_j = i_{g,j} $$
$$ u_j – u_{g,j} = L \frac{di_{g,j}}{dt} + R i_{g,j} $$
where *L* and *R* are the filter inductance and its equivalent series resistance, respectively.
The instantaneous power exchanged between the converter phase and the grid is:
$$ p_j(t) = u_{g,j}(t) \cdot i_{g,j}(t) $$
Under balanced sinusoidal conditions and assuming unity power factor control, the average power per phase is:
$$ \overline{P}_j = \frac{P_{\text{total}}}{3} $$
where $P_{\text{total}}$ is the total system power command. The power command for an individual energy storage cell within a healthy SM in phase *j* under normal, balanced conditions is:
$$ P_{\text{bat}, i}^* = \frac{P_{\text{total}}}{n_a + n_b + n_c} $$
where $n_a, n_b, n_c$ are the number of active SMs in each phase (normally all equal to N).
The grid-side controller typically employs a synchronous reference frame (dq) current control scheme. The active power ($P^*$) and reactive power ($Q^*$) references generate the d- and q-axis current references ($i_d^*$, $i_q^*$). After current regulation and decoupling, the controller outputs three-phase balanced sinusoidal modulation signals $u_j^*$.
Fault-Tolerant Operation: Analysis and Control Strategy
Maximum Allowable Faults and Operating Regimes
To ensure system availability, redundancy is often incorporated. This can be “hot” redundancy (extra SMs actively switching in parallel) or “cold” redundancy (standby SMs). However, adding redundancy increases cost and complexity. It is crucial to understand the fundamental limit of fault tolerance even without dedicated redundant hardware.
The primary constraint is the peak AC line voltage the converter must generate. For a grid with phase voltage amplitude $U_m$, the required maximum phase leg output voltage is $U_m$. Each SM provides a voltage equal to its energy storage cell voltage, $V_{\text{bat}}$. With $n$ original SMs and $n_r$ redundant SMs, the total available DC voltage per phase is $(n + n_r)V_{\text{bat}}$. When $n_e$ SMs fail in a phase, the available voltage becomes $(n + n_r – n_e)V_{\text{bat}}$.
The system can maintain normal modulation only if this available voltage exceeds the peak AC voltage requirement with sufficient margin (related to the modulation index M, where 0 < M < 1). The critical condition is defined by the ratio:
$$ \lambda = \frac{n + n_r – n_e}{n} $$
Here, $\lambda$ represents the “output capability factor” of the fault-affected phase relative to its healthy state.
The operating regime is determined as follows:
| Condition | Operating Regime | Description |
|---|---|---|
| $\lambda \ge 1$ | Redundant or Normal Operation | Healthy and redundant SMs can provide full voltage. Modulation signals remain unchanged. |
| $M \le \lambda < 1$ | Asymmetrical Fault-Tolerant Operation | Available voltage is reduced but still sufficient to synthesize the reference waveform by increasing modulation depth. Modulation signals must be scaled. |
| $\lambda < M$ | Uncontrollable | Available voltage is insufficient to generate the required AC voltage. System may lose control. |
The maximum number of tolerable faults $n_{e,\text{max}}$ in a phase for a given modulation index M is thus:
$$ n_{e,\text{max}} = n + n_r – \lceil n \cdot M \rceil $$
where $\lceil \cdot \rceil$ denotes the ceiling function.
Modulation Waveform Reconstruction for Fault Tolerance
When operating in the Asymmetrical Fault-Tolerant Regime ($M \le \lambda < 1$), the faulted phase cannot accurately track the original balanced reference signal $u_j^*$ because its voltage base is reduced. To maintain balanced line-line voltages and sinusoidal grid currents, the modulation signals must be reconstructed.
The fundamental principle is to scale up the reference signal for the faulted phase, effectively using a higher modulation index for that phase to compensate for the lower DC voltage base. For a fault in phase *a* with $n_e$ failed SMs, the reconstructed reference signal becomes:
$$ u_{a,\text{ref}}^* = \frac{n}{n + n_r – n_e} \cdot u_a^* = \frac{1}{\lambda} \cdot u_a^* $$
The references for healthy phases remain unchanged: $u_{b,\text{ref}}^* = u_b^*$, $u_{c,\text{ref}}^* = u_c^*$. This scaling ensures that the *fundamental component* of the synthesized line-line voltages (e.g., $u_{ab} = u_a – u_b$) remains balanced, even though the phase voltages themselves are asymmetric.
Carrier-Based Implementation with Phase-Shift Adjustment
The practical implementation uses Phase-Shifted Carrier (PSC) Pulse Width Modulation (PWM). In normal operation with N SMs per phase, N carriers are used, each shifted by $2\pi / N$. This ensures equal power distribution among SMs and high effective switching frequency.
When a submodule fails and is bypassed, the number of active SMs in that phase decreases to $N’ = n + n_r – n_e$. The PSC scheme must be adapted:
1. The PWM signals for the faulty SM are permanently disabled, and its bypass switch is closed.
2. The carrier signals for the remaining $N’$ healthy SMs in that phase are redistributed, with a new phase shift of $2\pi / N’$ between them.
3. The scaled modulation signal $u_{j,\text{ref}}^*$ is compared with this new set of carriers to generate the switching signals.
This process ensures that the available voltage levels in the faulted phase are used optimally and that the switching stress is evenly distributed among the remaining healthy SMs containing the energy storage cell units.
| Step | Action |
|---|---|
| 1 | Detect and isolate the faulty SM (disable pulses, close bypass). |
| 2 | Calculate the output capability factor $\lambda$ for the faulted phase. |
| 3 | If $M \le \lambda < 1$, proceed to Asymmetrical Fault-Tolerant Operation. |
| 4 | Reconstruct the modulation signal for the faulted phase: $u_{j,\text{ref}}^* = u_j^* / \lambda$. |
| 5 | Reconfigure the carrier signals for the faulted phase: new phase shift = $2\pi / (n + n_r – n_e)$. |
| 6 | Apply the reconstructed modulation wave to the reconfigured carriers. |
Hierarchical State-of-Charge (SOC) Balancing Strategy for Fault-Tolerant Operation
The fault-tolerant control maintains external power quality but creates an internal imbalance: the faulted phase has fewer active energy storage cell units to share the phase power. If left unchecked, this leads to faster SOC change in the faulted phase’s cells compared to the healthy phases, causing significant inter-phase SOC divergence. Furthermore, within a phase, intrinsic differences between individual energy storage cell units can cause intra-phase imbalance. A two-level hierarchical balancing strategy is proposed to address this.
Level 1: Inter-Phase SOC Balancing via Zero-Sequence Voltage Injection
The goal is to dynamically redistribute the total power $P_{\text{total}}$ among the three phases based on their aggregate SOC, rather than equally. This is achieved by injecting a zero-sequence voltage $u_0$ into the modulation signals. A zero-sequence voltage is common to all three phases and does not appear in the line-line voltages, thus it does not affect the balanced grid currents or total power transfer.
Let $SOC_{\text{sum},j}$ be the sum of the SOCs of all active energy storage cell units in phase *j*. The total system SOC sum is $SOC_{\text{total}} = \sum_{j=a,b,c} SOC_{\text{sum},j}$. The desired power sharing ratio for phase *j* is:
$$ K_j = \frac{SOC_{\text{sum},j}}{SOC_{\text{total}}} $$
Under perfect balance, all $K_j = 1/3$. To achieve this power distribution, a specific zero-sequence voltage component is added. The modified reference signals become:
$$ u_{j,\text{ref,inter}}^* = u_{j,\text{ref}}^* + u_0 $$
where $u_0$ is calculated to alter the power drawn from each phase. An effective synthesis method defines $u_0$ in terms of the grid voltages and the deviation of $K_j$ from 1/3:
$$ u_0 = 2 \left[ u_{g,a}(K_a – \frac{1}{3}) + u_{g,b}(K_b – \frac{1}{3}) + u_{g,c}(K_c – \frac{1}{3}) \right] $$
This formulation dynamically adjusts phase powers. For a phase with higher aggregate SOC ($K_j > 1/3$), it is commanded to provide more power during discharge (or absorb less during charge), and vice versa.
Special Consideration for Faulted Phase: In the faulted phase, the zero-sequence voltage $u_0$ is distributed across fewer SMs. To maintain the correct voltage addition per SM and prevent over-modulation, the zero-sequence component for the faulted phase (e.g., phase *a*) needs to be scaled:
$$ u_{a,\text{ref,inter}}^* = u_{a,\text{ref}}^* + \left(\frac{n}{n + n_r – n_e}\right) u_0 $$
This ensures the voltage stress per remaining healthy energy storage cell submodule is consistent with the control intent.
Level 2: Intra-Phase SOC Balancing via Dynamic Power Factor Adjustment
Within each phase, individual energy storage cell SOCs may differ. The goal is to equalize them by finely adjusting the power command for each SM. This is implemented by adding a corrective term to the average power command for SMs in that phase.
Let $\overline{SOC}_j$ be the average SOC of active SMs in phase *j*. For the *i*-th SM in phase *j* with SOC $SOC_{j,i}$, a proportional controller generates a power adjustment:
$$ \Delta P_{j,i} = K_p (\overline{SOC}_j – SOC_{j,i}) $$
where $K_p$ is a proportional gain. The total power reference for phase *j*, $P_j^*$, is determined by the Level 1 inter-phase balancing. The individual power reference for SM *i* is then:
$$ P_{j,i}^* = \frac{P_j^*}{N’} + \Delta P_{j,i} $$
where $N’$ is the number of active SMs in phase *j*.
This power command is translated into a modulation depth adjustment for that specific SM. A balancing factor $\beta_{j,i}$ is calculated:
$$ \beta_{j,i} = \frac{P_{j,i}^*}{(P_j^* / N’)} $$
The final modulation signal for the *i*-th SM in phase *j* is:
$$ u_{j,i,\text{final}}^* = \beta_{j,i} \cdot u_{j,\text{ref,inter}}^* $$
This means an energy storage cell with a lower-than-average SOC ($\Delta P_{j,i} > 0$) will receive a slightly larger modulation signal, causing it to contribute less power during discharge (or absorb more during charge), thereby raising its SOC relative to its peers.
The complete hierarchical control structure integrates both levels: the zero-sequence injection handles bulk power transfer between phases, while the individual per-SM factor adjustment handles fine-grained balancing within each phase, ensuring optimal utilization of every single energy storage cell even during asymmetrical fault-tolerant operation.
Simulation Verification and Results Analysis
To validate the proposed strategies, a detailed simulation model of a 13-level (6 SMs per phase initially) MMHC-BESS was built. The system parameters are summarized below:
| Parameter | Value |
|---|---|
| Rated Grid Voltage (Phase, RMS) | 220 V |
| System Power | 24 kW |
| Grid Filter Inductance (L) | 1 mH |
| Equivalent Series Resistance (R) | 0.1 Ω |
| Number of SMs per Phase (n) | 6 |
| Energy Storage Cell Voltage ($V_{\text{bat}}$) | 64 V |
| Submodule Capacitance | 475 µF |
| Switching Frequency | 10 kHz |
Scenario 1: Response to Submodule Fault and Fault-Tolerant Control Activation.
The system starts in normal discharge mode. At t=0.2s, a permanent fault is triggered in SM6 of phase A. The SM is bypassed. Initially, with no corrective action (0.2s to 0.3s), the three-phase grid currents become highly unbalanced and distorted due to the asymmetry, as the faulted phase can no longer track its reference. At t=0.3s, the proposed fault-tolerant control is activated. Instantly, the modulation signal for phase A is reconstructed (scaled up), and the carrier arrangement is adjusted. The results show that the grid currents rapidly regain perfect balance and sinusoidal shape. The line-line voltages also remain balanced and multistepped, although the phase voltage of phase A has fewer steps (5 levels now vs. 7 in healthy phases). The system maintains the commanded active power while keeping reactive power near zero.
Scenario 2: Performance of Hierarchical SOC Balancing during Fault-Tolerant Operation.
The initial SOCs of the 18 energy storage cell units (6 per phase) are set with random imbalances both between and within phases. Phase A’s SM6 is pre-set as faulty (bypassed, SOC fixed). The system operates in discharge mode with the proposed two-level balancing strategy active.
Inter-Phase Balance: The plot of the sum of SOCs per phase ($SOC_{\text{sum},j}$) reveals the effectiveness of Level 1 control. After the fault, the sum of SOCs in phase A is naturally lower because one cell is offline. The zero-sequence voltage injection successfully adjusts the power flow: phase A (with lower total capacity) delivers less current over time compared to phases B and C. Consequently, the sum SOCs of all three phases converge towards a common value, demonstrating successful inter-phase energy balancing.
Intra-Phase Balance: The SOC trajectories of individual energy storage cell units within each phase are observed. In phase A (with 5 active cells), the four initially higher-SOC cells discharge slightly faster, while the one initially lower-SOC cell discharges slower, causing all five SOC curves to converge. The same converging trend is clearly visible for the six cells in the healthy phases B and C. This demonstrates the efficacy of the Level 2 control using dynamic per-SM modulation adjustment.
The zero-sequence voltage $u_0$ and its in-phase projections ($u_{0a}, u_{0b}, u_{0c}$) were monitored. They show dynamic, non-sinusoidal waveforms that continuously adjust based on the real-time SOC ratios $K_j$, confirming the active redistribution of power among phases.
Conclusion and Perspective
This article has presented a holistic approach to enhancing the reliability and performance of Modular Multilevel Hybrid Converter-based Battery Energy Storage Systems. The cornerstone is a software-only fault-tolerant control strategy that enables continuous operation following submodule failures without relying on immediate hardware redundancy. By establishing the mathematical relationship between the number of healthy submodules and the achievable modulation index, the strategy dynamically reconstructs modulation waveforms and reconfigures the PWM carrier system. This maintains balanced grid currents and stable power exchange, which is critical for grid support functions.
Recognizing that fault-induced asymmetry severely impacts the longevity and capacity of the integrated energy storage cell units, a two-stage hierarchical SOC balancing strategy was developed. The first stage employs zero-sequence voltage injection to perform coarse, inter-phase power redistribution based on the aggregate SOC of each phase. The second stage performs fine, intra-phase balancing by individually adjusting the power reference for each submodule via a dynamic modulation factor. This dual-loop approach ensures that all energy storage cell units, whether in a healthy or faulted phase, are utilized uniformly, maximizing the system’s available energy capacity and prolonging battery life.
The simulation results validate both the feasibility and effectiveness of the proposed framework. The system seamlessly transitions to a stable fault-tolerant state, maintaining power quality, and simultaneously executes sophisticated energy management across the battery packs. Future work could involve experimental validation on a down-scaled prototype, extension of the control strategy to handle multiple simultaneous faults in different phases, and integration of lifetime prediction models for the energy storage cell to optimize the balancing algorithms further. As the penetration of renewable energy and distributed storage grows, such advanced control schemes will be essential for building resilient, efficient, and intelligent power infrastructure.