I study conducted electromagnetic interference in solar inverters because the switching behavior of modern power semiconductors directly affects grid quality, conversion efficiency, and the reliability of the entire photovoltaic energy conversion chain. In my work, I focus on solar inverters that use a boost stage and a T-type three-level inverter. The key problem I address is that fast IGBT transitions generate high \(dv/dt\) and \(di/dt\), and these transitions interact with parasitic capacitances and inductances to create common-mode and differential-mode noise. I model these mechanisms, extract the noise source impedance, design AC-side and DC-side EMI filters, and use a fast non-dominated sorting genetic algorithm to reduce filter volume while preserving attenuation.
My starting point is the switching cell. I treat the IGBT as the dominant noise source in solar inverters, not as an ideal switch. When the device turns on or turns off, the device voltage and current pass through several transient intervals. Each interval contributes a different spectral component. The turn-on process is especially important because the reverse recovery of the freewheeling diode can produce a current overshoot, and the parasitic emitter inductance can produce a voltage notch. The turn-off process is equally important because the current fall time and the collector-emitter voltage rise time create a high-frequency oscillation. I summarize the turn-on intervals in the following table.
| Turn-on interval | Condition | Device behavior | Noise implication |
|---|---|---|---|
| Interval 1 | Gate voltage rises toward threshold | Input capacitance is charged; no collector current flows | Low current noise, but gate loop resonance can couple into the power loop |
| Interval 2 | Gate voltage exceeds threshold | Collector current begins to rise; parasitic inductance supports a voltage drop | High \(di/dt\) excites differential-mode noise in solar inverters |
| Interval 3 | Diode reverse recovery | Collector current overshoots and then falls to load current | Strong high-frequency ringing and common-mode displacement current |
| Interval 4 | Device fully enhanced | Collector-emitter voltage settles to conduction drop | Noise decays, but parasitic capacitance remains charged |
I express the gate charging behavior as a first-order RC response:
$$ V_{ge}(t)=V_{g}\left(1-e^{-t/(R_g(C_{cg}+C_{ge}))}\right) $$
The time required to reach the threshold voltage is:
$$ t_1=R_g(C_{cg}+C_{ge})\ln\left(\frac{V_g}{V_g-V_{th}}\right) $$
During the current rise, the collector-emitter voltage is reduced by the parasitic source inductance:
$$ V_{ce}(t)=V_{dc}-L_s\frac{di_c(t)}{dt} $$
The turn-off process can be divided in a similar way. I summarize it in the next table.
| Turn-off interval | Condition | Device behavior | Noise implication |
|---|---|---|---|
| Interval 1 | Gate voltage falls from on-state value | Input capacitance discharges; collector current remains at load value | Gate loop behavior is still quasi-static |
| Interval 2 | Collector-emitter voltage begins to rise | Depletion region expands; Miller capacitance changes | High \(dv/dt\) drives common-mode current through parasitic capacitance |
| Interval 3 | Collector current begins to fall | Current fall interacts with loop inductance | Voltage overshoot and high-frequency ringing |
| Interval 4 | Gate voltage below threshold | Channel disappears; voltage settles to DC bus value | Residual oscillation decays through parasitic paths |
I express the gate discharge behavior as:
$$ V_{ge}(t)=V_{g}e^{-t/(R_g(C_{cg}+C_{ge}))} $$
For solar inverters, these switching transitions are not isolated events. They occur repeatedly at the PWM frequency, and the resulting spectrum extends from the switching frequency and its harmonics into the conducted EMI range. I therefore treat the IGBT not only as a power conversion device but also as a broadband noise source.
I next model the T-type three-level inverter because it is widely used in solar inverters when high efficiency and low harmonic distortion are required. Each phase leg can produce three output levels. I list the switching states in the table below.
| \(S_{a1}\) | \(S_{a2}\) | \(S_{a3}\) | \(S_{a4}\) | Output level |
|---|---|---|---|---|
| 1 | 1 | 0 | 0 | \(+U_{dc}/2\) |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | \(-U_{dc}/2\) |
When the phase leg changes from the positive state to the neutral state, the current path changes through the upper switch, the neutral-point switches, or the anti-parallel diodes depending on the load current direction. I observe that each commutation event changes the potential of the phase terminal with respect to ground. This potential change is the origin of common-mode voltage in solar inverters. The common-mode voltage of a three-phase system is:
$$ V_{CM}=\frac{V_A+V_B+V_C}{3} $$
I also derive the three-phase KVL equations for the AC side:
$$
\begin{aligned}
V_{AO}-V_{CM}&=Ri_A+L\frac{di_A}{dt},\\
V_{BO}-V_{CM}&=Ri_B+L\frac{di_B}{dt},\\
V_{CO}-V_{CM}&=Ri_C+L\frac{di_C}{dt}.
\end{aligned}
$$
For the DC side, I model the boost converter as another noise source inside solar inverters. When the boost switch turns on, the input capacitor and the boost inductor form a differential-mode loop. When the boost switch turns off, the diode and the output capacitor form another differential-mode loop. At the same time, the switched node voltage drives a common-mode current through the parasitic capacitance to ground. I summarize the two noise modes as follows.
| Noise mode | Main path | Dominant excitation | Typical source |
|---|---|---|---|
| Common mode | Phase or DC line to ground through parasitic capacitance | \(dv/dt\) | IGBT collector-emitter voltage transitions |
| Differential mode | Line-to-line or positive-to-negative DC path | \(di/dt\) | Switching current loops and diode recovery |
I use a line impedance stabilization network to measure the conducted noise of solar inverters. The network provides a defined impedance and separates the noise from the power source. The internal components and their roles are given in the following table.
| Component | Value | Role |
|---|---|---|
| \(L_1,L_2\) | \(50\,\mu H\) | Block high-frequency noise from the power source |
| \(C_1,C_2\) | \(1\,\mu F\) | Provide a low-impedance path for power-frequency current |
| \(C_3,C_4\) | \(0.1\,\mu F\) | Couple the noise to the measurement port |
| \(R_1,R_3\) | \(1\,k\Omega\) | Discharge path and bias stability |
| \(R_2,R_4\) | \(50\,\Omega\) | Provide the standard measurement impedance |
The line currents measured by the LISN are related to the common-mode and differential-mode currents by:
$$ i_L=i_{CM}+i_{DM},\qquad i_N=i_{CM}-i_{DM} $$
The corresponding modal voltages are:
$$ V_{CM}=\frac{V_L+V_N}{2},\qquad V_{DM}=\frac{V_L-V_N}{2} $$
I use these equations to separate the measured noise into common-mode and differential-mode components. This separation is essential for solar inverters because the two modes require different filter topologies and different component values.
I validate the noise mechanism with a MATLAB/Simulink model. I include parasitic inductances of the switching devices, cable inductances, and parasitic capacitances to ground. I also compare ideal components with non-ideal components. The simulation shows that a higher switching frequency increases the noise voltage in solar inverters. It also shows that larger parasitic parameters produce higher conducted noise. When I replace ideal inductors and capacitors with high-frequency models, the harmonic content of the grid current increases, and the filter attenuation becomes less ideal. These results confirm that parasitics cannot be ignored in solar inverters.
For the filter itself, I first examine the basic components. A real inductor is not a pure inductance. It includes winding resistance and distributed capacitance. I write its impedance as:
$$ Z_L(\omega)=\frac{R_P+j\omega L}{1-\omega^2LC_P+j\omega C_PR_P} $$
A real capacitor is not a pure capacitance either. It includes equivalent series resistance and equivalent series inductance. I write its impedance as:
$$ Z_C(\omega)=R_C+j\omega L_P+\frac{1}{j\omega C} $$
I use these models because the self-resonant frequency of a component determines its effective filtering range. In solar inverters, an inductor above its self-resonant frequency behaves capacitively, and a capacitor above its self-resonant frequency behaves inductively. I therefore choose components so that their self-resonant frequencies lie above the noise band of interest whenever possible.
I also consider safety and leakage. Common-mode capacitors are connected between line and ground, so their value is limited by leakage current. For a 220 V, 50 Hz grid, the leakage current must remain below the safety limit. I use:
$$ I=2\pi f C U $$
Differential-mode capacitors are connected line-to-line. They must withstand surge events, so I select X-class capacitors with appropriate voltage ratings. I summarize the design considerations in the following table.
| Filter element | Function | Design constraint | Typical choice |
|---|---|---|---|
| Common-mode inductor | Suppress common-mode current in solar inverters | High impedance at noise frequencies; low leakage | Nanocrystalline or ferrite toroid |
| Differential-mode inductor | Suppress differential-mode current in solar inverters | High saturation current; low DC resistance | Powder core or leakage inductance of CM choke |
| Common-mode capacitor | Divert common-mode currents | Leakage current limit | Y-class capacitor |
| Differential-mode capacitor | Divert differential-mode currents | Surge rating and displacement factor | X-class capacitor |
I then treat the EMI filter as a two-port network. This is the core of my design method. The insertion loss is defined as the ratio of load power before and after the filter is inserted:
$$ IL=10\log_{10}\left(\frac{P_1}{P_2}\right)=20\log_{10}\left(\frac{V_2′}{V_2}\right) $$
For a two-port network with ABCD parameters, the source impedance \(Z_S\), and the load impedance \(Z_L\), the insertion loss is:
$$ IL=20\log\left|\frac{AZ_L+B+CZ_SZ_L+DZ_S}{Z_S+Z_L}\right| $$
I use this expression to study how the noise source impedance affects the filter performance. The result is important for solar inverters because the source impedance is not constant and is not equal to \(50\,\Omega\) in many practical installations. I summarize several typical filter networks and their transmission matrices in the following table.
| Network | Transmission matrix |
|---|---|
| Single inductor | \(\begin{bmatrix}1 & j\omega L\\0 & 1\end{bmatrix}\) |
| Single capacitor | \(\begin{bmatrix}1 & 0\\j\omega C & 1\end{bmatrix}\) |
| LC type | \(\begin{bmatrix}1-\omega^2LC & j\omega L\\j\omega C & 1\end{bmatrix}\) |
| CL type | \(\begin{bmatrix}1 & j\omega L\\j\omega C & 1-\omega^2LC\end{bmatrix}\) |
| CLC type | \(\begin{bmatrix}1-\omega^2LC_1 & j\omega L\\j\omega(C_1+C_2)-j\omega^3LC_1C_2 & 1-\omega^2LC_2\end{bmatrix}\) |
| LCL type | \(\begin{bmatrix}1-\omega^2L_1C & j\omega(L_1+L_2)-j\omega^3L_1L_2C\\j\omega C & 1-\omega^2L_2C\end{bmatrix}\) |
When I plot insertion loss as a function of frequency and source impedance, I find a clear trend. For L-type, LC-type, and LCL-type filters, the inductor faces the noise source. In these topologies, the insertion loss decreases when the source impedance increases. The worst case occurs at the maximum source impedance. For C-type, CL-type, and CLC-type filters, the capacitor faces the noise source. In these topologies, the insertion loss decreases when the source impedance decreases. The worst case occurs at the minimum source impedance. This means that I can design for the worst-case source impedance and obtain robust attenuation across the conducted EMI band in solar inverters.
To obtain the source impedance, I use an insertion-loss-based extraction method. I do not assume that the source impedance is infinite or equal to \(50\,\Omega\). Instead, I insert a known common-mode inductor and measure the attenuation. I write the common-mode attenuation as:
$$ A_T=\frac{R_{loadCM}+Z_{sCM}}{R_{loadCM}+Z_{sCM}+Z_{fCM}} $$
From this expression, I obtain the maximum and minimum possible values of the common-mode source impedance:
$$ |Z_{sCM}|_{MAX}=\frac{|Z_{fCM}|}{1-A_T}+R_{loadCM} $$
$$ |Z_{sCM}|_{MIN}=\left|\frac{|Z_{fCM}|}{1-A_T}-R_{loadCM}\right| $$
For differential-mode impedance, I insert a known differential-mode capacitor and measure the attenuation. When the load resistance is much larger than the source impedance, I obtain:
$$ |Z_{sDM}|_{MAX}=|Z_{fDM}|(1+A_T) $$
$$ |Z_{sDM}|_{MIN}=|Z_{fDM}|(1-A_T) $$
I apply this method to both the AC side and the DC side of solar inverters. The extracted data are summarized in the following tables.
| Frequency (kHz) | \(A_{CM,req}\) | \(|Z_{sCM}|_{MAX}\) (\(\Omega\)) | \(|Z_{sCM}|_{MIN}\) (\(\Omega\)) |
|---|---|---|---|
| 150 | 17.78 | 72.80 | 39.47 |
| 200 | 11.22 | 139.56 | 106.22 |
| 300 | 10.00 | 226.00 | 192.66 |
| 400 | 10.00 | 295.78 | 262.44 |
| 500 | 6.31 | 608.00 | 574.67 |
| Frequency (kHz) | \(A_{DM,req}\) | \(|Z_{sDM}|_{MAX}\) (\(\Omega\)) | \(|Z_{sDM}|_{MIN}\) (\(\Omega\)) |
|---|---|---|---|
| 150 | 28.18 | 30.93 | 28.81 |
| 200 | 33.50 | 27.60 | 26.00 |
| 300 | 17.78 | 9.95 | 8.89 |
| 400 | 18.20 | 7.68 | 6.88 |
| 500 | 17.78 | 6.00 | 5.37 |
| Frequency (kHz) | \(A_{CM,req}\) | \(|Z_{sCM}|_{MAX}\) (\(\Omega\)) | \(|Z_{sCM}|_{MIN}\) (\(\Omega\)) |
|---|---|---|---|
| 150 | 3.16 | 39.35 | 10.65 |
| 200 | 2.51 | 52.60 | 2.60 |
| 300 | 2.04 | 87.13 | 27.13 |
| 400 | 1.67 | 128.62 | 78.62 |
| 500 | 1.20 | 197.67 | 147.67 |
| Frequency (kHz) | \(A_{DM,req}\) | \(|Z_{sDM}|_{MAX}\) (\(\Omega\)) | \(|Z_{sDM}|_{MIN}\) (\(\Omega\)) |
|---|---|---|---|
| 150 | 25.19 | 103.28 | 52.90 |
| 200 | 17.78 | 91.38 | 55.83 |
| 300 | 16.79 | 120.89 | 87.31 |
| 400 | 25.19 | 234.02 | 183.64 |
| 500 | 19.95 | 226.63 | 186.73 |
With these impedance bounds, I design the EMI filter for solar inverters. I first determine the required insertion loss by comparing the original noise spectrum with the applicable limit:
$$ IL_{req}=IL_{ori}-Limit+6\text{ dB}\mu V $$
I then choose the common-mode capacitor from the leakage-current constraint. For a 220 V, 50 Hz system, I use:
$$ I=2\pi f C U $$
I choose the differential-mode capacitor according to the desired displacement factor and surge rating. In my design, I use \(C_Y=0.01\,\mu F\) for common mode and \(C_X=3.3\,\mu F\) for differential mode. I then calculate the common-mode corner frequency:
$$ f_{cm}=\frac{1}{2\pi}\sqrt{\frac{|Z_{sCM}|_{MAX}+R_{loadCM}}{R_{loadCM}L_{CM}C_{CM}}} $$
and the differential-mode corner frequency:
$$ f_{dm}=\frac{1}{2\pi}\sqrt{\frac{|Z_{sDM}|_{MAX}+R_{loadDM}}{R_{loadDM}L_{DM}C_{DM}}} $$
I also obtain the required attenuation slope. For a two-stage LC filter, the slope is \(40\,dB/dec\). I shift the required attenuation line to the corner frequency:
$$ f_{ccm}=f_{Tcm}10^{-V_{cm.req}/40},\qquad f_{cdm}=f_{Tdm}10^{-V_{dm.req}/40} $$
I then equate the corner frequency expressions and solve for the common-mode and differential-mode inductances. I compare three design approaches: infinite source impedance, fixed \(50\,\Omega\) source impedance, and the extracted source impedance. The resulting filter parameters are listed in the next table.
| Design approach | AC CM inductance | AC DM inductance | DC CM inductance | DC DM inductance |
|---|---|---|---|---|
| Infinite source impedance | \(0.2\,mH\) | \(1.0\,\mu H\) | \(0.2\,mH\) | \(1.0\,\mu H\) |
| Fixed \(50\,\Omega\) source impedance | \(0.8\,mH\) | \(1.33\,\mu H\) | \(0.6\,mH\) | \(1.5\,\mu H\) |
| Extracted source impedance | \(1.2\,mH\) | \(5.4\,\mu H\) | \(1.5\,mH\) | \(4.2\,\mu H\) |
I validate the design with MATLAB simulations. The AC-side system uses a 220 V grid, an 800 V DC bus, a 10 kHz switching frequency, and a 20 kW active power rating. The DC-side system uses a 400 V input, an 800 V output, a 15 kHz switching frequency, and a 30 \(\Omega\) load. I compare the unfiltered case, a filter designed with infinite source impedance, a filter designed with \(50\,\Omega\) source impedance, and the filter designed with the extracted source impedance. The filter designed with the extracted source impedance gives the lowest residual noise voltage. For the AC side, it reduces the noise voltage to approximately 0.6 V. For the DC side, it reduces the noise voltage to approximately 3 V. These results show that ignoring the source impedance leads to suboptimal attenuation in solar inverters.
I also build an experimental platform for a T-type three-level photovoltaic grid-connected inverter. The platform uses a photovoltaic simulator, a 30 kW inverter, a line impedance stabilization network, a spectrum analyzer, an oscilloscope, and a current probe. The key equipment parameters are summarized below.
| Equipment | Parameter |
|---|---|
| Photovoltaic simulator | 250 V, programmable solar curve |
| Grid-connected inverter | 30 kW, T-type three-level topology |
| LISN | 150 kHz to 30 MHz, 50 \(\Omega\)/50 \(\mu H\) |
| Spectrum analyzer | 5 kHz to 1 GHz |
| Oscilloscope | 200 MHz, 1 GS/s |
| Current probe | 15 MHz, 0 A to 150 A |
The experimental results confirm my simulation. Before filtering, the common-mode current is about 77 mA, and the differential-mode current is about 126 mA. After inserting the filter designed from the extracted source impedance, the common-mode current drops to about 35 mA, and the differential-mode current drops to about 49 mA. The EMI noise spectrum is reduced by approximately 30 dB\(\mu V\). I observe that the filter provides margin below the limit across the entire conducted band.
Although the source-impedance-based design improves accuracy, it can increase the filter volume if the inductance is chosen too conservatively. I therefore introduce a multi-objective optimization step. I begin with the standard genetic algorithm. It uses selection, crossover, and mutation. The selection probability of an individual is:
$$ P_i=\frac{f_i}{\sum_{j=1}^{N}f_j} $$
Crossover combines two parent individuals. Mutation randomly changes a gene. I use these operations because they allow the search to explore a wide solution space. However, the standard genetic algorithm often converts multiple objectives into a single weighted objective. This introduces subjectivity into the weight selection and can produce a poor result for solar inverters, where both attenuation and volume matter.
I therefore use the fast non-dominated sorting genetic algorithm, NSGA-II. This algorithm ranks individuals by non-domination and then preserves diversity by crowding distance. The non-dominated sorting procedure assigns rank 1 to all individuals that are not dominated by any other individual. It then removes rank 1 and repeats the process. The crowding distance of an individual is computed from the neighboring individuals in the same front:
$$ L[i]_d=\sum_{k=1}^{m}\left|f_k(i+1)-f_k(i-1)\right| $$
The algorithm prefers individuals with lower rank and, within the same rank, larger crowding distance. I use an elitist strategy that combines parent and child populations before selection. This prevents the loss of good solutions during evolution. I set the population size to 150, the decision variable count to 2, the maximum iteration count to 150, the crossover probability to 0.8, and the mutation probability to 0.2. I summarize the NSGA-II settings in the following table.
| Parameter | Value |
|---|---|
| Population size | 150 |
| Number of decision variables | 2 |
| Maximum iterations | 150 |
| Crossover probability | 0.8 |
| Mutation probability | 0.2 |
| Lower bound | \(1\times 10^{-4}\) |
| Upper bound | \(2\times 10^{-2}\) |
For the optimization model, I use a two-stage LC filter. The differential-mode equivalent circuit includes the differential-mode source impedance, the first differential-mode inductor, the first differential-mode capacitor, the second differential-mode inductor, the second differential-mode capacitor, and the LISN load resistance. I write the differential-mode voltage at the load as:
$$ U_{DM}=\frac{Z_{Cdm1}Z_{Ldm1}Z_{Cdm2}Z_{Ldm2}R_{loadDM}}{Z_{Cdm1}Z_{Ldm1}Z_{Cdm2}Z_{Ldm2}+Z_{sDM}}V_{sDM} $$
I use the same procedure for the common-mode equivalent circuit. I then define the optimization objectives. The first objective is to ensure that the insertion loss exceeds the required value. The second objective is to minimize the volume. I can write the constraint as:
$$ IL_{CM}(\omega)\ge IL_{CM,req},\qquad IL_{DM}(\omega)\ge IL_{DM,req} $$
For the volume model, I relate the inductor volume to inductance, current, and the product of inductance and current. I use the following expression:
$$ V_L=k_{L1}L+k_{L2}I+k_{L3}LI+k_{L4} $$
I fit the coefficients from measured magnetic-core data. The fitted coefficients are \(k_{L1}=0.9718\), \(k_{L2}=0.2591\), \(k_{L3}=0.2559\), and \(k_{L4}=0.8364\). The fitted curve matches the measured data well, so I use it as the volume objective for solar inverters.
The optimization results show a significant volume reduction. For the common-mode filter, the original single-stage inductance is \(1.2\,mH\) with a volume of \(70.68\,cm^3\). After two-stage optimization, the common-mode inductances are \(0.3\,mH\) and \(0.2\,mH\), and the total volume is \(36.57\,cm^3\). For the differential-mode filter, the original inductance is \(5.4\,\mu H\) with a volume of \(6.51\,cm^3\). After optimization, the differential-mode inductances are \(3.6\,\mu H\) and \(1.9\,\mu H\), and the total volume is \(6.31\,cm^3\). I summarize the comparison below.
| Design stage | Filter component | Parameter | Total volume |
|---|---|---|---|
| Before optimization | Common-mode inductor | \(1.2\,mH\) | \(70.68\,cm^3\) |
| Before optimization | Differential-mode inductor | \(5.4\,\mu H\) | \(6.51\,cm^3\) |
| After optimization | Common-mode inductors | \(0.3\,mH\), \(0.2\,mH\) | \(36.57\,cm^3\) |
| After optimization | Differential-mode inductors | \(3.6\,\mu H\), \(1.9\,\mu H\) | \(6.31\,cm^3\) |
I verify the optimized two-stage filter in simulation. The grid current remains sinusoidal, and the noise voltage is suppressed to a level similar to that of the single-stage filter. This means that the two-stage design does not sacrifice attenuation while reducing the total magnetic volume. I then repeat the experiment. With the two-stage EMI filter, the common-mode current drops from about 77 mA to about 43 mA, and the differential-mode current drops from about 126 mA to about 35 mA. The EMI noise spectrum is reduced by approximately 25 dB\(\mu V\). These results confirm that the NSGA-II optimized filter is effective for solar inverters.
From my perspective, the main contributions of this work can be summarized as follows. I develop a conducted noise model for solar inverters that includes IGBT switching transients, parasitic parameters, and both AC-side and DC-side coupling paths. I establish a two-port network model for the EMI filter and show how the noise source impedance affects the insertion loss. I use an insertion-loss-based method to extract the common-mode and differential-mode source impedance bounds without assuming a fixed or infinite value. I then design the AC-side and DC-side filters from the extracted impedance and verify the design experimentally. Finally, I formulate a multi-objective optimization problem for the two-stage EMI filter and solve it with NSGA-II to reduce volume while maintaining attenuation.
The practical value of this work is that it reduces the trial-and-error effort that is often required when designing EMI filters for solar inverters. Instead of tuning components after the first prototype, I can estimate the source impedance, calculate the required inductance, and optimize the magnetic volume before construction. This is important for solar inverters because the market requires compact, efficient, and electromagnetically compatible products. The method also provides a clear path for extending the design to other converter topologies, other power levels, and other grid conditions.
I acknowledge that several directions remain open. One direction is to improve the accuracy of the source impedance extraction by including phase information and frequency dependence. Another direction is to include weak-grid conditions and load variations in the model. A third direction is to integrate the EMI filter design with the thermal and mechanical design of solar inverters so that volume, cost, and reliability are optimized together. In my future work, I plan to address these points and to validate the method on a wider range of solar inverters.
| Design issue | Traditional practice | My approach | Benefit for solar inverters |
|---|---|---|---|
| Source impedance | Assume infinite or \(50\,\Omega\) | Extract maximum and minimum bounds | More accurate attenuation prediction |
| Filter topology | Single-stage LC | Two-stage LC with optimized parameters | Lower magnetic volume |
| Optimization | Weighted single objective | NSGA-II with non-dominated sorting | Better trade-off between attenuation and volume |
| Validation | Simulation only | Simulation and experimental platform | Higher confidence for practical solar inverters |
Overall, I find that the electromagnetic compatibility of solar inverters cannot be separated from the switching behavior of the power devices, the parasitic layout, and the impedance of the surrounding system. By combining noise mechanism analysis, source impedance extraction, two-port filter modeling, and multi-objective optimization, I obtain a design procedure that is both physically meaningful and practically useful. The resulting EMI filters for solar inverters provide sufficient attenuation in the conducted frequency range while avoiding unnecessary magnetic volume.