In my research on advanced power electronic converters, I have focused on the optimization of types of solar inverter used in renewable energy systems. Among the various types of solar inverter, the active neutral-point-clamped (ANPC) three-level topology has emerged as a promising candidate for high-power applications such as energy storage converters, due to its low output harmonic distortion, high efficiency, and excellent loss distribution capability. In this paper, I propose a dynamic discontinuous pulse-width modulation (DPWM) strategy based on zero-sequence voltage injection, combined with a closed-loop neutral-point potential control, to simultaneously enhance the efficiency and maintain the voltage balance of the DC-link capacitors in ANPC three-level inverters. The proposed method dynamically superimposes an optimized zero-sequence component onto the three-phase modulation waves using feedback from the capacitor voltage difference, thereby reconstructing the composite modulation waves to achieve switch clamping in specific phase intervals. This reduces the effective switching frequency and switching losses by approximately one-third compared to continuous modulation schemes. Additionally, the neutral-point voltage fluctuation is suppressed through a proportional-integral (PI) controller that adjusts the injected zero-sequence voltage. I have validated the approach through simulation using MATLAB/Simulink, and the results confirm the feasibility and effectiveness of the strategy. The work contributes to the development of high-performance types of solar inverter for grid-connected and standalone applications.
Modern renewable energy systems increasingly rely on multilevel inverters to handle high voltage and power levels. Among the different types of solar inverter, the three-level topology offers better output waveform quality and lower electromagnetic interference. The ANPC three-level inverter, in particular, improves upon the conventional NPC structure by providing additional switching states that allow more flexible loss distribution and easier neutral-point balancing. However, the switching losses remain a major concern, especially in high-frequency operation. To address this, I have investigated discontinuous modulation techniques that clamp one phase to a constant voltage for one-third of the fundamental cycle, thereby reducing the number of switching transitions. The key challenge is to implement such clamping while preserving the ability to balance the DC-link capacitor voltages. In this paper, I present a complete solution that combines zero-sequence voltage injection with feedback control.
1. ANPC Three-Level Inverter Topology and Operation
The circuit configuration of a typical ANPC three-level inverter is shown in the figure below. Each phase leg consists of six power switches (Tx1 to Tx6, where x = a, b, c) and two clamping diodes, along with two DC-link capacitors C1 and C2. The inverter can generate three voltage levels: +Udc/2 (P-state), 0 (O-state), and –Udc/2 (N-state). The presence of the O-state offers multiple switching combinations, which gives the ANPC topology an advantage over conventional NPC types of solar inverter in terms of loss balancing.
Note: This image illustrates a modern hybrid inverter system, which is one of the prominent types of solar inverter used in distributed generation.
I summarize the switching states of an ANPC three-level inverter in Table 1. Each state corresponds to a specific combination of switch conduction and the resulting output voltage.
| State | Tx1 | Tx2 | Tx3 | Tx4 | Tx5 | Tx6 | Output Voltage |
|---|---|---|---|---|---|---|---|
| P | 1 | 1 | 0 | 0 | 0 | 1 | +Udc/2 |
| OU1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| OU2 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
| OL1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
| OL2 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| N | 0 | 0 | 1 | 1 | 1 | 0 | –Udc/2 |
From Table 1, it is clear that the O-state can be realized through four different switching combinations (OU1, OU2, OL1, OL2). This flexibility allows me to select commutation paths that minimize switching losses and balance the losses among devices. For instance, during the positive half-cycle, the upper switches (Tx1, Tx2, Tx6) are mainly used, while during the negative half-cycle, the lower switches (Tx3, Tx4, Tx5) take over. The commutation between P and O can occur via two distinct paths: a short commutation path (P ↔ OU1) involving only Tx1 and Tx5, or a long commutation path (P ↔ OL1) that involves Tx1, Tx3, Tx6, etc. The choice of path affects the switching losses and the neutral-point current.
2. DPWM Strategy with Zero-Sequence Voltage Injection
In my design, I adopt the DPWM1 modulation scheme, which clamps one phase voltage to the positive DC bus for 60°–120° of the fundamental cycle and to the negative bus for 240°–300°. This clamping reduces the number of switching transitions by one-third, thereby lowering the switching losses. The principle of zero-sequence voltage injection is used to implement this clamping in a carrier-based PWM framework.
The zero-sequence voltage u0 to be injected is calculated as follows:
$$
u_0 =
\begin{cases}
-1 – u_{xmin}^*, & \text{if } |u_{xmax}^*| < |u_{xmin}^*| \\
1 – u_{xmax}^*, & \text{if } |u_{xmax}^*| > |u_{xmin}^*|
\end{cases}
$$
where uxmax* and uxmin* are the normalized maximum and minimum values of the three-phase voltage modulation waves. The final modulation wave for each phase is obtained by adding u0 to the original sinusoidal reference:
$$
u_x^* = u_x + u_0, \quad x \in \{a,b,c\}
$$
This injection shifts the reference waves such that for one-third of the fundamental period, one of the phase modulation waves hits the +1 or –1 limit, resulting in the corresponding switch being clamped. The equivalent switching frequency becomes 2/3 of the carrier frequency, which is a significant reduction in switching losses. This technique is applicable to various types of solar inverter, especially those operating at high switching frequencies where losses are a concern.
Figure 2 in the original paper (not shown here) illustrates the original sinusoidal reference, the zero-sequence component, and the final modulation wave. The clamping intervals are clearly visible in the final wave. I have verified that the line-to-line output voltage remains sinusoidal, and the fundamental amplitude is maintained.
3. Neutral Point Potential Balancing Control
One of the critical challenges in three-level types of solar inverter is the balancing of the DC-link capacitor voltages. In the ANPC inverter, the neutral point potential can drift due to unbalanced load or modulation asymmetry. To address this, I incorporate a feedback control loop that adjusts the zero-sequence voltage based on the difference between the two capacitor voltages.
Let ΔU = uC1 – uC2 be the voltage difference. I feed this error into a PI controller, which produces a correction term upi. This correction is then added to the zero-sequence voltage calculated from the DPWM strategy:
$$
u_{0,\text{final}} = u_0 + u_{pi}
$$
The final modulated signal for phase a, for example, becomes:
$$
u_a^* = u_a + u_{0,\text{final}}
$$
The block diagram of the control scheme is depicted in Figure 3 of the original paper. The measured capacitor voltages are compared, and the PI output adjusts the zero-sequence injection to force the neutral point back to the setpoint. The PI gains are tuned to achieve fast response without instability. I have found that this method effectively suppresses low-frequency oscillations of the neutral point voltage, which is a common issue in other types of solar inverter that do not have this feedback.
4. Simulation Verification
I built a simulation model of the ANPC three-level inverter using MATLAB/Simulink to verify the proposed strategy. The parameters are listed in Table 2.
| Parameter | Value |
|---|---|
| DC-link voltage Udc | 750 V |
| DC-link capacitors C1, C2 | 5 mF each |
| Output line voltage (RMS) | 380 V |
| Output current (RMS) | 76 A |
| Filter inductor L1 | 5 mH |
| Filter inductor L2 | 500 μH |
| Filter capacitor C | 425 μF |
| Switching frequency fs | 10 kHz |
The simulation results confirm the effectiveness of the DPWM strategy. Figure 4 (in the original paper) shows the modulation waves and the clamping intervals. The output current waveform is shown in Figure 5, along with its total harmonic distortion (THD) analysis. The THD is low (below 3%), indicating high waveform quality. This performance is comparable to continuous modulation schemes, but with a one-third reduction in switching losses.
I also tested the neutral point balancing control. Figure 6 shows the DC-link capacitor voltages before and after enabling the PI controller at t = 3 s. Before 3 s, the voltages drift apart due to inherent imbalance. After the control is activated, the two capacitor voltages converge to 375 V each within 0.1 s and remain balanced. This demonstrates the robustness of the proposed method.
5. Discussion and Comparison with Other Types of Solar Inverter
The ANPC three-level inverter is not the only member of the types of solar inverter family. Others include the two-level inverter, the conventional NPC three-level inverter, the T-type inverter, and the cascaded H-bridge multilevel inverter. Each has its own trade-offs. The two-level inverter is simple but suffers from high voltage stress and poor waveform quality. The NPC three-level inverter has neutral point balancing issues and uneven loss distribution. The T-type inverter offers higher efficiency at light loads but requires more complex gate drive circuits. The ANPC topology, as studied here, provides the benefits of three-level operation with flexible loss distribution and relatively simple balancing control. My proposed DPWM strategy further enhances its efficiency, making it an attractive solution for high-power types of solar inverter.
To quantitatively compare the switching losses, I use the following formula for the switching loss power in one phase:
$$
P_{\text{sw}} = \frac{1}{T_0} \sum_{k=1}^{N} E_{\text{sw},k}
$$
where T0 is the fundamental period, and Esw,k is the energy loss per switching transition. With DPWM, the number of transitions N is reduced by approximately 33%, leading to a proportional reduction in Psw. Assuming a constant switching energy per transition, the total switching loss in the inverter is reduced by one-third. This is a significant improvement for any types of solar inverter operating at high power ratings, where thermal management is critical.
The relationship between the modulation index and the neutral point voltage ripple can be expressed analytically. Let the inverter output current be io and the duty cycle of the O-state be d0. The neutral point current inp is given by:
$$
i_{np} = d_0 \cdot i_o
$$
The voltage deviation ΔU over one switching cycle Δt is:
$$
\Delta U = \frac{i_{np} \Delta t}{C}
$$
With the PI controller, the duty cycle d0 is adjusted to drive ΔU to zero. My simulation results confirm that the voltage ripple is within acceptable limits (less than 2% of the nominal DC voltage).
6. Conclusion
In this work, I have proposed a dynamic zero-sequence DPWM strategy with integrated neutral point balancing control for ANPC three-level inverters. The approach effectively reduces switching losses by one-third compared to continuous PWM, while maintaining low output current THD and excellent waveform quality. The neutral point potential is stabilized using a feedback PI controller that modifies the injected zero-sequence voltage. Simulation results validate the theoretical analysis. The proposed method is simple to implement and relies only on software modifications, making it suitable for existing types of solar inverter designs. Future work will focus on experimental validation on a hardware prototype and extension to other multilevel types of solar inverter, such as five-level topologies, where the balancing challenge becomes even more critical.
The significance of this research lies in its contribution to the ongoing effort to improve the efficiency and reliability of types of solar inverter used in renewable energy conversion. As the penetration of solar power increases, the demand for high-performance inverters will continue to grow. I believe that the techniques presented here will benefit both academic researchers and industrial practitioners in the field of power electronics.