In the field of power electronics, the three phase inverter serves as a critical component for converting DC power to AC power in applications such as renewable energy systems, motor drives, and active filters. The performance of a three phase inverter directly impacts the stability, reliability, and efficiency of the entire system. Traditional inverters often rely on fixed topologies, such as two-level configurations, which are simple and robust but suffer from high voltage stress on switching devices and significant output current harmonics. To address these limitations, multi-level inverters, including three-level and four-level topologies, have been developed. These structures reduce voltage stress, improve output waveform quality, and allow for lower switching frequencies, thereby enhancing overall efficiency. However, designing separate experimental platforms for each inverter topology can be costly and inefficient, leading to hardware redundancy and increased laboratory space requirements. To overcome these challenges, I have designed a variable-structure three phase inverter experimental platform that can adapt to different topologies through reconfigurable terminal connections and control strategies. This platform leverages a digital signal processor (DSP) and field-programmable gate array (FPGA) for coordinated control, enabling the implementation of two-level, T-type three-level, and dual T-type four-level three phase inverters. The design incorporates split-bus main circuits, advanced modulation techniques, and comprehensive protection mechanisms to ensure reliability and flexibility. This article details the implementation principles, hardware design, control strategies, and experimental results of this variable-structure three phase inverter platform, emphasizing its cost-effectiveness and versatility for research and educational purposes.
The core innovation of this variable-structure three phase inverter lies in its ability to morph between different topologies by altering terminal connections and controlling insulated-gate bipolar transistors (IGBTs). The main circuit features a split-bus design with six capacitors (C1 to C6) and four variable-structure terminals (M1 to M4). Each phase leg consists of six IGBTs (e.g., Qa1 to Qa6 for phase A), allowing for flexible configuration. For a two-level three phase inverter, terminals M1 and M3 are connected, as well as M2 and M4, effectively paralleling capacitors C1 with C4, C2 with C5, and C3 with C6, and then connecting them in series. This results in a total DC bus capacitance of $2C/3$ if each capacitor has a value of $C$. In this mode, only the top and bottom IGBTs (e.g., Qa1 and Qa6) are switched complementarily, while the middle IGBTs remain off, producing output voltages that alternate between $0$ and $\pm U_{dc}/2$, where $U_{dc}$ is the DC input voltage. The space vector modulation for this two-level three phase inverter involves six active vectors and two zero vectors, as summarized in Table 1.
| Sector | Active Vectors | Zero Vectors | Modulation Waveform |
|---|---|---|---|
| I | UPNN, UPPN | UNNN, UPPP | M-shaped |
| II | UPPN, UPNN | UNNN, UPPP | M-shaped |
| … | … | … | … |
For a T-type three-level three phase inverter, terminals M1 and M4 are shorted to form the neutral point O. This configuration series-connects C4 and C5, parallels them with C1, and similarly series-connects C2 and C3, paralleling them with C6, yielding upper and lower DC bus capacitances of $3C/2$ each and a total capacitance of $3C/4$. This ensures balanced midpoint potential, mitigating voltage offset issues common in multi-level inverters. The IGBTs Qa2 and Qa3 are kept off, while Qa1, Qa4, Qa5, and Qa6 are controlled to generate output voltages at levels $0$, $\pm U_{dc}/2$, and $\pm U_{dc}$. The space vector diagram for this three-level three phase inverter divides into 6 major sectors and 36 minor sectors, with 27 vectors including redundant small vectors. The modulation strategy employs nearest-vector synthesis with equal splitting of redundant vectors to minimize current ripple. The volt-second balance equation for sector I-1, for instance, is given by:
$$U_{ref} T_s = U_{ONN} \frac{T_z}{4} + U_{PNN} \frac{T_x}{2} + U_{PON} \frac{T_y}{2} + U_{POO} \frac{T_z}{2} + U_{PON} \frac{T_y}{2} + U_{PNN} \frac{T_x}{2} + U_{ONN} \frac{T_z}{4}$$
where $T_s = T_z + T_x + T_y$ is the switching period, and $U_{ref}$ is the reference voltage vector. This results in a seven-segment modulation sequence that reduces harmonic distortion compared to the two-level approach.
In the dual T-type four-level three phase inverter configuration, all variable-structure terminals M1 to M4 are disconnected, allowing M1 and M4 to serve as connection points for two T-type legs. This creates a split-bus structure with output voltage levels at $\pm U_{dc}/3$, $\pm 2U_{dc}/3$, and $\pm U_{dc}$. However, this topology introduces challenges in maintaining capacitor voltage balance, as the midpoint voltages $U_{P’}$ and $U_{N’}$ can drift without proper control. To address this, a virtual space vector pulse width modulation (SVPWM) strategy is implemented, which synthesizes vectors that inherently balance the capacitor voltages by equally distributing the charging and discharging times for the intermediate levels. The virtual SVPWM for the four-level three phase inverter mirrors the three-level space vector diagram but incorporates additional levels for $U_{P’}$ and $U_{N’}$. For example, in sector I-1, the vectors $U_{VNN}$, $U_{PNN}$, $U_{PVN}$, and $U_{PVV}$ are used, corresponding to $U_{ONN}$, $U_{PNN}$, $U_{PON}$, and $U_{POO}$ in the three-level case. The volt-second balance is expressed as:
$$U_{ref} T_s = U_{VNN} \frac{T_z}{4} + U_{PNN} \frac{T_x}{2} + U_{PVN} \frac{T_y}{2} + U_{PVV} \frac{T_z}{2} + U_{PVN} \frac{T_y}{2} + U_{PNN} \frac{T_x}{2} + U_{VNN} \frac{T_z}{4}$$
This approach ensures that the capacitor voltages remain balanced over a fundamental cycle, though it may increase switching losses due to more frequent level transitions. The modulation waves for each phase in this four-level three phase inverter consist of three components (e.g., $m_{a1}$, $m_{a2}$, $m_{a3}$ for phase A), which are compared with three sets of stacked carriers in the FPGA to generate the driving signals for all six IGBTs per phase.
The hardware design of the variable-structure three phase inverter experimental platform is centered on a split-bus main circuit integrated onto a single printed circuit board (PCB) to minimize parasitic parameters. The DC bus comprises six electrolytic capacitors, each rated at 680 μF, with 20 kΩ, 3 W power resistors connected in parallel to assist in voltage balancing. The power switching devices are IGBTs (model FGL40N120AND), chosen for their high voltage and current handling capabilities. The driver circuits are designed on pluggable PCBs for easy maintenance and replacement, utilizing ACPL302J driver chips that provide protection against overcurrent and shoot-through faults by locking the outputs and disconnecting the relay in case of anomalies. The control board combines a TMS320F28335 DSP and a Xilinx XC3S400 FPGA, which work in tandem to execute control algorithms and modulation tasks. The DSP handles strategy computation, modulation wave calculation, and sampling via a 16-bit analog-to-digital converter (AD7656), while the FPGA generates carrier waves and driving signals. This division of labor leverages the DSP’s serial processing for complex calculations and the FPGA’s parallel processing for real-time signal generation, ensuring precise control of the three phase inverter across different topologies. The system also includes a sensor and relay board for voltage and current monitoring, a display for real-time data visualization via RS485 communication, and an adjustable DC power supply along with resistive-inductive loads for testing. Protection mechanisms are implemented in both software and hardware; the DSP monitors sampled data for overvoltage and overcurrent conditions, triggering the FPGA to disable PWM signals and open relays, while the driver chips provide additional hardware-based fault detection and response.
The collaborative operation between the DSP and FPGA is crucial for the adaptability of the three phase inverter platform. In the DSP, program initialization configures system clocks, GPIO, enhanced PWM (EPWM), and interrupts. The main function manages communication and display, awaiting external interrupts. When an interrupt occurs, the DSP reads AD7656 samples, performs protection checks, selects the appropriate modulation strategy based on the inverter topology, computes modulation waves, and sends them to the FPGA via a data bus. The FPGA, in turn, generates bidirectional triangular carrier waves. A carrier wave underflow triggers AD7656 sampling, which then generates an interrupt signal for the DSP. The FPGA compares the received modulation waves with the carriers to produce PWM signals, adding dead time to complementary drives to prevent shoot-through faults. In case of faults, the FPGA disables PWM and disconnects the relay. This seamless coordination enables the implementation of various SVPWM strategies for the three phase inverter, as detailed in Table 2.
| Topology | Modulation Type | Key Equations | Output Levels | Current THD |
|---|---|---|---|---|
| Two-Level | Standard SVPWM | $$U_{ref} T_s = U_{NNN} \frac{T_z}{4} + U_{PNN} \frac{T_x}{2} + U_{PPN} \frac{T_y}{2} + U_{PPP} \frac{T_z}{2} + \text{symmetric segments}$$ | 0, ±Udc/2 | ~7.2% |
| Three-Level | Nearest-Vector SVPWM | $$U_{ref} T_s = U_{ONN} \frac{T_z}{4} + U_{PNN} \frac{T_x}{2} + U_{PON} \frac{T_y}{2} + U_{POO} \frac{T_z}{2} + \text{symmetric segments}$$ | 0, ±Udc/2, ±Udc | ~4.9% |
| Four-Level | Virtual SVPWM | $$U_{ref} T_s = U_{VNN} \frac{T_z}{4} + U_{PNN} \frac{T_x}{2} + U_{PVN} \frac{T_y}{2} + U_{PVV} \frac{T_z}{2} + \text{symmetric segments}$$ | ±Udc/3, ±2Udc/3, ±Udc | ~6.1% |
Experimental validation of the variable-structure three phase inverter was conducted with a DC input from an adjustable power supply and a three-phase resistive-inductive load of 2.5 mH and 25 Ω. The modulation index was set to 0.95, switching frequency to 10 kHz, and dead time to 2 μs. For the two-level three phase inverter, connecting terminals M1-M3 and M2-M4 and applying standard SVPWM resulted in line voltages switching between 0 and $\pm U_{dc}/2$, with phase current total harmonic distortion (THD) values of approximately 7.06%, 7.12%, and 7.48%. The output waveforms exhibited typical two-level characteristics, confirming the effectiveness of the topology and modulation. For the T-type three-level three phase inverter, shorting M1 and M4 and implementing three-level SVPWM produced staircase line voltages at 0, $\pm U_{dc}/2$, and $\pm U_{dc}$, with current THD reduced to around 4.79%, 4.83%, and 5.14%. This demonstrates the superior harmonic performance of multi-level inverters. In the dual T-type four-level three phase inverter configuration, with all terminals disconnected and virtual SVPWM applied, the line voltages showed levels at $\pm U_{dc}/3$, $\pm 2U_{dc}/3$, and $\pm U_{dc}$. The capacitor voltages remained balanced throughout the cycle, indicating successful voltage regulation, though the current THD increased slightly to about 5.99%, 5.99%, and 6.34% due to the higher switching frequency and complexity of the modulation strategy. These results highlight the trade-offs between output quality and efficiency in four-level three phase inverters, underscoring the need for optimized modulation techniques to minimize losses.
The design of this variable-structure three phase inverter experimental platform offers significant advantages for research and education in power electronics. By enabling multiple inverter topologies on a single hardware setup, it reduces costs and space requirements while providing flexibility for exploring different modulation and control strategies. The use of DSP and FPGA allows for real-time implementation of advanced algorithms, such as SVPWM for two-level, three-level, and four-level three phase inverters, with robust protection features ensuring safe operation. Future work could focus on refining the modulation strategies to further reduce switching losses in four-level configurations and integrating adaptive control techniques for dynamic performance optimization. Overall, this platform serves as a versatile tool for investigating the characteristics of various three phase inverter topologies, contributing to the advancement of efficient and reliable power conversion systems.