In recent years, the adoption of photovoltaic (PV) power generation has become increasingly widespread, driven by the global shift towards renewable energy sources. The core component of any PV system is the solar inverter, which converts direct current (DC) from solar panels into alternating current (AC) suitable for grid integration. The performance, reliability, and efficiency of a solar inverter are heavily dependent on its controller design. As control strategies become more complex to meet grid standards and maximize energy harvest, the hardware architecture of the inverter controller must evolve. Traditional designs using single Digital Signal Processors (DSPs) or combinations like DSP+FPGA face challenges in balancing real-time control, computational load, human-machine interface (HMI), and communication tasks. This article presents a novel controller design for a solar inverter based on a multi-processor architecture centered around a TMS320F28335 DSP and two ARM Cortex-M3 microcontrollers. We will delve into the hardware system design, detailed circuit analysis, software framework, and control algorithms. Experimental results from a 10kW prototype validate the feasibility and effectiveness of this approach, demonstrating stable grid-tied operation with high precision.
The proposed solar inverter controller architecture aims to distribute functionalities intelligently across specialized processors to overcome limitations of previous designs. The TMS320F28335 DSP serves as the main control unit, handling high-speed, real-time tasks such as pulse-width modulation (PWM) generation, analog-to-digital conversion (ADC) of critical signals, and execution of core control algorithms like Maximum Power Point Tracking (MPPT) and grid synchronization. The first ARM microcontroller (referred to as ARM_SLAVE) acts as a safety and monitoring co-processor. It manages temperature sensing, additional fault detection, and can issue hardware-level lockout signals to enhance system protection. The second ARM (ARM_LCD) is dedicated exclusively to HMI and communication protocols, providing a responsive interface for parameter setting and data display without burdening the main control loop. This “DSP + Dual ARM” configuration offers a scalable, cost-effective solution with strong real-time performance, ease of development, and room for functional expansion, making it highly suitable for modern, grid-connected solar inverters.
The overall hardware system block diagram illustrates the synergy between these components. The solar inverter’s power stage is a two-level topology, beginning with a DC-DC boost converter for MPPT and voltage elevation, followed by a three-level inverter bridge for DC-AC conversion. An LCL filter connects the inverter output to the grid. The DSP interfaces directly with the power stage through gate driver circuits and samples key voltages and currents via sensor networks and signal conditioning circuits. It communicates with ARM_SLAVE via a serial communication interface (SCI) for exchanging safety thresholds and status data. Similarly, it uses another SCI channel to send operational data (power, voltage, frequency) and receive user commands from ARM_LCD. This structured division of labor ensures that the DSP’s computational resources are reserved for time-critical control loops, while the ARMs handle supervisory and interactive tasks, leading to a robust and efficient solar inverter controller.
Hardware System Architecture and Core Circuit Design
The hardware foundation of our solar inverter controller is built for precision, reliability, and isolation. The main control board hosts the DSP28335, the two LPC1768 ARM microcontrollers, and the peripheral circuits that interface with the high-voltage power stage. Key hardware modules include signal conditioning for current and voltage sensors, gate driver circuits, overcurrent protection hardware, and zero-crossing detection circuits. Each module is designed to ensure signal integrity, provide electrical isolation, and enable fast fault response.
Current Sensing and Signal Conditioning Circuit
Accurate current measurement is paramount for current control loop performance and protection. For grid current sensing, we employ high-precision current transformers (e.g., model 4640-X400 with a 1000:1 ratio). The secondary current is converted to a voltage across a precision resistor. This small AC voltage signal is then conditioned to match the DSP’s ADC input range (0-3V). The conditioning circuit uses operational amplifiers in two stages. The first stage is a voltage follower for buffering. The second stage adds a DC bias of 1.5V to the AC signal, shifting it into the positive range. Given the solar inverter’s rated output current of 15.15A RMS (peak ≈21.43A), the final conditioned voltage signal varies between approximately 0.071V and 2.928V. The design for one phase is representative of all three. The circuit also derives the maximum of the three-phase currents (IgridMAX) for centralized overcurrent protection. The transfer function for the conditioning stage can be summarized as:
$$ V_{out}(t) = G_{sensor} \cdot R_{sense} \cdot i_{grid}(t) + V_{bias} $$
Where \( G_{sensor} = 1/1000 \) is the sensor gain, \( R_{sense} = 100 \Omega \), and \( V_{bias} = 1.5V \).
Gate Driver Circuit for Power Switches
The PWM signals from the DSP are low-voltage logic signals incapable of driving Insulated-Gate Bipolar Transistor (IGBT) modules directly. The gate driver circuit provides the necessary voltage level shift, current amplification, and galvanic isolation. We use high-speed optocoupler-based driver ICs like the TLP350. This IC integrates an LED, a photodiode, and two MOSFETs in a push-pull configuration. When the DSP output signal (Drive_A) is high and its complement (Drive_K) is low, the internal LED turns on, causing the photodiode to conduct and activate the output MOSFETs. This applies the positive driver supply voltage (e.g., +15V) between the gate and emitter (Drive_G and Drive_S) of the IGBT, turning it on. When the DSP signals are reversed, the output applies a negative voltage (e.g., -8V) to the IGBT gate to ensure reliable turn-off. The circuit includes external resistors and Zener diodes for gate protection and speed optimization. The propagation delay of this driver is a critical parameter for the solar inverter’s switching accuracy and is kept minimal (typically under 500ns).
Overcurrent Protection (OCP) Hardware Circuit
To protect the solar inverter from catastrophic failure during fault conditions like short circuits, a dedicated, fast hardware protection circuit is implemented alongside software protection. This circuit takes the conditioned maximum current signal (IgridMAX) as input. This voltage signal is compared against a fixed reference voltage (e.g., 2.5V, corresponding to a current threshold) using a high-speed comparator. Under normal operation, the comparator output is high. If the current exceeds the threshold, the comparator output flips to low. This event triggers two actions almost simultaneously: 1) It pulls down a signal (SOCP) connected to a DSP interrupt pin, alerting the software, and 2) It turns on a transistor, generating a hardware signal (OUTOCP) that directly controls the output enable pins of buffer chips placed in the gate signal path. These buffer chips (e.g., 74VC541AW) have two active-low enable pins (OE1 and OE2). The OUTOCP signal and a temperature fault signal from ARM_SLAVE are connected to these enables. A fault on either line forces the buffer outputs to a high-impedance state, instantly blocking all gate drive signals to the IGBTs. This hardware “lockout” provides a safety net with response times in the microsecond range, independent of the DSP’s software loop.
Grid Voltage Zero-Crossing Detection Circuit
Precise grid synchronization is essential for a grid-tied solar inverter. A zero-crossing detection circuit converts the sinusoidal grid voltage into a digital square wave synchronized with its zero crossings. The grid voltage is stepped down and conditioned to a low-voltage AC signal. This signal is then fed into a comparator stage with hysteresis (to prevent noise-induced multiple transitions) where it is compared with the same 1.5V DC bias used earlier. When the AC voltage is positive relative to the bias, the comparator outputs a low logic level; when negative, it outputs high. The resulting square wave’s rising and falling edges correspond very closely to the actual grid voltage zero crossings. This signal is fed into a DSP capture (ECAP) pin. The DSP software uses interrupts on these edges to calibrate and synchronize its Phase-Locked Loop (PLL) software algorithm, ensuring the inverter’s output current is precisely in phase with the grid voltage.
Software Architecture and Control Algorithm Design
The software for this multi-processor solar inverter controller is modular and task-specific. The DSP runs the time-critical control loops at a fixed high frequency (e.g., 20 kHz), while the ARMs run lower-priority monitoring and interface tasks.
DSP28335 Main Control Program Flow
The DSP software begins with extensive initialization of its internal clocks, peripherals (PWM, ADC, SCI, ECAP, GPIO), and interrupt tables. After initialization, it enters a main supervisory loop. Key tasks executed within high-priority interrupt service routines (ISRs) include:
- Data Acquisition: At the 20 kHz rate, the ADC module samples DC-link voltage, PV voltage and current, three-phase grid voltages, and three-phase inverter output currents.
- Fault Monitoring: Sampled values are compared against software limits. Hardware fault signals (like SOCP) are also polled. Any fault triggers a protection sequence.
- Control Algorithm Execution: This includes the MPPT algorithm for the DC-DC stage, the DC-link voltage control loop (outer loop), the grid current control loop (inner loop), and the software PLL for grid synchronization.
- PWM Update: The outputs of the current control loop are used to update the duty cycles of the PWM modules driving the inverter bridge.
- Communication: The DSP packages system data (power, energy, status) and sends it to ARM_LCD via SCI. It also receives user-set parameters from ARM_LCD and sends safety limits to ARM_SLAVE.
A simplified state machine governs the overall system operation: WAIT -> CHECK (insulation, leakage current) -> BOOST (DC-link pre-charge) -> GRID-CONNECT (relay closure) -> RUN. Faults can cause a transition back to WAIT or to a complete STOP state.
Maximum Power Point Tracking (MPPT) Algorithm
The MPPT controller for the front-end boost converter is a hybrid algorithm combining the Constant Voltage (CV) method for startup and a variable-step Perturb and Observe (P&O) method for steady-state operation. This improves convergence speed and reduces steady-state oscillation around the Maximum Power Point (MPP). The algorithm logic is as follows:
Let \( V_{pv}(k) \) and \( I_{pv}(k) \) be the sampled PV voltage and current at step \( k \). The power is \( P_{pv}(k) = V_{pv}(k) \cdot I_{pv}(k) \). Let \( V_{ref} \) be the boost converter’s voltage reference command.
- Initialization/Startup (CV Method): Set a flag \( MPPT\_Const = 1 \). Set \( V_{ref} = 0.8 \cdot V_{oc} \), where \( V_{oc} \) is the measured open-circuit voltage of the PV array. This brings the operating point quickly near the MPP region.
- Steady-State (Variable-step P&O): When \( |V_{pv} – 0.8V_{oc}| \) is small, set \( MPPT\_Const = 0 \).
- Calculate power change: \( \Delta P = P_{pv}(k) – P_{pv}(k-1) \)
- Calculate voltage change: \( \Delta V = V_{pv}(k) – V_{pv}(k-1) \)
- The perturbation step size \( \Delta V_{step} \) is chosen based on \( |\Delta P| \):
- If \( |\Delta P| > P_1 \) (a large power change), use a large step \( \Delta V_{step1} \).
- If \( |\Delta P| \leq P_1 \), use a smaller step \( \Delta V_{step2} \).
- An even smaller step \( \Delta V_{step3} \) can be used when very close to MPP to minimize loss.
- The direction of perturbation is decided by the classic P&O rule: If \( \Delta P > 0 \), keep the same direction of voltage change; if \( \Delta P < 0 \), reverse the direction.
The algorithm ensures efficient energy harvest for the solar inverter under varying irradiation conditions. The following table summarizes the step sizes used in our implementation:
| Condition | Step Size | Purpose |
|---|---|---|
| Startup (CV phase) | \( \Delta V_{step\_cv} \) (e.g., 5V) | Fast approach to MPP region |
| \( |\Delta P| > P_1 \) | \( \Delta V_{step1} \) (e.g., 2V) | Fast tracking during rapid irradiance change |
| \( |\Delta P| \leq P_1 \) | \( \Delta V_{step2} \) (e.g., 0.5V) | Normal tracking |
| Very near MPP (optional) | \( \Delta V_{step3} \) (e.g., 0.1V) | Minimize steady-state oscillation |
Voltage and Current Double-Loop Control Strategy
The core of the solar inverter’s grid-tied operation is a cascaded control structure with an outer voltage loop and an inner current loop, implemented in the synchronous reference frame (dq-frame).
Outer Voltage Loop: This loop regulates the DC-link voltage (\( V_{dc} \)) to a stable reference value (\( V_{dcref} \)), which is primarily determined by the MPPT algorithm or can be set manually. The error is processed by a Proportional-Integral (PI) controller. The output of this PI controller is the reference for the d-axis current (\( i_{dref1} \)), which represents the active power component needed to maintain the DC-link voltage. An additional feedforward term (\( i_{dref2} \)) can be added based on estimated power balance to improve dynamic response. The total d-axis reference current is:
$$ i_{dref} = i_{dref1} + i_{dref2} = K_{p\_v}(V_{dcref} – V_{dc}) + K_{i\_v} \int (V_{dcref} – V_{dc}) dt + \frac{2 P_{pv}}{3 V_{gd}} $$
Where \( V_{gd} \) is the d-component of grid voltage, and \( P_{pv} \) is the PV power. The q-axis reference current (\( i_{qref} \)) is typically set to zero for unity power factor operation but can be set to a non-zero value for reactive power support if required.
Inner Current Loop: This faster loop forces the inverter output currents to follow the references \( i_{dref} \) and \( i_{qref} \). The measured three-phase grid currents (\( i_a, i_b, i_c \)) are transformed to the dq-frame using the Park transformation, synchronized to the grid voltage angle \( \theta \) provided by the PLL.
$$ \begin{bmatrix} i_d \\ i_q \end{bmatrix} = \frac{2}{3} \begin{bmatrix} \cos\theta & \cos(\theta – 2\pi/3) & \cos(\theta + 2\pi/3) \\ -\sin\theta & -\sin(\theta – 2\pi/3) & -\sin(\theta + 2\pi/3) \end{bmatrix} \begin{bmatrix} i_a \\ i_b \\ i_c \end{bmatrix} $$
The current errors (\( i_{dref} – i_d \), \( i_{qref} – i_q \)) are fed into PI controllers. The outputs of these PI controllers are the d and q components of the inverter output voltage references in the rotating frame (\( v_d^*, v_q^* \)). These are then transformed back to the stationary αβ-frame using the inverse Park transform, and finally to three-phase voltage references for the PWM modulator.
$$ \begin{bmatrix} v_\alpha^* \\ v_\beta^* \end{bmatrix} = \begin{bmatrix} \cos\theta & -\sin\theta \\ \sin\theta & \cos\theta \end{bmatrix} \begin{bmatrix} v_d^* \\ v_q^* \end{bmatrix} $$
The PI controllers for the current loop are tuned for high bandwidth to ensure accurate current tracking. The transfer function for the PI controller in the s-domain is:
$$ G_{PI}(s) = K_p + \frac{K_i}{s} $$
The gains \( K_p \) and \( K_i \) are designed considering the plant model (LCL filter impedance) and desired crossover frequency.
Software Phase-Locked Loop (PLL) for Grid Synchronization
Accurate knowledge of the grid voltage’s phase angle (\( \theta \)) is critical for the dq transformations. We implement a synchronous reference frame PLL (SRF-PLL). The three-phase grid voltages (\( v_a, v_b, v_c \)) are sampled and transformed to the αβ-frame (Clarke transform), and then to the dq-frame using an estimated angle \( \hat{\theta} \).
$$ \begin{bmatrix} v_\alpha \\ v_\beta \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix} \begin{bmatrix} v_a \\ v_b \\ v_c \end{bmatrix} $$
$$ \begin{bmatrix} v_d \\ v_q \end{bmatrix} = \begin{bmatrix} \cos\hat{\theta} & \sin\hat{\theta} \\ -\sin\hat{\theta} & \cos\hat{\theta} \end{bmatrix} \begin{bmatrix} v_\alpha \\ v_\beta \end{bmatrix} $$
In a balanced three-phase system, when \( \hat{\theta} \) matches the actual grid angle, \( v_q \) becomes zero. Therefore, the PLL control loop uses \( v_q \) as the error signal. A PI controller processes this error to adjust the estimated frequency (\( \hat{\omega} \)), which is then integrated to obtain \( \hat{\theta} \). A feedforward term of the nominal grid frequency (\( \omega_0 = 2\pi \cdot 50 \text{ or } 60 \text{ Hz} \)) is added to improve lock speed.
$$ \hat{\omega} = \omega_0 + \left( K_{p\_pll} v_q + K_{i\_pll} \int v_q \, dt \right) $$
$$ \hat{\theta} = \int \hat{\omega} \, dt \quad (\text{modulo } 2\pi) $$
This PLL structure provides a robust and accurate phase angle estimate even in the presence of minor grid distortions, which is essential for stable operation of the grid-connected solar inverter.
ARM Microcontrollers Software Design
ARM_SLAVE (Safety Co-processor): This ARM runs a loop that periodically reads temperature sensors attached to IGBT heatsinks and the cabinet interior. It compares these readings against limits received from the DSP. If a temperature exceeds its limit, it immediately asserts a hardware signal (S_INV_OFF) that, combined with the OCP signal, disables the gate driver buffers. It also sends a message to the DSP indicating the fault source. This dual-level protection (hardware + software) enhances the reliability of the solar inverter.
ARM_LCD (HMI Processor): This ARM manages a touch-screen display. It runs an embedded GUI application that allows users to set parameters (e.g., power limits, grid standards), view real-time data (power, voltage, current, energy yield, frequency), and acknowledge faults. It communicates with the DSP via SCI, requesting data packets at a lower rate (e.g., 10 Hz) and sending user commands asynchronously. This separation ensures that the display refresh and communication processing never interfere with the real-time control tasks of the DSP.
Experimental Validation and Performance Analysis
To validate the design, a 10kW prototype of the two-stage solar inverter was built and tested. The power stage consisted of IGBT modules for both the boost converter and the three-level NPC inverter. The control platform was the custom-designed board with DSP28335 and dual ARM LPC1768 chips. The solar inverter was connected to a programmable DC source (simulating PV panels) on the input and to the AC grid through an isolating circuit breaker on the output.
The experimental setup aimed to verify key performance metrics: output voltage quality, grid current synchronization, dynamic response, and protection functionality. Testing was conducted under various input DC voltages and output power levels.
Steady-State Waveforms and Data
The inverter output phase voltages were measured and found to be stable three-level waveforms with low harmonic distortion. The line-to-line voltage exhibited a nearly sinusoidal shape after the LCL filter. More critically, the grid currents injected by the solar inverter were measured. The three-phase currents were balanced and sinusoidal. The phase relationship between the grid voltage and the inverter current was analyzed to verify synchronization. The following table shows the measured phase difference between the grid voltage fundamental and the inverter current fundamental at different grid frequencies around the nominal 50 Hz, demonstrating excellent synchronization performance of the controller.
| Grid Frequency (Hz) | Absolute Phase Error φ (degrees) |
|---|---|
| 49.996 | 3.24 |
| 49.997 | 3.07 |
| 49.998 | 3.15 |
| 49.999 | 2.54 |
| 50.000 | 2.50 |
| 50.001 | 2.87 |
| 50.002 | 2.58 |
| 50.003 | 3.42 |
| 50.004 | 3.28 |
All phase errors are well below the typical limit of 5 degrees specified for grid-tied solar inverters, confirming the effectiveness of the SRF-PLL and current control loop.
The RMS values of the output line voltage and current were also logged over time during a steady-state operation at full power. The voltage RMS remained constant at approximately 233 V (for a 400V line-to-line system), and the current RMS was stable at around 15.1 A, corresponding to the expected 10kW output (for a balanced three-phase system: \( P = \sqrt{3} \cdot V_{LL} \cdot I_{L} \cdot \text{pf} \)).
Dynamic Performance and Protection Tests
The dynamic response was tested by applying step changes in the DC input power (simulating sudden changes in solar irradiation). The MPPT algorithm successfully tracked the new maximum power point within a few hundred milliseconds. The DC-link voltage showed minimal deviation during these transients, thanks to the well-tuned voltage loop. The grid current smoothly transitioned to the new power level while maintaining sinusoidal shape and synchronization.
Protection features were rigorously tested. An intentional overcurrent condition was created. The hardware protection circuit responded within 5 microseconds, blocking all gate signals and preventing any damage to the IGBTs. The DSP also registered the fault via its interrupt pin and executed a safe shutdown routine. Similarly, heating the IGBT heatsink beyond the setpoint triggered the ARM_SLAVE to assert its lockout signal, validating the multi-processor safety scheme. The solar inverter consistently demonstrated robust and reliable protection behavior.
Efficiency and Power Quality
While a full efficiency curve across the load range is beyond this article’s scope, the prototype solar inverter achieved a peak efficiency exceeding 97% at rated power. The Total Harmonic Distortion (THD) of the grid current was measured below 3% at full load, which meets international standards such as IEEE 1547 and EN 61000-3-2 for grid-connected inverters. This low THD is a direct result of the high switching frequency (set by the DSP’s PWM at 10-20 kHz), the LCL filter design, and the accurate current control loop.
Conclusion
This article has presented the comprehensive design and implementation of a high-performance controller for a solar inverter, utilizing a multi-core architecture based on a TMS320F28335 DSP and two ARM Cortex-M3 microcontrollers. The detailed hardware design of critical circuits—including signal conditioning, gate driving, fast protection, and synchronization—provides a solid foundation for reliable operation. The software architecture effectively partitions tasks: the DSP handles high-speed, deterministic control algorithms (MPPT, dual-loop current/voltage control, PLL), while the ARMs manage safety supervision and user interaction. This division leverages the strengths of each processor, leading to a controller that is both powerful and flexible.
The proposed control strategies, including a hybrid MPPT algorithm, synchronous frame PI controllers for voltage and current, and a software PLL, have been shown to deliver precise and stable performance. Experimental results from a 10kW prototype confirm the design’s viability. The solar inverter successfully generated high-quality three-phase AC power, synchronized accurately with the grid, and demonstrated robust responses to dynamic changes and fault conditions. The “DSP + Dual ARM” architecture proves to be an excellent solution for modern grid-tied solar inverters, balancing computational power, real-time performance, safety, and user accessibility. This design approach is scalable and can be adapted for solar inverters of different power ratings or for inverters with additional functionalities like battery energy storage integration, making it a valuable contribution to the advancement of renewable energy conversion systems.