In my work on modern power electronics, the proliferation of renewable energy sources has made the on-grid inverter a cornerstone of distributed generation systems. An on-grid inverter serves the critical function of converting direct current (DC) from sources like photovoltaic panels or batteries into alternating current (AC) that is synchronized with the utility grid. The quality of this conversion, characterized by low harmonic distortion and precise phase/frequency alignment, directly impacts grid stability and power quality. While traditional unipolar Sinusoidal Pulse Width Modulation (SPWM) techniques have been widely adopted, they often result in output waveforms with relatively high harmonic content and associated switching losses. To address these limitations, I designed and implemented a single-phase on-grid inverter system based on bipolar SPWM modulation. This design centers on an STM32 microcontroller, utilizes a full-bridge topology driven by dedicated gate drivers, and employs a dual-loop control strategy combined with phase-locked loop (PLL) technology to ensure high-quality, grid-synchronized output.
The overall system architecture for my single-phase on-grid inverter is structured into several key functional blocks. The core is the STM32F103C8T6 microcontroller, which generates the bipolar SPWM control signals. These signals are fed into two IR2110 high-side and low-side gate driver ICs. Each IR2110 produces a complementary pair of gate pulses, resulting in four driving signals for the MOSFETs in the full-bridge inverter circuit. This inverter stage chops the DC input into a high-frequency PWM waveform. An LC low-pass filter then attenuates the high-frequency switching components, leaving a fundamental 50/60 Hz sinusoidal voltage. The AC output is connected to both a local load and the utility grid via a coupling interface. Critical to the control are the voltage and current sampling circuits, which provide real-time feedback. This feedback is processed by the dual-loop (voltage outer loop, current inner loop) controller within the STM32. Simultaneously, a PLL algorithm tracks the grid voltage’s phase and frequency. The controller adjusts the SPWM modulation in real-time based on the feedback error and the synchronized grid reference, ensuring the inverter’s output current is precisely in phase with the grid voltage. A user interface with buttons and an OLED display allows for parameter adjustment and monitoring.
The heart of the control system for this on-grid inverter is the STM32F103C8T6 microcontroller. I selected this device for its ARM Cortex-M3 core, high-performance capabilities, and rich peripheral set crucial for power electronics. Its high-speed clock of up to 72 MHz allows for precise timing control, which is essential for generating high-resolution SPWM signals. The advanced control timer (TIM1) is particularly valuable as it can generate multiple complementary PWM outputs with programmable dead-time insertion—a vital feature to prevent shoot-through faults in the bridge legs. The built-in Analog-to-Digital Converter (ADC) is used to sample the output voltage and current feedback signals, forming the sensory input for the closed-loop control algorithms.
The power conversion stage is a standard single-phase full-bridge inverter, the workhorse of the on-grid inverter. It comprises four N-channel MOSFETs (Q1-Q4), each with an integral anti-parallel body diode for freewheeling current. The bridge is driven such that the diagonal pairs (Q1 & Q4) and (Q2 & Q3) switch alternately. When Q1 and Q4 are on, the output voltage is +Vdc. When Q2 and Q3 are on, the output voltage is -Vdc. By modulating the duty cycle of these states with a sinusoidal reference, a bipolar SPWM waveform is created at the bridge’s output terminals. A small resistor is placed in series with each MOSFET gate to dampen ringing and limit inrush current caused by the gate capacitance. The unfiltered output is a high-frequency square wave modulated at the amplitude of a sine wave. To recover the fundamental sine wave, a second-order LC low-pass filter is essential. The filter’s cutoff frequency ($f_c$) must be strategically placed between the fundamental frequency (e.g., 50 Hz) and the switching frequency (e.g., 20 kHz) to effectively attenuate switching harmonics while passing the desired output. The relationship is given by:
$$ f_c = \frac{1}{2\pi\sqrt{LC}} $$
For my design, I selected L = 3 mH and C = 1 µF, yielding a cutoff frequency of approximately 2.9 kHz, which provides sufficient attenuation for a 20 kHz switching frequency.
| Component | Part/Value | Key Function |
|---|---|---|
| Microcontroller | STM32F103C8T6 | SPWM generation, dual-loop control, PLL |
| Gate Driver | IR2110 (x2) | Isolates MCU, provides high-current gate drive |
| Power Switches | N-MOSFETs (e.g., IRF540) | Forms the full-bridge inverter stage |
| DC Link Voltage | 12 V (Design Example) | Input power source |
| Output Filter | L=3 mH, C=1 µF | Attenuates switching frequency harmonics |
| Switching Frequency | 20 kHz | Carrier frequency for SPWM modulation |
Driving the high-side MOSFETs in a bridge configuration requires a voltage referenced to the source terminal, which floats at the switching node potential. The IR2110 driver chip elegantly solves this challenge. It integrates a bootstrap circuit to generate the necessary floating supply for the high-side driver. In my on-grid inverter design, two IR2110 chips are used: one for the left bridge leg (Q1, Q2) and one for the right leg (Q3, Q4). The STM32’s PWM outputs are connected to the low-side (LIN) and high-side (HIN) input pins of each IR2110. The driver then produces the corresponding high-current, level-shifted outputs (LO and HO) to drive the MOSFET gates directly. An enable pin is connected to a microcontroller GPIO, allowing for a safe shutdown of all outputs if a fault is detected. The bootstrap diode and capacitor for each IR2110 are critical external components; they charge when the low-side switch is on, creating a local voltage source to turn on the high-side switch when needed.
Accurate feedback is the foundation of stable closed-loop control for an on-grid inverter. I designed separate sampling circuits for output voltage and current. For voltage sensing, a voltage transformer scales down the high-voltage AC output to a low-level signal. This signal is then conditioned by a precision operational amplifier circuit, which includes gain adjustment and clamping diodes for over-voltage protection before being fed to the STM32’s ADC input. Current sensing is similarly implemented, typically using a Hall-effect current sensor or a shunt resistor with differential amplification. The sampled instantaneous voltage $v_{fb}(t)$ and current $i_{fb}(t)$ are digitally processed by the microcontroller. The auxiliary power supply for the control circuitry is derived from the DC input using linear regulators like the AMS1117 to provide stable 5 V and 3.3 V rails.
The control strategy for a high-performance on-grid inverter must achieve two primary objectives: regulating the DC-link voltage (if applicable) and injecting a grid-synchronized sinusoidal current with low distortion. I employed a dual-loop control scheme, which is highly effective for this purpose. The outer loop is a voltage loop that maintains a stable DC bus voltage. Its output sets the amplitude of the current reference. The inner loop is a fast current loop that forces the inverter output current to track this reference precisely. For grid-tied operation, the current reference must be a pure sinusoid locked in phase with the grid voltage. This is achieved using a Phase-Locked Loop (PLL). The PLL continuously tracks the grid voltage’s phase angle $\theta_{grid}$, allowing the controller to generate a perfectly synchronized sinusoidal reference signal, $\sin(\theta_{grid})$.
The current controller in the inner loop is crucial. A standard Proportional-Integral (PI) controller performs well for DC signals but has limited gain at the AC fundamental frequency, leading to steady-state tracking error. Therefore, for an on-grid inverter, I used a Proportional-Resonant (PR) controller. An ideal PR controller has infinite gain at its resonant frequency $\omega_0$ (the grid frequency, e.g., 314 rad/s for 50 Hz), enabling zero steady-state error for sinusoidal signals at that frequency. The ideal transfer function is:
$$ G_{PR}(s) = K_p + \frac{2K_rs}{s^2 + \omega_0^2} $$
where $K_p$ is the proportional gain and $K_r$ is the resonant gain. In practice, a non-ideal (“quasi”) PR controller is used to improve robustness against slight frequency variations:
$$ G_{QPR}(s) = K_p + \frac{2K_r\omega_c s}{s^2 + 2\omega_c s + \omega_0^2} $$
Here, $\omega_c$ is a small cutoff frequency that widens the bandwidth around the resonant peak. The output of this controller, $u_{ctrl}(t)$, directly modulates the duty cycle of the SPWM signal.
| Control Loop | Controller Type | Primary Function | Key Parameters |
|---|---|---|---|
| Voltage (Outer) | PI Controller | Regulates DC-link voltage, sets current reference amplitude. | $K_{p,V} = 5$, $K_{i,V} = 50$ |
| Current (Inner) | Quasi-PR Controller | Tracks sinusoidal current reference with zero steady-state error. | $K_{p,I} = 0.1$, $K_{r,I} = 30$, $\omega_c = 10$ rad/s |
| Synchronization | Phase-Locked Loop (PLL) | Extracts grid voltage phase ($\theta_{grid}$) for reference generation. | Bandwidth, PI gains within PLL |
The voltage outer loop employs a standard PI controller. It compares the measured DC voltage (or an equivalent feedback from the AC side) $V_{dc,fb}$ with a reference $V_{dc,ref}$. The error is processed to produce the amplitude $I_{ref}^{*}$ for the current reference:
$$ I_{ref}^{*}(t) = K_{p,V} \cdot e_V(t) + K_{i,V} \int e_V(t) dt $$
where $e_V(t) = V_{dc,ref} – V_{dc,fb}(t)$. The complete synchronized current reference for the inner loop is then:
$$ i_{ref}(t) = I_{ref}^{*}(t) \cdot \sin(\theta_{grid}(t)) $$
The current error $e_I(t) = i_{ref}(t) – i_{fb}(t)$ becomes the input to the quasi-PR controller, completing the dual-loop control structure that ensures robust performance of the on-grid inverter under varying load and grid conditions.
The software implementation on the STM32 brings the hardware and control theory to life. The main program begins with comprehensive initialization of all peripherals: GPIO pins for PWM outputs and driver enable, the ADC for sampling, timers for PWM generation and system ticks, the PLL algorithm, and communication interfaces for the display. After initialization, the system enters an infinite loop that handles non-critical tasks like reading button presses to adjust output frequency or voltage setpoints, updating the OLED display with real-time parameters (input voltage, output frequency, amplitude), and implementing slow protection monitors.
The core real-time control tasks are executed inside a high-priority timer interrupt service routine (ISR), triggered at the switching frequency (e.g., 20 kHz). This ensures deterministic and timely updates. Within the ISR, the sequence of operations is critical:
- Sample: Read the latest ADC conversions for grid voltage, inverter output voltage, and output current.
- Protect: Check for over-current or over-voltage conditions. If a fault is detected, immediately disable the PWM outputs (via the driver enable pin) to protect the on-grid inverter.
- Synchronize: Execute the PLL algorithm using the sampled grid voltage to update the estimated grid phase angle $\theta_{grid}$.
- Control:
- Calculate the voltage loop PI controller output to determine the current amplitude reference $I_{ref}^{*}$.
- Generate the instantaneous current reference: $i_{ref} = I_{ref}^{*} \cdot \sin(\theta_{grid})$.
- Calculate the current error and process it through the quasi-PR controller to obtain the new modulating signal $m(t)$.
- Modulate: Update the PWM duty cycles for the next switching period based on $m(t)$ and the carrier waveform. In bipolar SPWM, this is implemented by comparing the sinusoidal modulating signal $m(t)$ with a high-frequency triangular carrier wave. The comparison determines the on/off states for the bridge switches, effectively encoding the sine wave into pulse widths.
- Repeat: Exit the ISR, waiting for the next interrupt to begin the cycle anew.
This interrupt-driven architecture ensures that the control loop for the on-grid inverter runs with minimal latency and high regularity, which is essential for stability and power quality.
Generating the bipolar SPWM signals efficiently is a key software task. The STM32’s advanced timer (TIM1) is configured in center-aligned PWM mode 1. The timer’s auto-reload register (ARR) defines the switching period. The core of SPWM generation is a pre-calculated sine table stored in memory. The table contains samples of a sine wave over one period. During each PWM interrupt (or using DMA for greater efficiency), a new value from this sine table, scaled by the modulating signal $m(t)$ from the controller, is written into the timer’s capture/compare registers (CCRx). This value sets the pulse width for that specific switching cycle. By updating the CCRx registers for multiple channels, the timer hardware automatically generates the complementary PWM waveforms with the inserted dead-time, driving the four switches of the full-bridge on-grid inverter.
To validate the design and performance of my bipolar SPWM based on-grid inverter, I constructed a hardware prototype and conducted a series of tests. A 12 V DC supply was used as the input source. The microcontroller was programmed with a switching frequency of 20 kHz. The inverter’s standalone performance was first verified. The output frequency was adjustable via the user interface from 2 Hz to 200 Hz in 1 Hz steps. The measured output frequency showed high accuracy, especially in the common power frequency range, as summarized in the table below. The filtered output voltage waveform was observed to be a clean, low-distortion sinusoid, confirming the effectiveness of the bipolar SPWM modulation and LC filter design.
| Set Frequency [Hz] | Measured Frequency [Hz] | Absolute Error [Hz] | Relative Error [%] |
|---|---|---|---|
| 50.0 | 49.95 | -0.05 | -0.10 |
| 60.0 | 59.87 | -0.13 | -0.22 |
| 75.0 | 74.72 | -0.28 | -0.37 |
| 100.0 | 99.51 | -0.49 | -0.49 |
The most critical test for an on-grid inverter is its synchronization and current injection capability. The prototype was connected to a low-voltage grid simulator. The oscilloscope captures demonstrated excellent performance: the inverter’s output current waveform was a clean sine wave. More importantly, this current waveform was perfectly in phase with the grid voltage waveform. The dual-loop control system successfully maintained this synchronization dynamically, and the current’s total harmonic distortion (THD) was measurably low. The system responded correctly to changes in the current reference (simulating varying available DC power), smoothly adjusting the injected current amplitude while maintaining unity power factor. This confirms the effectiveness of the combined PR current control and PLL synchronization in managing the grid-interactive behavior of the on-grid inverter.
In conclusion, the design and implementation of this single-phase on-grid inverter based on bipolar SPWM modulation have proven successful. Using the STM32 as a versatile control platform allowed for the integration of precise SPWM generation, sophisticated dual-loop control algorithms, and robust grid synchronization via a PLL. The bipolar modulation technique, compared to unipolar alternatives, contributed to a reduction in output harmonic content. The hardware design, centered on the IR2110-driven full-bridge and LC filter, is efficient and reliable. Experimental results confirm that the inverter provides stable, adjustable AC output with high frequency accuracy and, crucially, achieves excellent synchronization with the utility grid for high-quality power injection. This design offers a practical, low-cost, and high-performance solution for single-phase distributed energy systems, highlighting the continuous evolution and application of power electronics in enabling smarter and more resilient grids through advanced on-grid inverter technology.