1. Introduction
The demand for high-efficiency solar inverter has driven the adoption of advanced DC/DC boost topologies to accommodate higher voltage ratings. For 1500 V photovoltaic (PV) systems, conventional two-level boost converters face limitations due to excessive voltage stress on switching devices. This study focuses on the flying capacitor boost (FCB) circuit, a three-level topology that reduces voltage stress, enhances efficiency, and enables compact designs for string solar inverter. We present a systematic parameter design methodology, semiconductor selection criteria, and dynamic control strategies validated through simulations.
2. Circuit Topology and Operating Principles
2.1 Structure of the Flying Capacitor Boost Circuit
The FCB circuit (Figure 1) comprises:
- Input filter inductor L
- Input filter capacitor Cin
- Flying capacitor Cf
- Switching devices T1, T2, D1, and D2.
The flying capacitor Cf stabilizes at half the output voltage (Vout/2), reducing voltage stress on switches to Vout/2.
2.2 Operating Modes
The FCB operates in four modes based on the states of T1 and T2:
- Mode 1 (T1-OFF, T2-ON): Energy stored in L; Cf charges.
- Mode 2 (T1-ON, T2-OFF): Energy transferred to Vout; Cf discharges.
- Mode 3 (T1, T2-OFF): Inductor current freewheels through diodes.
- Mode 4 (T1, T2-ON): Inductor stores energy without Cf interaction.
The operation splits into two cases based on duty cycle D:
- Case 1 (D≤0.5): Sequence: Mode 1 → Mode 3 → Mode 2 → Mode 3.
- Case 2 (D>0.5): Sequence: Mode 1 → Mode 4 → Mode 2 → Mode 4.
3. Parameter Design Methodology for Solar Inverter
3.1 Semiconductor Device Selection
Key Requirements:
- Voltage Rating: Withstand Vout/2+ΔVce,max.
- Current Rating: Handle peak and RMS currents.
For a 1500 V solar inverter:
- Vce=1.15×21300+200=947.5V
- Ice=1.1×60=66A
A 950 V/145 A IGBT module (Table 1) was selected, validated for thermal performance.
Table 1: IGBT Module Parameters
| Parameter | Value |
|---|---|
| Voltage Rating | 950 V |
| Current Rating | 145 A |
| Thermal Resistance (IGBT) | 0.34 K/W |
| Thermal Resistance (Diode) | 0.57 K/W |
3.2 Input Filter Inductor Design
Inductor ripple current ΔIL is maximized at D=0.25 or D=0.75:ΔIL,max=16LfVout(Peak-to-peak)
To limit ΔIL,max≤0.6Iin,max:L≥16f×0.6Iin,maxVout=150μH
Simulation results showed ΔIL,max=31.4A (vs. limit: 36 A).
3.3 Input Filter Capacitor Design
The capacitor must suppress high-frequency ripple reflected to the PV source. For a 2% ripple current limit:Rr+1/(2ωCin)1/(2ωCin)<0.02
Additionally, voltage ripple ΔVin is governed by:Cin≥16fΔVinΔIL,max=14μF
Simulated ΔVin=11.17V (vs. limit: 20 V).
3.4 Flying Capacitor Design
Cf must limit voltage ripple ΔVf to <10% of Vout/2:Cf≥0.1Voutf2IL,max×(0.5−∣0.5−D∣)
At D=0.5, Cf=42μF achieved ΔVf=16.14V (vs. limit: 65 V).
4. Dynamic Control Strategy
A dual-loop control ensures stable inductor current (iL) and flying capacitor voltage (VCf):
- Outer Loop: Adjusts T2’s duty cycle (x2) to regulate iL.
- Inner Loop: Fine-tunes T1’s duty cycle (x1=x2+δ) to maintain VCf=Vout/2.
State-Space Equations:LdtdiL=Vin+VCf(x1−x2)−Vout(1−x2)CfdtdVCf=−iL(x1−x2)
5. Simulation and Validation
A 1500 V solar inverter prototype was simulated under Vin=800–1300V, Vout=1300V, and f=16kHz. Key results include:
Table 2: Simulated Performance vs. Design Limits
| Parameter | Design Limit | Simulation Result |
|---|---|---|
| Inductor Ripple | 36 A | 31.4 A |
| Input Capacitor Ripple | 20 V | 11.17 V |
| Flying Capacitor Ripple | 65 V | 16.14 V |
Waveforms confirmed stable operation with minimal voltage/current deviations (Figures 2–4).
6. Conclusion
This study presents a comprehensive design methodology for flying capacitor boost circuits in 1500 V solar inverter. Key contributions include:
- Optimal parameter selection for L, Cin, and Cf.
- Semiconductor device selection based on voltage/current stresses.
- Dual-loop control ensuring stability under dynamic conditions.
The proposed approach enhances efficiency, reduces component stress, and validates the FCB topology’s suitability for high-voltage PV systems. Future work will explore hardware implementation and loss optimization for commercial solar inverter.