In recent years, the adoption of photovoltaic (PV) systems has surged globally, driven by the need for sustainable energy solutions. A critical component in these systems is the solar inverter, which converts DC power from PV panels into AC power for grid integration. Among various inverter topologies, transformerless solar inverters have gained significant attention due to their compact size, lower cost, and higher efficiency compared to isolated counterparts. However, the absence of galvanic isolation introduces challenges, particularly the generation of common mode currents, which can lead to electromagnetic interference (EMI), safety hazards, and reduced system reliability. This paper focuses on addressing these issues in three-phase current source solar inverters, a topology that offers inherent advantages such as elimination of electrolytic capacitors and avoidance of shoot-through faults, thereby enhancing longevity and robustness in solar energy applications.
Current source solar inverters differ fundamentally from voltage source inverters by utilizing an inductive DC link to maintain a stable current, rather than a capacitive DC bus. This characteristic makes them suitable for PV systems where reliability and durability are paramount. However, like all transformerless solar inverters, they are susceptible to common mode currents due to the parasitic capacitance between the PV panels and ground. These currents flow through the stray capacitances, creating leakage paths that can trip ground fault protection devices and pose electric shock risks. Therefore, developing effective suppression techniques for common mode currents is essential for the widespread deployment of transformerless solar inverters in residential, commercial, and industrial PV installations.
The topology under investigation is a three-phase seven-switch H7 current source solar inverter, as illustrated in the system diagram. This configuration incorporates an additional switch (S7) compared to traditional six-switch designs, providing enhanced control flexibility for mitigating common mode voltages. The DC side consists of PV panels with a parasitic capacitance \(C_{PV}\) to ground, while the AC side connects to the grid through filter inductors and capacitors. The key switches (S1 to S6) are arranged in a bridge configuration, with S7 positioned to enable alternative current paths. This structure is representative of advanced solar inverters aimed at improving performance in grid-tied applications.
To analyze the common mode behavior, we establish a high-frequency common mode model for the solar inverter system. The common mode voltage \(V_{CM}\) is defined as the average of the voltages at points P and N relative to ground, expressed as:
$$V_{CM} = \frac{V_{PO} + V_{NO}}{2}$$
Here, \(V_{PO}\) and \(V_{NO}\) are the voltages from points P and N to the ground reference O, respectively. The common mode current \(I_{CM}\) flows through the parasitic capacitance \(C_{PV}\) and is driven by \(V_{CM}\). The model simplifies the system to a series circuit comprising \(C_{PV}\), the DC link inductance \(L_d\), and the equivalent impedance of the grid connection. By examining the switching states, we can derive \(V_{CM}\) for each state, as summarized in Table 1. This analysis reveals that traditional modulation schemes generate high \(V_{CM}\) magnitudes, leading to significant \(I_{CM}\), whereas proposed strategies aim to minimize these values.
| Space Vector | Conducting Switches | Common Mode Voltage \(V_{CM}\) |
|---|---|---|
| I₁ | S1, S6 | \(-V_c/2\) |
| I₂ | S2, S1 | \(-V_b/2\) |
| I₃ | S3, S2 | \(-V_a/2\) |
| I₄ | S4, S3 | \(-V_c/2\) |
| I₅ | S5, S4 | \(-V_b/2\) |
| I₆ | S6, S5 | \(-V_a/2\) |
| I₇ | S1, S4 | \(V_a\) |
| I₈ | S3, S6 | \(V_b\) |
| I₉ | S5, S2 | \(V_c\) |
| I₁₀ | S7 | 0 |
Modulation strategies play a pivotal role in controlling common mode currents in solar inverters. Space vector modulation (SVM) is widely used for current source solar inverters due to its ability to manage output currents and voltages efficiently. The conventional SVM approach, referred to as Solution I, employs two active vectors and one zero vector to synthesize the reference current vector. For instance, in sector 1, vectors I₁, I₂, and I₇ are used with dwell times calculated as:
$$T_1 = T_s m \sin\left(\frac{\pi}{6} – \theta\right)$$
$$T_2 = T_s m \sin\left(\frac{\pi}{6} + \theta\right)$$
$$T_0 = T_s – T_1 – T_2$$
where \(T_s\) is the switching period, \(m\) is the modulation index (\(m = I_{ref}/I_d\)), and \(\theta\) is the vector angle. However, this method results in a high \(V_{CM}\) because the zero vector I₇ produces a voltage equal to the phase voltage, doubling the magnitude compared to active vectors. To address this, Solution II introduces virtual zero vectors by combining active vectors with opposite directions, such as I₁ and I₄, to achieve a net zero output while reducing \(V_{CM}\). The dwell times for this scheme are adjusted as:
$$T_1 = T_s m \sin\left(\frac{\pi}{6} – \theta\right) + \frac{T_0}{2}$$
$$T_2 = T_s m \sin\left(\frac{\pi}{6} + \theta\right)$$
$$T_4 = \frac{T_0}{2}$$
Although Solution II lowers \(V_{CM}\), it leads to bipolar current pulses in the inverter output, degrading differential mode performance. Therefore, we propose a novel SVM strategy, Solution III, which utilizes the zero vector I₁₀ (with S7 conducting) to maintain low \(V_{CM}\) while ensuring three-level current waveforms. The dwell times for Solution III in sector 1 are:
$$T_1 = T_s m \sin\left(\frac{\pi}{6} – \theta\right)$$
$$T_2 = T_s m \sin\left(\frac{\pi}{6} + \theta\right)$$
$$T_{10} = T_s – T_1 – T_2$$
This approach effectively minimizes common mode voltages without compromising the output current quality, making it suitable for high-performance solar inverters. The mathematical formulation for the current space vectors is derived from the phase currents \(i_a\), \(i_b\), and \(i_c\), given by:
$$I(t) = \frac{2}{3}\left[i_a(t) + i_b(t)e^{j\frac{2\pi}{3}} + i_c(t)e^{j\frac{4\pi}{3}}\right]$$
For the H7 solar inverter, the ten space vectors correspond to specific switch states, as shown in Table 1. The active vectors (I₁ to I₆) have magnitudes of \(\frac{2}{\sqrt{3}}I_d\) and are spaced 60 degrees apart, while the zero vectors (I₇ to I₁₀) result in zero output current. By leveraging these vectors strategically, we can suppress common mode currents in transformerless solar inverters.
Experimental validation was conducted on a prototype solar inverter system to evaluate the proposed modulation strategies. The setup included a digital control platform based on TMS320F28335 DSP and EP4CE10E22C8 FPGA, with power switches using IGBTs and diodes. Key parameters were: switching frequency \(f_s = 10\) kHz, DC link inductance \(L_d = 5\) mH, DC current \(I_d = 8\) A, AC filter capacitance \(C = 66\) μF, and parasitic capacitance \(C_{PV} = 220\) nF. The solar inverter was connected to a grid simulator to emulate real-world conditions. Results from Solution I showed a peak common mode voltage exceeding 300 V, which induced common mode currents above 300 mA, violating safety standards such as VDE-0126-1-1. In contrast, Solution II reduced \(V_{CM}\) significantly, but the output currents exhibited bipolar pulses, leading to increased harmonic distortion. Solution III demonstrated superior performance, with \(V_{CM}\) maintained below 150 V and common mode currents limited to under 300 mA, while preserving three-level current waveforms for improved grid compatibility.
The effectiveness of the proposed solar inverter design is further analyzed through mathematical modeling of the common mode circuit. The common mode current \(I_{CM}\) can be expressed as:
$$I_{CM} = \frac{V_{CM}}{Z_{CM}}$$
where \(Z_{CM}\) is the impedance of the common mode path, dominated by \(C_{PV}\) and the inductances at high frequencies. Assuming a sinusoidal grid voltage with phase voltages \(V_a\), \(V_b\), and \(V_c\), the common mode voltage for different switching states can be computed. For example, during the conduction of S1 and S6, \(V_{CM} = -V_c/2\), where \(V_c = V_m \sin(\omega t + 120^\circ)\). By integrating these over a switching cycle, we derive the RMS common mode voltage as:
$$V_{CM,RMS} = \sqrt{\frac{1}{T_s} \int_0^{T_s} V_{CM}^2 dt}$$
This calculation confirms that Solution III yields the lowest \(V_{CM,RMS}\), aligning with experimental observations. Additionally, the output current quality is assessed using total harmonic distortion (THD), defined as:
$$THD = \frac{\sqrt{\sum_{n=2}^{\infty} I_n^2}}{I_1}$$
where \(I_n\) is the nth harmonic component and \(I_1\) is the fundamental current. Solution III achieves a THD below 5%, meeting grid codes for solar inverters, whereas Solution II results in higher THD due to bipolar pulses. These metrics underscore the advantages of the H7 topology in advancing solar inverter technology.
Beyond modulation, the choice of semiconductor devices impacts the performance of solar inverters. The H7 solar inverter can employ reverse-blocking IGBTs (RB-IGBTs) to eliminate series diodes, reducing conduction losses and enhancing efficiency. The on-state voltage drop \(V_{CE}\) for an IGBT is modeled as:
$$V_{CE} = V_{th} + R_{on} I_C$$
where \(V_{th}\) is the threshold voltage, \(R_{on}\) is the on-resistance, and \(I_C\) is the collector current. By using RB-IGBTs, the overall power loss \(P_{loss}\) in the solar inverter decreases, improving the system’s energy conversion efficiency \(\eta\), given by:
$$\eta = \frac{P_{out}}{P_{in}} \times 100\%$$
where \(P_{out}\) is the AC output power and \(P_{in}\) is the DC input power from the PV panels. This consideration is crucial for maximizing the yield of solar power systems, especially in large-scale installations where efficiency gains translate to significant economic benefits.
Comparative analysis with other transformerless solar inverter topologies, such as H5, H6, and HERIC designs, reveals that the H7 current source solar inverter offers a unique balance of common mode suppression and reliability. Voltage source solar inverters often rely on large DC-link capacitors, which have limited lifespan and pose reliability concerns. In contrast, current source solar inverters inherently avoid these issues, making them suitable for long-term operation in harsh environments. The proposed modulation strategy further enhances this advantage by addressing common mode currents without adding passive components or complex circuitry, keeping the system cost-effective and simple.
Future work on solar inverters could explore adaptive modulation techniques that dynamically adjust switching patterns based on grid conditions and PV output variations. Machine learning algorithms could be integrated into the control system to optimize performance in real-time, further reducing common mode currents and improving efficiency. Additionally, the integration of energy storage systems with solar inverters, as hinted by the hybrid inverter image, presents opportunities for developing multifunctional solar inverters that support grid stability and energy management.
In conclusion, this research demonstrates a novel approach to common mode current suppression in transformerless three-phase H7 current source solar inverters. Through detailed modeling and analysis, we have shown that the proposed space vector modulation strategy (Solution III) effectively minimizes common mode voltages while maintaining high-quality output currents. Experimental results validate the feasibility of this method, with common mode currents reduced below the 300 mA threshold specified by safety standards. The H7 topology, combined with advanced modulation, represents a significant step forward in the design of reliable and efficient solar inverters for modern PV systems. As the demand for renewable energy grows, such innovations will play a vital role in enhancing the performance and adoption of solar power technologies worldwide.