In modern photovoltaic (PV) systems, transformerless solar inverters are highly favored due to their compact size, reduced cost, and higher efficiency. However, the absence of galvanic isolation creates a parasitic path between the PV panels, the ground, and the grid, leading to significant leakage currents. This issue becomes particularly critical for safety, electromagnetic compatibility (EMC), and overall system reliability. Among various topologies, impedance source (Z-source) solar inverters offer a unique single-stage power conversion solution with inherent buck-boost capability and improved immunity to shoot-through faults, eliminating the need for dead-time insertion. This paper delves into the common-mode behavior of a transformerless three-phase four-leg Z-source solar inverter. I will establish a comprehensive common-mode model, analyze the factors influencing leakage current, and propose a novel modulation strategy designed to maintain a constant common-mode voltage, thereby effectively suppressing leakage current. Experimental results from a hardware prototype validate the effectiveness of the proposed approach for solar inverter applications.
The core circuit of the Z-source four-leg solar inverter under investigation is shown in the schematic below. The network formed by diodes VD1, VD2, inductors Lz1, Lz2, and capacitors Cz1, Cz2 constitutes the impedance network. The parasitic capacitance between the PV array and the ground is represented by Cpv.
The operational principle of Z-source solar inverters hinges on two distinct states: the shoot-through (ST) state and the non-shoot-through (NST) state. Assuming symmetric components (Lz1 = Lz2 = Lz, Cz1 = Cz2 = Cz) and steady-state operation, the voltages across the capacitors and inductors are equal:
$$ V_{C1} = V_{C2} = V_C $$
$$ V_{L1} = V_{L2} = V_L $$
During the NST state, the inverter bridge is connected to the DC source and the Z-network. The inductor voltage and the output voltage of the Z-source network, Vi, are given by:
$$ V_L = V_{dc} – V_C $$
$$ V_i = V_{dc} – 2V_L = 2V_C – V_{dc} $$
If T0 and T1 are the durations of the ST and NST states within a switching period Ts (Ts = T0 + T1), and the shoot-through duty cycle is defined as d = T0/Ts, applying the volt-second balance principle to the inductor yields:
$$ \frac{T_0 V_C + T_1 (V_{dc} – V_C)}{T_s} = 0 $$
Solving these equations provides the key steady-state relationships for the solar inverter:
$$ V_C = \frac{1 – d}{1 – 2d} V_{dc} = B_B \cdot V_{dc} $$
$$ V_i = \frac{1}{1 – 2d} V_{dc} = B \cdot V_{dc} $$
$$ B = \frac{1}{1-2d}, \quad B_B = \frac{1-d}{1-2d} $$
Here, B is the boost factor, demonstrating the single-stage boost capability crucial for solar inverters when the PV voltage is lower than the required grid voltage. During the ST state, the inverter bridge is shorted, diodes VD1 and VD2 are reverse-biased, isolating the PV panels from the inverter, and the capacitors discharge energy into the inductors.
The primary challenge for transformerless solar inverters is the leakage current. To analyze this, I derive the common-mode (CM) loop model for the four-leg Z-source topology. When the system is in the ST state, the diodes are off, breaking the CM path. Therefore, leakage current only flows during NST states. Applying Kirchhoff’s laws to the CM model during an NST state, the voltage across the parasitic capacitor Cpv can be expressed as a function of key system voltages:
$$ V_{Cpv} = V_{PV} – V_{CM} = \frac{2L}{2(L+L_z)+C} \left( V_{L2} + \frac{V_{C4}}{2} \right) $$
Where Vcm is the common-mode voltage defined as the average of the four leg voltages (VAN, VBN, VCN, VDN). The leakage current i_cm is then:
$$ i_{cm} = -C_{pv} \frac{dV_{Cpv}}{dt} $$
Further analysis shows that Vc4 itself is intricately linked to Vcm. Since Vl2 is constant during a steady-state NST interval, the primary variable causing high-frequency dv/dt across Cpv, and hence leakage current, is the common-mode voltage Vcm. Therefore, the strategy for leakage current suppression in this solar inverter focuses on maintaining a constant Vcm during all NST states.
I analyzed all 16 possible NST switching states for the four-leg bridge. The common-mode voltage for each state is summarized in the table below. The states are represented by the switching signals for legs A, B, C, and D (e.g., ‘1100’ means upper switches of legs A and B are ON, and lower switches of legs C and D are ON).
| Switching State | Common-Mode Voltage (Vcm) |
|---|---|
| 1111 | $$B_B V_{dc}$$ |
| 1110, 1101, 1011, 0111 | $$(2B_B+1)V_{dc}/4$$ |
| 1100, 1001, 0011, 0101, 1010, 0110 | $$V_{dc}/2$$ |
| 0001, 0010, 0100, 1000 | $$(3-2B_B)V_{dc}/4$$ |
| 0000 | $$(1-B_B)V_{dc}$$ |
Critically, only the six states highlighted in the table (1100, 1001, 0011, 0101, 1010, 0110) yield a constant common-mode voltage of Vdc/2, independent of the boost factor B or shoot-through duty cycle d. During the ST state, all leg voltages are equal, resulting in Vcm = Vdc/2 as well. A viable modulation strategy for a leakage-free solar inverter must, therefore, ensure that only these six NST states are used, while effectively integrating the required shoot-through states for boost control.
The conventional modulation for Z-source solar inverters interleaves shoot-through periods within the traditional zero states. This method, while providing boost, utilizes all eight active and zero vectors of the three-phase bridge. The fourth leg is typically modulated with a zero-sequence signal to increase DC bus utilization. In such a scheme, the NST states include vectors like 111, 000, 110, etc., leading to Vcm values that vary between BBVdc, (2BB+1)Vdc/4, (3-2BB)Vdc/4, and (1-BB)Vdc within a switching cycle. This high-frequency oscillation of Vcm excites the resonant LC circuit formed by the filter/parasitic components and the PV capacitance, generating substantial leakage current, as confirmed by the later experimental results.
To overcome this limitation, I propose a novel modulation strategy specifically designed for the four-leg Z-source solar inverter. The core idea is to completely avoid the traditional zero vectors (111 and 000 for the first three legs) during NST periods. Instead, the required “zero” state is achieved by using a combination of active vectors and the fourth leg. The modulation for the first three legs (A, B, C) is organized by sector:
| Sector | Carrier for ma | Carrier for mb | Carrier for mc |
|---|---|---|---|
| A1, A2, A3 | -Vtri | Vtri | -Vtri / Vtri |
| A4, A5, A6 | Vtri | -Vtri / Vtri | Vtri / -Vtri |
Where Vtri and -Vtri are two triangular carriers 180 degrees out of phase. This arrangement ensures that the output states for legs A, B, and C are always one of the six active vectors (100, 110, 010, 011, 001, 101). The traditional zero-vector time is effectively converted partly into shoot-through time and partly into the adjacent active vectors (e.g., 010 and 101).
The switching signal for the fourth leg (D) is then derived logically to enforce the condition of having exactly two upper switches and two lower switches ON at any NST instant. This is achieved by an XOR operation on the first three leg’s upper switch signals:
$$ S_7 = S_1 \oplus S_3 \oplus S_5 $$
This guarantees that the resulting four-leg state is always one of the six with constant Vcm = Vdc/2, such as 1100 or 1010. The shoot-through states are inserted by simultaneously turning on all lower switches (or all upper switches) of the four-leg bridge without affecting the CM voltage condition. This proposed modulation seamlessly integrates the boost function of the Z-source solar inverter with inherent constant common-mode voltage operation, effectively decoupling the leakage current path.
To validate the analysis and the proposed modulation strategy for the solar inverter, I constructed a laboratory prototype. The system parameters were: Input DC voltage Vdc = 120V, Z-source inductance Lz = 3mH, Z-source capacitance Cz = 940μF, switching frequency fs = 20kHz, output filter inductance Lf = 5mH, filter capacitance Cf = 9.9μF, shoot-through duty cycle d = 0.2, and parasitic PV capacitance Cpv = 300nF. A digital platform using a TMS320F28335 DSP and a Xilinx FPGA XC3S400 implemented the control algorithms.
First, I tested the conventional modulation. The Z-source network successfully boosted the voltage. With Vdc=120V and d=0.2, the theoretical boost factor B is 1/(1-2*0.2)=1.667, giving an expected DC-link voltage Vi of 200V, which aligned with the measured value. The output line-to-line voltages and currents were sinusoidal with low distortion. However, the bridge output voltages (e.g., VAN) and the voltage across the parasitic capacitor (Vcpv) showed high-frequency switching noise. Most importantly, the measured leakage current had a peak value exceeding 300mA and an RMS value of 253mA, which fails to meet stringent safety standards like VDE-0126-1-1.
Subsequently, I implemented the proposed modulation strategy on the same solar inverter hardware. The Z-source output voltage remained correctly boosted to approximately 200V. The AC output voltage and current waveforms maintained high quality. The critical difference was observed in the common-mode behavior. The bridge voltages now switched only among the six specific states during NST periods. Consequently, the voltage across the parasitic capacitor, Vcpv, became a clean 50Hz sinusoidal waveform with negligible high-frequency ripple. The corresponding leakage current was drastically reduced to a peak value well below 300mA and an RMS value of only 22.5mA. This significant reduction brings the system into full compliance with the VDE-0126-1-1 standard, demonstrating the superior performance of the proposed method for transformerless solar inverters.
The experimental comparison clearly demonstrates the limitations of the conventional Z-source modulation in transformerless solar inverter applications regarding leakage current. The variation of common-mode voltage with the shoot-through duty cycle excites the parasitic resonance. In contrast, the proposed four-leg topology combined with the novel modulation strategy provides an effective solution. By strategically using only the switching states that yield a constant common-mode voltage of Vdc/2 during both shoot-through and non-shoot-through intervals, the high-frequency excitation across the PV parasitic capacitance is eliminated. This approach successfully integrates the desirable single-stage boost feature of Z-source solar inverters with excellent leakage current suppression capability, enhancing the safety and EMC performance of transformerless PV systems. Future work could explore the application of this principle to other impedance network based or quasi-Z-source solar inverter topologies.