The pervasive integration of power electronic-based generation, particularly from photovoltaic (PV) sources, has fundamentally altered the dynamics of modern power systems. A solar inverter, as the critical interface between the PV array and the grid, must maintain stable operation not only under ideal conditions but also during grid disturbances. Among these, voltage sags (dips) are one of the most frequent and consequential power quality events. While significant research exists on the low-voltage ride-through (LVRT) capabilities of solar inverters as mandated by grid codes, these requirements often specify a single, simplified voltage-time profile. This approach overlooks the multifaceted nature of real-world voltage sags and the nuanced response of the inverter’s internal controls and protections. My research aims to bridge this gap by proposing and implementing a comprehensive methodology for characterizing the voltage sag tolerance of solar inverters, moving beyond the conventional two-dimensional view to a feature-vector-based assessment and introducing the concept of Process Immunity Time (PIT) for a more accurate representation.
A voltage sag is typically defined as a reduction in the root-mean-square (RMS) voltage to between 0.1 and 0.9 pu for a duration from half a cycle to one minute. The traditional characterization focuses solely on magnitude (\(V_{sag}\)) and duration (\(T_{sag}\)). However, the transient behavior of a solar inverter, a sophisticated switching device, is sensitive to the precise instantaneous conditions at the moment of disturbance inception and recovery. This introduces a third critical feature: the Point-on-Wave (POW). The POW is the phase angle of the fundamental voltage waveform at the instant the sag begins (initial POW, \(\theta_i\)) and ends (final POW, \(\theta_f\)). The initiation of a sag at a voltage zero-crossing versus a peak, for instance, imposes drastically different initial conditions on the inverter’s phase-locked loop (PLL) and current controllers, potentially leading to divergent stability outcomes.
Therefore, to accurately model the stress on a solar inverter, a voltage sag event (\(S\)) should be described by a feature vector:
$$ S = [V_{sag}, T_{sag}, \theta_i, \theta_f, \Delta\phi, \ldots] $$
where \(\Delta\phi\) represents phase-angle jump, and other elements could include harmonic distortion or unbalance. For this study, the primary vector under consideration is \(S = [V_{sag}, T_{sag}, \theta_i]\). The susceptibility of equipment to POW has been noted in standards like IEC 61000-4-30 and demonstrated for devices like contactors and drives. Extending this understanding to solar inverters is crucial for a complete resilience assessment.
The industry-standard method for depicting equipment susceptibility is the Voltage Tolerance Curve (VTC), often exemplified by the ITIC (CBEMA) or SEMI F47 curves. It plots the boundary of voltage magnitude versus duration that separates normal operation from malfunction. While useful, the VTC is an equipment-centric, electrical-state representation. It implies a binary outcome—trip or survive—and is typically derived for a single, unspecified POW. In reality, the “malfunction” of a solar inverter is often the result of an internal protection (e.g., overcurrent, DC overvoltage) being triggered after a delay. This delay is the core of the Process Immunity Time (PIT) concept. PIT shifts the focus to a critical process variable (e.g., inverter output current, DC-link voltage). It is defined as the time interval between the onset of a voltage sag and the moment a specified process parameter (\(P\)) crosses a limiting threshold (\(P_{limit}\)), causing a shutdown.
$$ PIT = t(P \geq P_{limit}) – t_{sag\_start} $$
For a solar inverter, the relevant PIT curve would map the time for its output current to reach the overcurrent protection setpoint under various sag vectors \(S\). This provides a more granular and physically meaningful tolerance description than a binary VTC. The immunity of the solar inverter is thus encapsulated in the PIT surface over the multidimensional sag feature space.
Experimental Methodology and Test Vectors
To empirically derive both VTCs and PIT curves for a solar inverter, a controlled laboratory test setup was essential. The core of the setup was a programmable AC power source capable of generating precise voltage sag waveforms with adjustable features. A commercial string solar inverter was connected to this emulated grid. The DC input was supplied by a PV array simulator set to a constant power point, allowing for repeatable tests independent of sunlight variability. The inverter fed a local resistive load. High-speed power quality analyzers and data loggers measured the grid-side voltage and current, as well as critical inverter parameters.
The testing philosophy was to systematically explore the defined sag feature vector space. A comprehensive test matrix was designed, as summarized in Table 1.
| Primary Feature | Test Range | Step/Increment | Purpose |
|---|---|---|---|
| Sag Magnitude (\(V_{sag}\)) | 0 – 0.9 pu (of nominal) | 0.02 pu | To find the magnitude threshold for various durations. |
| Sag Duration (\(T_{sag}\)) | 0 – 90 ms | 5 ms | To determine the critical clearing time for various magnitudes. |
| Point-on-Wave (\(\theta_i\)) | 0°, 15°, 30°, 45°, 60°, 75°, 90° | 15° | To assess sensitivity to the instantaneous voltage at sag initiation. |
| Output Power (\(P_{out}\)) | ~20% rated, ~80% rated | N/A | To evaluate the impact of inverter loading/operating point. |
Each test cycle began with the solar inverter operating stably at nominal grid voltage. A specific sag event \(S\), defined by the chosen vector from the matrix, was then injected. The inverter’s response was categorized: “Ride-Through” (stable operation, current within limits), or “Trip” (protection activated, inverter disconnects). For PIT analysis, the waveform of the inverter’s output current was recorded with high resolution to precisely determine the time from sag start to the current exceeding its protection threshold. Hundreds of such tests were conducted to populate the feature space adequately.
Results and Analysis: VTCs, POW Sensitivity, and Operational Dependence
The aggregate results from the binary (trip/survive) tests were first used to construct traditional Voltage Tolerance Curves. Crucially, a family of VTCs was generated, one for each tested Point-on-Wave (\(\theta_i\)). This immediately revealed a significant finding: the voltage tolerance boundary of the solar inverter is not unique but is a function of \(\theta_i\). Figure 1 conceptually illustrates the spread of these boundaries in the \(V_{sag}\) vs. \(T_{sag}\) plane for different \(\theta_i\) values.
The data showed distinct regions of POW sensitivity. For deep sags (\(V_{sag} < 0.4\) pu), the solar inverter’s tolerance was highly dependent on \(\theta_i\). When the sag initiated at a lower phase angle (e.g., \(\theta_i = 0°\)), the inverter could withstand the sag for up to 20 ms. However, when the same magnitude sag initiated at a higher angle (e.g., \(\theta_i = 90°\)), the critical duration reduced to approximately 10 ms. This can be attributed to the more severe instantaneous voltage step and the consequent larger transient current demand and PLL disturbance when a sag starts near the voltage peak compared to a zero-crossing.
In the moderate sag region (0.4 pu \(< V_{sag} < 0.6\) pu, \(T_{sag}\) between 20-25 ms), the influence of POW was also pronounced. The boundary for \(\theta_i = 0°\) was located at a lower voltage magnitude than that for \(\theta_i = 90°\), meaning the solar inverter was more tolerant to sags starting at zero-crossings in this specific region. For shallow sags (\(V_{sag} > 0.72\) pu), the solar inverter demonstrated full ride-through capability for durations up to 90 ms, regardless of the POW, aligning with typical LVRT requirements.
Furthermore, the operating condition of the solar inverter significantly impacted its tolerance. Tests were repeated at two distinct output power levels: a light-load condition (~20% of rated inverter power) and a heavy-load condition (~80% of rated power). Table 2 contrasts the critical sag duration for a 0.5 pu sag at different POWs under these two operational states for the solar inverter.
| Point-on-Wave (\(\theta_i\)) | Critical Duration @ ~20% Load (ms) | Critical Duration @ ~80% Load (ms) | Observation |
|---|---|---|---|
| 15° | > 90 | ~25 | Markedly reduced tolerance under heavy load. |
| 75° | ~35 | ~15 | Tolerance reduced at both loads, but heavy load condition is far more restrictive. |
The results are clear: the solar inverter exhibits a stronger voltage sag tolerance when operating at lighter loads. Under heavy load, the inverter is operating closer to its current and thermal limits. The transient overcurrent caused by a voltage sag is therefore more likely to reach the protection threshold quickly, leading to a shorter effective immunity time and a shrunken VTC boundary. This underscores that the immunity of a solar inverter is not an intrinsic, fixed property but is contingent upon its instantaneous operating point.
Process Immunity Time (PIT) Analysis for the Solar Inverter
The binary VTC analysis, while informative, masks the dynamic process leading to a trip. To gain deeper insight, the PIT concept was applied. The chosen process parameter was the RMS value of the solar inverter’s output current (\(I_{rms}\)), with the limit \(I_{limit}\) being its overcurrent protection setting. For a set of voltage sags with the same nominal magnitude (0.65 pu) and duration (80 ms) but different feature vectors, the current response was recorded. The PIT was measured as the time from sag initiation until \(I_{rms} \geq I_{limit}\).
Four specific sag events were analyzed:
1. \(S_1 = [0.65pu, 80ms, 0°]\) (Baseline, magnitude & duration only)
2. \(S_2 = [0.65pu, 80ms, 0°, \Delta\phi=60°]\) (With phase-angle jump)
3. \(S_3 = [0.65pu, 80ms, 90°]\) (With high POW)
4. \(S_4 = [0.65pu, 80ms, 90°, \Delta\phi=60°]\) (With both high POW and phase jump)
The results, summarized in Table 3, demonstrate the powerful discrimination of the PIT metric.
| Sag Event | Feature Vector (Key Elements) | Measured PIT (ms) | Interpretation |
|---|---|---|---|
| \(S_1\) | Baseline (0° POW) | 120.2 | Reference immunity time. |
| \(S_2\) | Baseline + 60° Phase Jump | 98.5 | Phase jump introduces additional transient, reducing PIT by ~18%. |
| \(S_3\) | 90° POW | 85.7 | High POW is more stressful than phase jump alone, reducing PIT by ~29%. |
| \(S_4\) | 90° POW + 60° Phase Jump | 63.4 | Combined features have a severe, compounding effect, reducing PIT by ~47%. |
The PIT analysis quantitatively confirms that different sag features stress the solar inverter in different ways. A sag starting at 90° POW is more damaging than one with a 60° phase jump starting at 0° POW, as reflected in the shorter PIT. The combination of adverse features leads to the shortest PIT, dramatically increasing the risk of inverter tripping. This explains why two sags with identical magnitude and duration on a standard VTC can have completely different outcomes for the solar inverter. The PIT curve, therefore, provides a continuous and multidimensional surface that more faithfully represents the solar inverter’s tolerance landscape. The relationship can be conceptually modeled as:
$$ PIT = f(S, \Omega) = f(V_{sag}, T_{sag}, \theta_i, \theta_f, \Delta\phi, …; P_{dc}, V_{dc}, …) $$
where \(\Omega\) represents the operational state vector of the solar inverter (DC power, DC voltage, temperature, etc.).
Discussion and Implications
The findings of this research carry significant implications for the design, testing, and integration of solar inverters. The demonstrated sensitivity to Point-on-Wave challenges the adequacy of single-profile LVRT tests. Grid codes and compliance testing for solar inverters could be enhanced by mandating tests across a range of POWs to ensure robustness against the statistical distribution of real-world sag initiations. Inverter manufacturers can use this vector-based testing approach to stress-test their control algorithms and protection schemes more comprehensively, leading to more resilient designs.
For system planners and operators, understanding that a solar inverter’s tolerance is contingent on its operating power is critical. During periods of high solar generation (heavy inverter loading), the grid is paradoxically more vulnerable to the loss of this generation from voltage sags. This insight should inform stability studies and the design of advanced grid-support functions. The PIT framework also offers a superior metric for comparing different solar inverter models or for setting custom protection parameters in specific, sensitive applications.
While this study focused on magnitude, duration, and initial POW, the feature vector methodology is extensible. Future work should incorporate phase-angle jumps (\(\Delta\phi\)), which preliminary PIT data shows to be influential. The effect of unbalanced sags on three-phase solar inverters is another crucial dimension. Furthermore, the PIT concept can be applied to other internal parameters of the solar inverter, such as DC-link voltage, whose rise during sags due to power imbalance can also trigger protection. Developing a multi-parameter PIT model would yield an even more complete immunity portrait.
Conclusion
In conclusion, accurately assessing the voltage sag tolerance of a solar inverter requires moving beyond the conventional two-dimensional magnitude-duration paradigm. This research establishes that the immunity boundary of a solar inverter is not a fixed curve but a multi-faceted surface shaped by the complete feature vector of the sag event—most notably the Point-on-Wave—and the instantaneous operating condition of the inverter itself. The proposed methodology, combining systematic testing with a defined sag feature vector and analysis via Process Immunity Time curves, provides a more rigorous, realistic, and informative characterization framework. The solar inverter’s response is a dynamic process culminating in a protection trip; the PIT metric captures this dynamics where a binary VTC cannot. Adopting this comprehensive approach in design, testing, and system analysis is essential for developing solar inverters—and by extension, power systems with high renewable penetration—that are truly resilient to the complex reality of grid voltage disturbances.