In modern power systems, the large-scale integration of renewable energy sources has necessitated the deployment of advanced battery energy storage system technology. Lithium-ion battery energy storage system are favored for their rapid response, flexible configuration, and geographical independence. However, the operational reliability and safety of these systems are paramount. Frequent incidents of fires and thermal runaway in storage power stations globally have highlighted insulation failure as a critical trigger. A fundamental aspect of this insulation challenge lies in the electrical interaction between the battery system and ground, primarily driven by common-mode (CM) phenomena. This paper delves into the characteristics, influencing factors, and implications of common-mode voltage and current in a battery energy storage system.
The core of a grid-connected battery energy storage system comprises the battery clusters and the Power Conversion System (PCS). The PCS, typically utilizing Pulse Width Modulation (PWM) techniques like Sinusoidal PWM (SPWM) or Space Vector PWM (SVPWM) in a three-level Neutral-Point-Clamped (NPC) or Active NPC (ANPC) topology, facilitates bidirectional power flow. The high-frequency switching actions of the PCS’s semiconductor devices are the primary source of common-mode voltage. Meanwhile, the battery cluster, which houses numerous battery modules, battery management units, and cooling apparatus within a metallic frame or enclosure, inherently possesses distributed parasitic capacitances between its internal DC busbars (positive and negative poles) and the grounded frame.
This grounded frame design and the ubiquitous parasitic capacitance create a conduit for the PCS-generated common-mode voltage to invade the battery energy storage system. This invasion manifests in two detrimental effects: 1) Severe fluctuation of the pole-to-ground voltage (the voltage between the positive/negative DC bus and earth), subjecting the insulation to high-frequency, high-amplitude stress; and 2) The generation of significant common-mode ground currents due to the high-frequency charging and discharging of the parasitic capacitors. These effects collectively degrade insulation, accelerate aging, induce electromagnetic interference in battery management circuits, and ultimately threaten the safety and longevity of the battery energy storage system.
1. Mechanism of Common-Mode Voltage Generation and Intrusion
The common-mode voltage ($u_{cm}$) in a three-phase PCS is fundamentally defined as the arithmetic average of the three-phase output voltages relative to the DC-link midpoint (point ‘o’):
$$u_{cm} = \frac{u_{Ao} + u_{Bo} + u_{Co}}{3}$$
Under PWM modulation, each phase leg outputs a pulsed voltage ($u_{xo}$, where x = A, B, C) swinging between the positive DC level ($p$), the negative DC level ($n$), and the midpoint ($o$). The superposition of these three pulsed waveforms results in a staircase-shaped common-mode voltage waveform. Its amplitude can theoretically reach up to $\pm V_{dc}/2$, directly scaling with the DC-link voltage $V_{dc}$ of the battery energy storage system.
The intrusion path for this common-mode voltage into the battery cluster is critical. The $u_{cm}$ propagates from the PCS bridge legs to the AC grid neutral. Since both the AC grid and the battery system frame are grounded (though at potentially different physical points), a coupling path is established through the grounding network. This voltage then appears across the parasitic capacitors ($C_{v1}$ and $C_{v2}$) formed between the battery system’s positive/negative poles and the grounded frame. Consequently, the common-mode voltage superimposes itself onto the DC pole voltages, causing the pole-to-ground voltages ($u_{cv1}$, $u_{cv2}$) to oscillate violently. Simultaneously, it drives a common-mode current ($i_{cm} = i_{cm1} + i_{cm2}$) through these parasitic capacitors to ground.
2. Second-Order Common-Mode Equivalent Circuit Model
To quantitatively analyze this phenomenon, a simplified yet accurate common-mode equivalent circuit for the entire battery energy storage system is essential. Starting from the three-phase circuit equations of the PCS with an LCL filter and incorporating the grounding impedance $Z_g$, the common-mode current $i_{cm}$, and the parasitic capacitors $C_{v1}$ and $C_{v2}$, one can derive the common-mode loop equations. By assuming a symmetric three-phase grid and that the parasitic capacitances are the dominant coupling path, the model can be significantly simplified.
The positive and negative parasitic capacitances ($C_{v1}$, $C_{v2}$) appear in parallel in the common-mode path. Defining the total parasitic capacitance $C = C_{v1} + C_{v2}$, and considering the equivalent inductance $L = L_f / 3$ (where $L_f$ is the inverter-side filter inductance) and resistance $R = R_g + R_0/3$ (combining grounding and line resistance), the system reduces to a classic series RLC circuit driven by the PCS common-mode voltage source $u_{cm}$. The impedance of the parallel capacitor branch ($1/j\omega C$) is much smaller than the series inductor impedance ($j\omega L$) at typical switching frequencies, confirming the validity of this series model.
The simplified second-order common-mode equivalent circuit is shown below:
$$ \text{Circuit: } u_{cm} \rightarrow (R + L + C) \rightarrow \text{Ground} $$
Where the voltage across the capacitor $C$ represents the common-mode voltage $u_{cmv}$ impressed on the battery cluster poles relative to ground.
The transfer functions from the source $u_{cm}$ to the cluster common-mode voltage $u_{cmv}$ and the common-mode current $i_{cm}$ are given by:
$$H_1(s) = \frac{U_{cmv}(s)}{U_{cm}(s)} = \frac{1}{LCs^2 + RCs + 1}$$
$$H_2(s) = \frac{I_{cm}(s)}{U_{cm}(s)} = \frac{Cs}{LCs^2 + RCs + 1}$$
Where $s$ is the complex frequency variable. The natural frequency $\omega_n$ and damping ratio $\zeta$ of this system are:
$$\omega_n = \frac{1}{\sqrt{LC}}, \quad \zeta = \frac{R}{2}\sqrt{\frac{C}{L}}$$
For practical battery energy storage system parameters, the system is typically underdamped ($0 < \zeta < 1$), leading to oscillatory transient responses to the step-like edges of the PWM common-mode voltage.
3. Quantification of Common-Mode Voltage and Current Characteristics
3.1 Transient Peak Analysis
To assess the worst-case stress, the transient peak values of $u_{cmv}$ and $i_{cm}$ in response to a step change in $u_{cm}$ are derived. Solving the underdamped second-order system response yields the approximate peak values:
$$u_{cmv\_max} \approx 1.025 \cdot u_{cm\_max}$$
$$i_{cm\_max} \approx 0.4 \cdot (C_{v1} + C_{v2}) \cdot u_{cm\_max} \cdot \omega_n$$
Where $u_{cm\_max}$ is the peak amplitude of the PCS-generated common-mode voltage. This analysis reveals that the transient common-mode voltage invading the battery energy storage system can slightly exceed the source voltage, while the common-mode current peak is directly proportional to the total parasitic capacitance and the system’s natural frequency.
3.2 Steady-State Frequency-Domain Analysis
In steady state, the RMS or spectral characteristics are more relevant. The magnitude of the cluster’s common-mode voltage and current at a given frequency $\omega$ (where $\omega = 2\pi f$) are:
$$|U_{cmv}(\omega)| = \frac{|U_{cm}(\omega)|}{\sqrt{(1 – LC\omega^2)^2 + (RC\omega)^2}}$$
$$|I_{cm}(\omega)| = \frac{C \omega \cdot |U_{cm}(\omega)|}{\sqrt{(1 – LC\omega^2)^2 + (RC\omega)^2}}$$
The pole-to-ground voltages for the positive and negative poles are:
$$U_{cv1} = \frac{V_{dc}}{2} + U_{cmv}, \quad U_{cv2} = -\frac{V_{dc}}{2} + U_{cmv}$$
The spectral composition of $u_{cm}$ is crucial. A Fourier analysis of the typical three-level PWM waveform shows that $u_{cm}$ contains a DC component and dominant harmonic clusters centered at odd multiples of the switching frequency ($f_0$):
$$f_{cm\_centers} = (2k-1)f_0, \quad k=1,2,3,…$$
Thus, the stress on the battery energy storage system insulation is primarily at high frequencies (e.g., $f_0$, $3f_0$, $5f_0$), where insulation materials are more susceptible to degradation.
4. Analysis of Key Influencing Factors
Based on the derived models, the impact of two major variable factors—parasitic capacitance and PCS switching frequency—on the common-mode voltage and current in the battery energy storage system is analyzed.
4.1 Influence of Parasitic Capacitance ($C_{v1}$, $C_{v2}$)
The total parasitic capacitance $C$ has opposing effects on the steady-state amplitude of $u_{cmv}$ and $i_{cm}$:
- Common-Mode Voltage ($u_{cmv}$): An increase in $C$ leads to a decrease in the impedance of the capacitive branch ($1/\omega C$). This provides a lower-impedance path to ground for the common-mode voltage, effectively shunting it and reducing the voltage $u_{cmv}$ that appears across the battery poles. The relationship is inverse.
- Common-Mode Current ($i_{cm}$): Although a larger $C$ reduces $u_{cmv}$, the current is given by $I_{cm} = U_{cmv} \cdot (\omega C)$. The increase in the capacitive susceptance ($\omega C$) dominates, leading to an overall increase in $i_{cm}$. The relationship is direct.
This dual effect creates a design trade-off for the battery energy storage system.
4.2 Influence of Switching Frequency ($f_0$)
The switching frequency directly determines the spectral location of the common-mode stress:
- Higher $f_0$ shifts the dominant harmonic energy to higher frequencies.
- At these higher frequencies, the capacitive impedance ($1/\omega C$) decreases, which can marginally increase $i_{cm}$ for a given $u_{cm}$ amplitude.
- More importantly, high-frequency voltage stress (high $dv/dt$) is particularly aggressive for insulation, increasing dielectric losses and accelerating aging. The high-frequency $i_{cm}$ can also cause more severe electromagnetic interference (EMI) with sensitive battery management system (BMS) electronics within the battery energy storage system.
The following table summarizes the influence of these parameters based on the analytical model:
| Parameter | Effect on Common-Mode Voltage ($u_{cmv}$) | Effect on Common-Mode Current ($i_{cm}$) | Physical Reason |
|---|---|---|---|
| Parasitic Capacitance $C \uparrow$ | Amplitude $\downarrow$ | Amplitude $\uparrow$ | Lower impedance path to ground shunts voltage but increases capacitive current. |
| Switching Frequency $f_0 \uparrow$ | Slight change (depends on resonance) | Amplitude $\uparrow$ (typically) | Higher $\omega$ increases capacitive susceptance ($\omega C$) and shifts stress to more damaging high frequencies. |
| DC-Link Voltage $V_{dc} \uparrow$ | Amplitude $\uparrow$ (proportional) | Amplitude $\uparrow$ (proportional) | Source $u_{cm\_max}$ is proportional to $V_{dc}$. |
| Grounding Resistance $R_g \uparrow$ | Amplitude $\uparrow$ | Amplitude $\downarrow$ | Higher impedance in the CM loop limits current but allows higher voltage buildup. |
5. Simulation and Experimental Validation
To validate the theoretical analysis, a simulation model of a 100-kW battery energy storage system with a three-level ANPC PCS was built. Experiments were conducted on a laboratory-scale prototype. Key parameters are listed below:
| Parameter | Value |
|---|---|
| Rated Power | 100 kW |
| Grid Voltage (Line-to-Line RMS) | 690 V |
| DC-Link Voltage ($V_{dc}$) | 1100 V |
| Switching Frequency ($f_0$) | 2.8 – 3.0 kHz |
| Filter Inductance ($L_f$) | 310 µH |
| Parasitic Capacitance Range ($C_{v1}$, $C_{v2}$) | 3 nF to 310 nF |
5.1 Waveform and Spectral Characteristics
Measurements confirmed the severe pole-to-ground voltage fluctuations. With $V_{dc}=1100V$, the positive pole-to-ground voltage peaked at approximately +900 V, and the negative pole reached -880 V, with a $dv/dt$ exceeding 1.7 MV/s. The common-mode current reached amplitudes of up to 16 A. Spectral analysis of the pole voltage clearly showed dominant harmonics at $f_0$, $3f_0$, and $5f_0$, aligning perfectly with the theoretical prediction.
5.2 Validation of Influencing Factors
A series of tests were conducted by varying the externally connected parasitic capacitors. The results quantitatively confirmed the analytical predictions.
| Total Parasitic Capacitance C (nF) | Positive Pole-Ground Voltage Peak (V) | Positive Pole CM Current Peak (A) | Trend Observation |
|---|---|---|---|
| 6 | ~940 | ~4.7 | Base Case |
| 173 | ~820 | ~10.5 | $u_{cmv}$ ↓, $i_{cm}$ ↑ |
| 340 | ~750 | ~12.5 | $u_{cmv}$ ↓, $i_{cm}$ ↑ |
| 620 | ~680 | ~14.6 | $u_{cmv}$ ↓, $i_{cm}$ ↑ |
The inverse relationship between $u_{cmv}$ and $C$, and the direct relationship between $i_{cm}$ and $C$, are evident. Tests with different switching frequencies (2.8 kHz, 2.9 kHz, 3.0 kHz) confirmed the shift in the harmonic spectrum, with the dominant peak moving accordingly while maintaining the odd-multiple relationship.
6. Implications and Design Recommendations for Battery Energy Storage Systems
The presence of significant common-mode voltage and current poses a substantial challenge to the insulation integrity and electromagnetic compatibility of a battery energy storage system. Based on the comprehensive analysis, the following conclusions and design recommendations are drawn:
- Common-Mode Voltage is a Primary Stressor: The high-frequency, high-$dv/dt$ common-mode voltage superimposed on the DC pole voltage is a major factor accelerating insulation aging within the battery cluster. The pole-to-ground voltage can exceed the DC voltage level during transients.
- Parasitic Capacitance is a Critical Parameter: It directly governs the amplitude of both the common-mode voltage stress and the ground current. There exists a trade-off; reducing $C$ lowers $i_{cm}$ but increases $u_{cmv}$, and vice-versa.
- Switching Frequency Defines the Stress Spectrum: The stress is concentrated around odd harmonics of $f_0$. Higher $f_0$ leads to stress at more electrically “aggressive” frequencies, even if the voltage amplitude is somewhat attenuated by the filter.
Recommendations for System Design Optimization:
- Enhanced Insulation Design: The insulation system of the battery energy storage system, particularly for the DC busbars, battery module housings, and BMS wiring, must be rated not only for the DC voltage but also for high-frequency, high-amplitude common-mode voltage surges. Materials with low dielectric loss at high frequencies are preferable.
- Active/Passive Mitigation at the PCS: Employing modified PWM strategies (e.g., Near-State PWM, active zero-state PWM) that inherently generate lower common-mode voltage can reduce the source excitation. Incorporating common-mode chokes in the DC or AC lines can increase the impedance of the common-mode path.
- Control of Parasitic Capacitance: The physical layout of the battery cluster should be designed to minimize uncontrolled parasitic capacitance to the grounded frame. This could involve careful spacing, the use of shielding, or dielectric materials with lower permittivity between live parts and ground.
- Isolation Strategies: For high-reliability applications, introducing galvanic isolation (e.g., a transformer) between the PCS and the battery cluster can fundamentally break the common-mode conduction path, though at the cost of efficiency, weight, and size.
- Robust Grounding and Filtering: Implementing a single-point, low-impedance grounding scheme for the entire battery energy storage system can help manage common-mode potential differences. Additionally, installing high-frequency rated capacitors (Y-capacitors) in a coordinated manner between poles and ground can provide a controlled, low-impedance path to shunt common-mode noise away from sensitive components, but must be done within safety limits.
In summary, the common-mode voltage and current issue is an intrinsic and significant challenge in PWM-driven, non-isolated battery energy storage system architectures. A thorough understanding of its characteristics and influencing factors, as provided by the analytical model and validated through experiment, is essential for the optimal design, reliable operation, and enhanced safety of modern grid-scale battery energy storage system.