In recent years, the widespread integration of distributed energy resources into the grid has led to the extensive application of solar inverters. To enhance system efficiency, various methods such as wide-bandgap semiconductors, advanced topologies, soft-switching techniques, and discontinuous pulse width modulation (DPWM) have been employed. DPWM, in particular, reduces switching losses by clamping each bridge arm to either the positive or negative DC bus for one-third of the fundamental period, thereby improving efficiency compared to continuous modulation schemes like space vector PWM (SVPWM). However, the discontinuous nature of DPWM introduces high-frequency common-mode voltage components, which can exacerbate common-mode currents (CMC) and degrade grid current quality, especially in high-power solar inverter systems with large parasitic capacitances. This paper addresses this issue by proposing a semi-DPWM (SDPWM) strategy that injects a third-order sinusoidal component during the clamping transitions of traditional DPWM, effectively suppressing high-order common-mode harmonics while maintaining high efficiency.
The common-mode current problem in solar inverters arises due to the parasitic capacitance between the photovoltaic (PV) array and ground. In low-power systems, this capacitance is negligible, but in larger installations, it increases significantly, leading to resonant frequencies within the common-mode loop that amplify CMC. Traditional DPWM methods, such as DPWM1, introduce abrupt changes in the modulation waves during clamping intervals, generating substantial common-mode voltage harmonics. These harmonics excite the resonant peak of the common-mode circuit, resulting in elevated CMC and increased total harmonic distortion (THDi) of the grid current. To mitigate this, we analyze the common-mode equivalent circuit and derive the transfer function to identify the resonant frequency. Based on this analysis, we develop the SDPWM strategy, which smooths the clamping transitions by injecting a continuous third-order sinusoidal signal, reducing the high-frequency common-mode voltage content without significantly compromising efficiency.
The common-mode behavior of a solar inverter system can be modeled using the equivalent circuit shown in Figure 1. For a three-level T-type inverter, the common-mode voltage \(v_{CM}\) is defined as the average of the phase-to-neutral voltages: \(v_{CM} = (v_{AO} + v_{BO} + v_{CO})/3\). The common-mode current \(i_{CM}\) is the sum of the grid currents: \(i_{CM} = i_{ga} + i_{gb} + i_{gc}\). Assuming symmetric three-phase parameters, the system equations can be derived as follows:
$$v_{AO} = L \frac{di_a}{dt} + r i_a + L_g \frac{di_{ga}}{dt} + r_g i_{ga} + L_{cm} \frac{di_{CM}}{dt} + e_a + v_{GO}$$
$$v_{BO} = L \frac{di_b}{dt} + r i_b + L_g \frac{di_{gb}}{dt} + r_g i_{gb} + L_{cm} \frac{di_{CM}}{dt} + e_b + v_{GO}$$
$$v_{CO} = L \frac{di_c}{dt} + r i_c + L_g \frac{di_{gc}}{dt} + r_g i_{gc} + L_{cm} \frac{di_{CM}}{dt} + e_c + v_{GO}$$
Summing these equations and considering that the grid voltages sum to zero (\(\sum e = 0\)), we obtain the common-mode voltage equation:
$$v_{CM} = \frac{L + L_g}{3} \frac{d(i_0 + i_{CM})}{dt} + \frac{r + r_g}{3} (i_0 + i_{CM}) + L_{cm} \frac{di_{CM}}{dt} + v_{GO}$$
where \(i_0 = i_{Ca} + i_{Cb} + i_{Cc}\) represents the sum of the inverter-side capacitor currents. The voltage \(v_{GO}\) between the grid neutral and the DC-link midpoint can be expressed in terms of the PV stray capacitance \(C_s\):
$$v_{GO} = \frac{1}{C_s} \int i_{CM} \, dt + \frac{\Delta v_{dc}}{2}$$
Substituting and simplifying, the transfer function from common-mode voltage to common-mode current is derived as:
$$G_{CM}(s) = \frac{i_{CM}(s)}{v_{CM}(s)} = \frac{C_s s}{(L_1 + L_2) C_s s^2 + r_2 C_s s + 1}$$
where \(L_1 = L/3\), \(L_2 = L_g/3 + L_{cm}\), and \(r_2 = (r + r_g)/3\). The resonant frequency \(f_r\) of the common-mode loop is given by:
$$f_r = \frac{1}{2\pi \sqrt{(L_1 + L_2) C_s}}$$
For high-power solar inverters, \(C_s\) increases, lowering \(f_r\) below the switching frequency \(f_s\). This results in a significant gain at \(f_r\), amplifying common-mode currents. The Bode plot of \(G_{CM}(s)\) for a 50 kW system shows a resonant peak near 2.55 kHz, where the gain reaches approximately 30 dB, explaining the increased CMC under DPWM.
To suppress these harmonics, we propose the SDPWM strategy. Traditional DPWM methods use a zero-sequence compensation voltage \(v_{CM1}\) defined as:
$$v_{CM1} = \frac{V_{DC}}{2} \left[ \alpha (1 – 2V_{\min}) – (1 – \alpha) V_{\max} \right]$$
where \(V_{\max}\) and \(V_{\min}\) are the maximum and minimum phase voltages, and \(\alpha = [1 + \sin(3\omega t)]/2\). In SDPWM, we introduce a smooth transition during clamping by injecting a third-order sinusoidal component. Let \(\theta\) be the angle over which the clamping transition is smoothed. The modified compensation voltage \(v_{CM}\) is given by:
$$v_{CM} = \begin{cases}
-V_m \sin(3\omega t) & \text{for } 0 \leq \omega t \leq \theta \\
-\frac{V_{DC}}{2} + V_P \left[ \frac{1}{m} \sin\left(\frac{\pi}{3} + \theta\right) – \frac{1}{3} \right] & \text{for } \theta \leq \omega t \leq \frac{\pi}{3} – \theta \\
-V_m \sin(3\omega t) & \text{for } \frac{\pi}{3} – \theta \leq \omega t \leq \frac{\pi}{3}
\end{cases}$$
where \(V_m = \frac{V_P}{m} \left[ \sin\left(\frac{\pi}{3} + \theta\right) – \frac{1}{3} \right]\), \(V_P\) is the peak inverter voltage, and \(m\) is the modulation index. The harmonic content of the common-mode voltage under SDPWM is analyzed by computing the Fourier coefficients. The nth harmonic amplitude \(V_{CM}^{(n)}\) is derived as:
$$V_{CM}^{(n)} = \frac{\Delta V}{\pi} M_n(\theta)$$
where \(M_n(\theta) = \frac{\sin(n\theta)}{n} \left[ 1 – \cos(3\theta) \right] + \frac{\cos(n\theta)}{n} \sin(3\theta)\). As \(\theta \to 0\), \(M_n(\theta) \to 1\), indicating that DPWM is a special case of SDPWM. The relationship between \(\theta\), \(m\), and THDi is illustrated in a 3D plot, showing that THDi increases with both \(m\) and \(\theta\). For a solar inverter requiring THDi < 5%, an optimal \(\theta\) can be selected based on the modulation index.
Experimental validation was conducted on a 50 kVA solar inverter system with parameters: \(L = 70 \mu H\), \(C = 32 \mu F\), \(C_{dc} = 2820 \mu F\), \(C_s = 20 \mu F\) (simulating a 100 kW PV array), \(L_g = 25 \mu H\), \(L_{cm} = 230 \mu H\). The switching frequency was 16.2 kHz, grid voltage 230 Vrms, and DC-link voltage 810 V. Comparisons were made among SVPWM, DPWM, and SDPWM. The THDi under SDPWM was measured at 3.71%, slightly higher than the theoretical 3.3% but significantly better than DPWM, while SVPWM achieved 2.4%. The common-mode current under SDPWM was 1.35 A, close to SVPWM’s 1.06 A and much lower than the 1.97 A observed in a prior DPWM method using triangular injection. Efficiency tests showed that SDPWM achieved a peak efficiency of 97.2%, outperforming SVPWM’s 97.1% across the load range, as summarized in Table 1.
| Modulation Strategy | THDi (%) | Common-Mode Current (A) | Peak Efficiency (%) |
|---|---|---|---|
| SVPWM | 2.4 | 1.06 | 97.1 |
| DPWM | >5 | 1.97 | 97.3 |
| SDPWM (proposed) | 3.71 | 1.35 | 97.2 |
The harmonic spectrum of the output current under SDPWM revealed suppressed components near the resonant frequency of 2.5 kHz, with amplitudes around 0.1 A, confirming effective mitigation of common-mode excitations. The waveform transitions in SDPWM were smoother, reducing the high-frequency content that plagues traditional DPWM. This makes SDPWM particularly suitable for large-scale solar inverters where parasitic capacitances are substantial.
In conclusion, the proposed SDPWM strategy effectively reduces common-mode currents in solar inverters by injecting a third-order sinusoidal component during clamping transitions. This approach maintains the efficiency benefits of DPWM while minimizing grid current distortion. Theoretical analysis and experimental results demonstrate that SDPWM achieves a balance between power quality and efficiency, making it a viable solution for modern photovoltaic systems. Future work could explore adaptive tuning of the transition angle \(\theta\) based on real-time operating conditions to further optimize performance.