The integration of photovoltaic (PV) systems into the power grid relies heavily on efficient and reliable solar inverters. Among various topologies, the three-level Neutral-Point Clamped (NPC) inverter has gained significant traction for medium to high-power applications due to its advantages of lower switching stress on power devices and reduced harmonic distortion in the output voltage compared to its two-level counterpart. However, in transformerless PV systems, a critical challenge arises from the generation of leakage currents. These currents flow through the parasitic capacitance between the PV panels and the ground, induced by the common-mode (CM) voltage produced by the inverter’s switching actions. Leakage current can lead to increased system losses, electromagnetic interference (EMI), distortion of grid current, and poses safety risks. Therefore, developing effective modulation strategies to suppress leakage current is paramount for the performance and safety of three-level NPC solar inverters.
Traditional approaches to mitigate this issue often involve hardware modifications, such as adding isolation transformers or common-mode filters. While effective, these solutions increase the system’s cost, weight, and volume, reducing the power density—a key metric for modern solar inverters. Consequently, software-based methods, which modify the Pulse Width Modulation (PWM) strategy to minimize the CM voltage at its source, present a more economical and flexible alternative.
Discontinuous PWM (DPWM) strategies are particularly attractive for solar inverters as they can significantly reduce switching losses. By clamping one of the inverter phases to either the positive or negative DC bus for a portion of the fundamental cycle, one-third of the switching devices remain inactive during each switching period. This directly translates to higher efficiency. However, conventional DPWM methods implemented via Space Vector PWM (SVPWM) necessitate complex sector identification and vector duty cycle calculations in every switching cycle. More importantly, the choice of clamping vectors significantly impacts the magnitude of the injected low-frequency CM voltage, which is a primary driver of leakage current in systems with substantial parasitic capacitance.
This work analyzes the inherent low-frequency CM voltage components of various DPWM types and identifies DPWM1 as the strategy with the smallest inherent CM voltage magnitude. Building upon this, I propose an Improved DPWM (I-DPWM) strategy specifically designed for three-level NPC solar inverters. The core innovation lies in analytically modifying the zero-sequence voltage injection at the points of discontinuity in the DPWM1’s CM voltage waveform. This modification further reduces the peak amplitude of the low-frequency CM voltage component, leading to enhanced leakage current suppression. Furthermore, the strategy is implemented using a carrier-based modulation scheme, which eliminates the computational burden associated with traditional SVPWM-based DPWM, making it more practical for digital controller implementation. The effectiveness of the proposed I-DPWM method is validated through both detailed simulation of a 20-kW system and experimental results from a scaled-down 125-W prototype.
Mechanism of Leakage Current Generation in NPC Solar Inverters
The generation of leakage current is intrinsically linked to the common-mode voltage, \(v_{com}\), of the solar inverter. For a three-phase three-level NPC inverter, the CM voltage is defined as the average of the three phase output voltages with respect to the negative DC bus midpoint (or a virtual ground point). Using the switching states \(S_x\) (where \(S_x = 1, 0, -1\) for P, O, N states respectively, and \(x \in \{a, b, c\}\)), it can be expressed as:
$$v_{com} = \frac{V_{dc}}{6} (S_a + S_b + S_c)$$
where \(V_{dc}\) is the total DC-link voltage.
The leakage current, \(i_{leak}\), flows through the parasitic capacitance, \(C_{pv}\), of the PV array. An LCL filter is commonly used at the output of the solar inverter. The simplified common-mode equivalent circuit, considering the filter inductances (\(L_f\), \(L_g\)) and the parasitic capacitance, reveals the relationship between the CM voltage and the leakage current. The transfer function can be derived as:
$$i_{leak}(s) = \frac{3 C_{pv} s}{ (L_f + L_g) C_{pv} s^2 + 3} v_{com}(s)$$
This equation shows that the leakage current is directly proportional to the CM voltage, its frequency, and the value of the parasitic capacitance. For multi-kW scale solar inverters, the parasitic capacitance (typically 50-150 nF/kWp for crystalline silicon) and the filter inductance can be substantial, resulting in a low-impedance path for both high-frequency (switching frequency) and low-frequency (e.g., 150 Hz, 3rd harmonic) components of the CM voltage. Therefore, a comprehensive suppression strategy must address both spectral regions.
Analysis of Common-Mode Voltage in Carrier-Based DPWM
Implementing DPWM via space vector analysis involves selecting specific redundant small vectors to achieve the clamping effect. While effective, this method requires real-time vector decomposition and duty cycle calculation. A more computationally efficient approach is to use Carrier-Based PWM (CBPWM), where the DPWM effect is achieved by injecting an appropriate zero-sequence voltage, \(v_{zs}\), into the fundamental three-phase sinusoidal reference voltages. The modified phase reference voltages become:
$$v_{x}^{*’} = v_{x}^{*} + v_{zs}, \quad x \in \{a, b, c\}$$
For a three-level inverter, this zero-sequence injection shapes the reference waveforms so that one phase hits the upper or lower clamp level for 120-degree intervals.
Different DPWM schemes (DPWM1, DPWM2, DPWM3, DPWM0, DPWMMIN, DPWMMAX) correspond to different clamping patterns and, consequently, different injected zero-sequence voltages. By calculating the equivalent modulating waves for these schemes, one can derive their low-frequency CM voltage component, \(v_{com,lf}\). This component is essentially the average of the three modified reference waves over a switching period, mapped to the DC-link voltage:
$$v_{com,lf} \approx \frac{V_{dc}}{2} \cdot \frac{ (v_{a}^{*’} + v_{b}^{*’} + v_{c}^{*’} )}{3} = \frac{V_{dc}}{2} \cdot v_{zs}$$
A comparative analysis reveals that among the standard DPWM schemes applicable without causing DC offset, DPWM1 yields the lowest amplitude of low-frequency CM voltage. For a modulation index \(m = 0.8\), the peak \(v_{com,lf}\) for DPWM1 is approximately \(\pm 0.2 V_{dc}/2\). The waveform, however, contains discontinuities at 60-degree intervals, which contribute to its spectral content and the resultant leakage current.
| DPWM Scheme | Clamping Pattern | Low-Freq CM Voltage Peak (p.u. of \(V_{dc}/2\)) |
|---|---|---|
| DPWM1 | Max phase clamped to P, Min phase clamped to N | ~0.2 |
| DPWM2 | Clamping shifted by 30° | ~0.33 |
| DPWM3 | Clamping shifted by -30° | ~0.33 |
| DPWM0 | Clamping at zero-crossing of phase voltage | ~0.27 |
Proposed I-DPWM Strategy for Enhanced Suppression
The proposed I-DPWM strategy starts from the DPWM1 scheme due to its inherent advantage of low CM voltage. The key observation is that the discontinuities in the DPWM1’s CM voltage waveform are the primary source of its peak magnitude. The proposed improvement focuses on eliminating these discontinuities by locally modifying the clamping behavior around the discontinuity points.
In the standard DPWM1, a phase is clamped to either the positive (P) or negative (N) DC rail for 120 degrees. At the instant of transition from one clamping phase to another, the CM voltage jumps. The I-DPWM strategy introduces a short interval, \(\Delta\theta\), around these transition points where none of the phases is clamped to the extreme rails. Instead, during this interval \(\Delta\theta\), the phase whose voltage is closest to zero is clamped to the neutral point (O). This is achieved by injecting a different zero-sequence component during this interval.
Mathematically, the zero-sequence voltage for I-DPWM, \(v_{zs,I}\), is defined piecewise. For the majority of the cycle, it follows the DPWM1 pattern. During the transition intervals of length \(\Delta\theta\) centered at the discontinuity points (e.g., at \(\omega t = \pi/3\)), it is defined to enforce zero clamping. The boundary of this interval, \(\Delta\theta\), is found by solving for the intersection where the original DPWM1 clamp reference equals the condition for zero clamping. For a modulation index \(m\), this is given by solving:
$$1 – m \sin(\omega t – 2\pi/3) = – m \sin(\omega t)$$
The solution yields the required \(\Delta\theta\). The analytical expression for \(v_{zs,I}\) ensures a continuous and smoother low-frequency CM voltage waveform.
The effect is a significant reduction in the peak amplitude of \(v_{com,lf}\). For \(m=0.8\), the peak value is reduced from \(\pm 0.2 V_{dc}/2\) to approximately \(\pm 0.139 V_{dc}/2\). Spectral analysis confirms a reduction across multiple low-frequency harmonics, most notably the dominant 150 Hz (3rd harmonic) component. It is important to note that this improvement is most effective for modulation indices below a certain threshold (approximately \(m < 0.93\)). Beyond this, the peak CM voltage is determined by a different point in the waveform, and the benefit of smoothing the discontinuity diminishes.
Implementation and Dead-Time Compensation
A significant practical advantage of the proposed method is its implementation via simple carrier-based comparison. The three modified reference voltages \(v_{a}^{*’}\), \(v_{b}^{*’}\), \(v_{c}^{*’}\) are compared against two level-shifted triangular carriers to generate the switching signals for the three-level NPC solar inverter. This bypasses the computational complexity of SVPWM, requiring only the pre-calculation or real-time generation of the appropriate zero-sequence signal \(v_{zs,I}(\omega t, m)\).
Furthermore, to maintain waveform fidelity in a practical solar inverter, dead-time compensation is integrated. Dead-time distorts the output voltage, particularly affecting the duration of the O-state. For the I-DPWM strategy, a modified compensation rule is applied. When the original reference \(u\) (normalized) is not at the clamping extremes (\(\pm1\)), the compensation adjusts the reference as follows:
$$ u_{compensated} = \begin{cases}
\min(u + d_{dead}, 1), & \text{if } i > 0 \\
\max(u – d_{dead}, -1), & \text{if } i < 0
\end{cases}$$
where \(d_{dead}\) is the dead-time as a fraction of the switching period, and \(i\) is the phase current direction. This correction helps maintain the accurate synthesis of the output voltage and the intended CM voltage profile.
Simulation and Experimental Verification
The performance of the proposed I-DPWM strategy was rigorously verified. A simulation model of a 20-kW three-level NPC solar inverter was built in Matlab/Simulink. Key parameters are summarized below.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Rated Power | 20 kW | DC-Link Capacitors | 1600 µF |
| DC-Link Voltage (\(V_{dc}\)) | 620 V | Grid Phase Voltage (RMS) | 220 V |
| Switching Frequency | 20 kHz | Parasitic Capacitance (\(C_{pv}\)) | 2.4 µF |
| Inverter-side Inductor (\(L_f\)) | 4 mH | Grid-side Inductor (\(L_g\)) | 1 mH |
Simulations were conducted for two modulation indices: \(m=0.8\) and \(m=0.93\). For \(m=0.8\), switching from DPWM1 to I-DPWM resulted in a clear reduction in the peak-to-peak amplitude of both the low-frequency CM voltage and the leakage current. The discontinuity-induced transient in the leakage current was also notably suppressed. The spectrum of the CM voltage showed a reduction across low-frequency harmonics. For \(m=0.93\), the improvement was less pronounced, as theoretically predicted, but the I-DPWM still performed comparably or slightly better than DPWM1.
To substantiate the simulation findings, a 125-W laboratory prototype of the three-level NPC solar inverter was constructed and tested. The experimental parameters were scaled accordingly. The results conclusively mirrored the simulation outcomes. At \(m=0.8\), the I-DPWM strategy demonstrated a measurable decrease in leakage current magnitude compared to DPWM1. Spectral measurements from the experiment confirmed the reduction in low-frequency CM voltage components. At \(m=0.93\), the distinction between the two strategies was minimal, validating the theoretical boundary of effectiveness for the proposed modification.
Conclusion
This work addresses the critical issue of leakage current in transformerless three-level NPC solar inverters. By performing a detailed analysis of the low-frequency common-mode voltage inherent in various DPWM schemes, the DPWM1 strategy was identified as a promising base for improvement. The proposed I-DPWM strategy introduces a targeted modification to the zero-sequence injection at the points of waveform discontinuity in DPWM1. This innovation effectively smooths the low-frequency CM voltage, leading to a significant reduction in its peak amplitude and, consequently, the magnitude of the leakage current for modulation indices below approximately 0.93. The method retains the primary advantage of DPWM—reduced switching losses—while being implemented via a straightforward carrier-based algorithm, avoiding the computational overhead of SVPWM. Comprehensive simulation of a 20-kW system and experimental validation on a 125-W prototype confirm the effectiveness and practicality of the I-DPWM strategy, making it a valuable contribution to the development of efficient and safe high-performance solar inverters.