In this paper, I present a novel flyback micro-inverter topology that integrates active clamp and power decoupling functions to address the lifespan and reliability issues caused by electrolytic capacitors in conventional flyback micro-inverters. The proposed converter, as analyzed in the following sections, not only reduces low-frequency ripple in the input current but also enables zero-voltage switching (ZVS) of the main switch and recycles transformer leakage energy. The study systematically explores the operating principles, control strategy, and parameter design, validated by simulation and experimental results from an 80 W prototype. This work contributes to the understanding of how different types of solar inverters can be optimized for distributed photovoltaic systems, particularly focusing on the trade-off between cost, efficiency, and longevity.
I begin by discussing the background. Among various types of solar inverters, the flyback topology is widely adopted in micro-inverters due to its simplicity, galvanic isolation, and low component count. However, conventional flyback inverters suffer from short lifetime caused by large electrolytic capacitors required to buffer the double-line-frequency power pulsation. Moreover, leakage inductance leads to voltage spikes and increased switching losses. Active clamp techniques can recycle leakage energy and achieve soft switching, but they often still rely on electrolytic capacitors for power decoupling. My proposed solution merges an active clamp circuit with a power decoupling function using a single storage capacitor, which serves both as a clamp capacitor and an energy buffer. This approach reduces the input filter capacitance to a small film capacitor (6.8 μF) while maintaining high efficiency and low output distortion.
The structure of the paper is as follows. Section II details the circuit topology and operating modes. Section III presents the control strategy and power decoupling mechanism. Section IV provides key design equations and component selection. Section V discusses simulation and experimental results. Finally, Section VI concludes the paper with a comparison of different types of solar inverters.
Circuit Topology and Operating Principle
The proposed active clamp power decoupling flyback micro-inverter is shown in Fig. 1 (conceptual diagram, not reproduced here). The circuit consists of an input filter (Cin), a flyback converter (main switch Q1, transformer T1 with primary winding w1, secondary windings w3 and w4, diodes D2 and D3), an active clamp circuit (switches Q5, Q6 and capacitor Cs), and a power decoupling circuit (auxiliary switch Q2, diode D1, auxiliary winding w2, and the same capacitor Cs). The secondary side uses two windings that alternate operation during positive and negative half-line cycles. The key innovation is that capacitor Cs simultaneously acts as the clamp capacitor and the decoupling energy storage element. This integration reduces component count and improves reliability. I analyze the circuit under two operating modes: Mode I (Ppv > Pac) and Mode II (Ppv < Pac), where Ppv is the instantaneous PV power and Pac is the instantaneous AC output power. The detailed switching states and current paths are described below.
Mode I (Excess power, Ppv > Pac): In this mode, the surplus energy is stored in Cs via the active clamp path. The switching cycle consists of ten stages. Stage 1 (t0–t1): Q1 turns on with ZVS; the body diode of Q6 conducts. Stage 2 (t1–t2): The primary current iLm increases linearly from zero to peak ipeak1. Stage 3 (t2–t3): Q1 turns off; the energy in Lm and leakage inductance Lk charges Cs through the body diode of Q5; iLm decreases from ipeak1 to ipeak2. Stage 4 (t3–t4): Q3 turns on; the remaining leakage energy continues to charge Cs until iLk reaches zero; secondary current is flows to the AC side via D2 and Q3, decreasing linearly. Stage 5 (t4–t5): D2 turns off naturally; Lm resonates with Cds1 (parasitic capacitance of Q1). Stage 6 (t5–t6): Body diode of Q5 conducts; D2 re-conducts; the voltage across Lk becomes (n1:n3)vac – vCs, causing iLk to increase in reverse. Stage 7 (t6–t7): Q6 turns on with zero current. Stage 8 (t7–t8): Q5 turns off; the reverse current iLk discharges Cds1 via Q6; vds1 falls to zero. Stage 9 (t8–t9): Body diode of Q1 conducts. Stage 10 (t9–t10): Q1 turns on with ZVS; iLk continues to fall to zero and then rises together with iLm.
Mode II (Deficit power, Ppv < Pac): The stages are similar to Mode I, except that during the equivalent of Stage 3, switch Q2 turns on, allowing Cs to discharge through auxiliary winding w2, boosting the primary current from ipeak1 to ipeak2. The remaining stages follow the same pattern, ensuring ZVS of Q1 and energy recovery.
The key waveforms for both modes are summarized in Table 1, which compares the states of switches and diode conduction over one switching period.
| Stage | Q1 | Q2 | Q3 | Q5 | Q6 | D1 | D2 |
|---|---|---|---|---|---|---|---|
| 1-2 (Mode I) | ON | OFF | OFF | OFF | body diode ON | OFF | OFF |
| 3 (Mode I) | OFF | OFF | OFF | body diode ON | OFF | OFF | OFF |
| 4 (Mode I) | OFF | OFF | ON | body diode ON | OFF | OFF | ON |
| 3 (Mode II) | OFF | ON | OFF | body diode ON | OFF | ON | OFF |
| … (rest similar) | … | … | … | … | … | … | … |
Control Strategy and Power Decoupling
The control objective is to maintain constant PV output power while shaping the AC current into a sine wave. The two peak current references ipeak1 and ipeak2 are crucial. The first reference is derived from maximum power point tracking (MPPT). Under constant input power assumption, ipeak1 is given by:
$$ i_{peak1} = \sqrt{\frac{2 P_{pv} T_s}{L_m}} $$
where Ts is the switching period and Lm the magnetizing inductance. The on-time of Q1 is then:
$$ d_1 T_s = \frac{L_m i_{peak1}}{v_{pv}} $$
For sinusoidal output, the required instantaneous power at time t0 is 2Ppv sin²(ωt0). The required energy stored in the transformer determines ipeak2:
$$ i_{peak2} = \sqrt{\frac{P_{pv} T_s}{L_m}} \, |2\sin(\omega t_0)| $$
In Mode I, the charging time of Cs (stage 3) is:
$$ d_{ch} T_s = \frac{L_m (i_{peak1} – i_{peak2})}{v_{Cs}} $$
In Mode II, the discharging time (Q2 on) is:
$$ d_{dis} T_s = \frac{L_m (i_{peak2} – i_{peak1})}{v_{Cs}} \cdot \frac{n_2}{n_1} $$
A voltage loop around vCs adjusts the average value to keep the power balance stable. The control implementation uses a digital controller (STM32F407VET6) with PI regulators.
Key Parameter Design
I select the storage capacitor Cs to handle the double-line-frequency energy variation. The required capacitance is:
$$ C_s = \frac{P_{pv}}{\omega V_{Cs\_avg} \Delta V_{Cs}} $$
With a rated power of 80 W and choosing VCs_avg = 210 V and ΔVCs = 33 V, I obtain Cs = 40 μF. This value allows the use of a long-life film capacitor instead of an electrolytic one. To ensure proper active clamp operation, the minimum voltage of Cs must exceed the reflected AC voltage:
$$ V_{Cs\_min} > v_{ac} \frac{n_1}{n_3} $$
The magnetizing inductance Lm must be designed such that the converter operates in discontinuous conduction mode (DCM). The condition is:
$$ L_m < \frac{T_s}{2 P_{pv}} \left[ \frac{1}{v_{pv}} + \frac{1 – 2|\sin(100\pi t)|}{v_{Cs}} + \frac{n_3}{V_{rms} n_1} \right]^{-2} $$
Additionally, the sum of duty ratios must leave enough time for the active clamp and dead time. I choose Lm = 60 μH. For soft switching, the leakage inductance must provide enough energy to discharge the parasitic capacitance of Q1 (Cds1 = 700 pF). The required Q5 on-time is:
$$ d_{acf} T_s \geq \sqrt{L_k C_{ds1}} \cdot \frac{V_{pv} + v_{Cs}}{v_{Cs} – v_{ac} \frac{n_1}{n_3}} $$
With Lk = 5.5 μH, I set dacf accordingly. The dead time between Q5 turn-off and Q1 turn-on must exceed one quarter of the resonant period:
$$ d_{dead} T_s \geq \frac{\pi}{2} \sqrt{L_k C_{ds1}} $$
Table 2 summarizes the selected component values and their voltage/current ratings.
| Parameter | Symbol | Value |
|---|---|---|
| Input voltage | vpv | 50 V |
| AC voltage (RMS) | Vrms | 110 V |
| Rated power | Ppv | 80 W |
| Switching frequency | fs | 50 kHz |
| Transformer turns ratio | n1:n2:n3:n4 | 1:1:1.1:1.1 |
| Magnetizing inductance | Lm | 60 μH |
| Leakage inductance | Lk | 5.5 μH |
| Input filter capacitor | Cin | 6.8 μF (film) |
| Storage/clamp capacitor | Cs | 40 μF (film) |
| Q1 parasitic capacitance | Cds1 | 700 pF |
| Device | Part Number | Rating |
|---|---|---|
| Q1 | NCE65T260F | 650 V / 26 A |
| Q2 | MS15N100HGT1 | 1000 V / 15 A |
| Q3, Q4 | NCE70T180F | 700 V / 18 A |
| Q5, Q6 | CI19N120SM | 1200 V / 19 A |
| D1, D2, D3 | DSEI30-10A | 1000 V / 30 A |
Simulation and Experimental Results
I built an 80 W prototype controlled by an STM32F407VET6 microcontroller. The simulation (using PSIM) and experimental results confirm the theoretical analysis. Key waveforms include the PV input current ipv, AC output voltage vac and current iac, and the storage capacitor voltage vCs. In steady state, the average vCs is 211 V with a ripple of 35 V, closely matching the design. The output current THD is 2.17%, well below the IEEE 1547.2 limit. The PV input current ripple is less than 10%, indicating effective power decoupling. Figure (refer to the conceptual waveforms in the original description) shows the soft-switching behavior of Q1: the drain-source voltage drops to zero before the gate pulse arrives, confirming ZVS. The measured peak efficiency reaches 81% at approximately 60 W load, which is 1.6% higher than a version without active clamp. Table 4 compares the proposed topology with other reported types of solar inverters in the literature.
| Reference | Rated Power (W) | Input Voltage (V) | Number of Switches | Filter Capacitance (μF) | Storage Capacitor (μF) | Peak Efficiency (%) |
|---|---|---|---|---|---|---|
| [13] | 100 | 35 | 7 | 20 | 40 | 70 |
| [14] | 100 | 35 | 8 | 15 | 44 | 73 |
| [21] | 80 | 50 | 7 | 560 | — | 82.3 |
| This work | 80 | 50 | 9 | 6.8 | 40 | 81 |
The proposed micro-inverter uses a small film capacitor (6.8 μF) for input filtering, demonstrating a significant improvement in lifetime compared to conventional designs that require large electrolytic capacitors (e.g., 560 μF in [21]). Although the switch count is slightly higher than some other types of solar inverters, the integration of power decoupling and active clamp eliminates the need for a separate bulky electrolytic capacitor, thereby enhancing reliability. The efficiency is competitive, and the ZVS operation reduces electromagnetic interference.
Conclusion
I have proposed and validated an active clamp power decoupling flyback micro-inverter that addresses the longevity issue of traditional micro-inverters by replacing electrolytic capacitors with film capacitors. The circuit integrates power decoupling and active clamp functions into a single storage capacitor, achieving low input current ripple, zero-voltage switching of the main switch, and leakage energy recovery. Experimental results from an 80 W prototype show an input ripple below 10%, output THD less than 5%, and a peak efficiency of 81%. This work provides a practical solution among various types of solar inverters for distributed photovoltaic systems where reliability and compactness are critical. Future research will focus on further improving efficiency through advanced modulation schemes and exploring the integration of this topology with other types of solar inverters for higher power applications.