In the context of accelerating global energy transition and climate change mitigation, electric vehicles (EVs) have emerged as a pivotal component of sustainable transportation. The integration of EVs with the power grid, facilitated by Vehicle-to-Grid (V2G) technology, unlocks the potential of EV batteries as distributed energy storage systems. This enables critical grid services such as peak shaving, frequency regulation, and enhanced renewable energy utilization. The core power electronic interface enabling this bidirectional energy flow is the grid tied inverter. When operating in discharge mode, this grid tied inverter functions to inject power from the EV’s battery into the grid. The stability and quality of this power injection are fundamentally dependent on the precise regulation of the intermediate DC bus voltage. However, the control of this DC link in a grid tied inverter presents significant challenges due to system nonlinearities, strong coupling between control loops, and susceptibility to multi-source disturbances like load changes and grid voltage sags. Traditional control methodologies often fall short in this demanding environment.
Conventional approaches for controlling a grid tied inverter typically employ a PI-based dual-loop control structure. The outer voltage loop regulates the DC bus voltage, while the inner current loop manages the grid current. Despite its widespread use, the PI controller’s performance is inherently limited. Its design relies heavily on an accurate linear model of the system, which is difficult to obtain due to the grid tied inverter‘s nonlinear characteristics. Furthermore, PI controllers struggle with rejecting disturbances that are not within their designed bandwidth, leading to slow transient response and significant voltage overshoot or undershoot during dynamic events. These limitations can compromise the power quality injected into the grid and potentially stress the power semiconductor devices. Therefore, developing an advanced control strategy that offers robust performance, fast dynamic response, and strong disturbance rejection is paramount for the reliable operation of V2G systems.
This article addresses these challenges by proposing a novel improved dual-loop control strategy for the DC bus voltage of a grid tied inverter in V2G applications. The core innovation lies in the synergistic combination of two modern control techniques: Model Predictive Power Control (MPDPC) for the inner loop and first-order Linear Active Disturbance Rejection Control (LADRC) for the outer voltage loop. The inner MPDPC loop directly controls the active and reactive power fed into the grid, offering superior dynamic performance and inherent handling of system constraints. The outer LADRC loop is designed to robustly regulate the DC bus voltage by actively estimating and compensating for total disturbances, encompassing both internal model uncertainties and external perturbations. This LADRC+MPDPC structure is specifically engineered to enhance the grid tied inverter‘s transient response and immunity to multi-source interference. I will provide a comprehensive derivation of the system model, detailed design of both control loops, and extensive simulation studies comparing the proposed method against traditional PI dual-loop and PI+MPDPC strategies under various disturbance scenarios.
The power circuit of a two-stage V2G system is considered. The first stage is a bidirectional DC-DC converter interfacing the EV battery, providing wide voltage regulation. The second stage, which is the focus of this control design, is the three-phase voltage source grid tied inverter. It is connected to the grid through an LCL or L filter (represented here as an L filter for simplicity in control derivation). The primary objective of this grid tied inverter is to control the power flow between the DC bus and the AC grid while maintaining a stable DC link voltage and ensuring high-quality grid currents. The mathematical model of the three-phase grid tied inverter in the stationary abc frame is given by:
$$ L_s \frac{d\mathbf{i}_{abc}}{dt} = \mathbf{e}_{abc} – R_s \mathbf{i}_{abc} – \mathbf{u}_{abc} $$
where \( L_s \) and \( R_s \) are the grid filter inductance and equivalent resistance, \( \mathbf{e}_{abc} \), \( \mathbf{i}_{abc} \), and \( \mathbf{u}_{abc} \) are the three-phase grid voltage, inverter output current, and inverter bridge voltage vectors, respectively. For control design, it is standard practice to transform this model into the synchronous rotating dq reference frame, which aligns with the grid voltage vector. This transformation converts AC quantities into DC quantities, simplifying the controller design. The model in the dq frame is:
$$ \begin{aligned}
L_s \frac{di_d}{dt} &= e_d – R_s i_d – u_d + \omega L_s i_q \\
L_s \frac{di_q}{dt} &= e_q – R_s i_q – u_q – \omega L_s i_d
\end{aligned} $$
Here, \( i_d \) and \( i_q \) are the d-axis and q-axis currents (representing active and reactive power components), \( u_d \) and \( u_q \) are the corresponding inverter voltages, \( e_d \) and \( e_q \) are the grid voltages (with \( e_q \) typically zero after alignment), and \( \omega \) is the grid angular frequency. The cross-coupling terms \( \omega L_s i_q \) and \( -\omega L_s i_d \) are evident. Traditional vector control uses feedforward decoupling to separate the d and q axes. The power balance between the DC and AC sides is crucial for voltage regulation. The relationship between the DC bus power and the AC side power, neglecting losses, is:
$$ P_{dc} = V_{dc} I_{dc} \approx \frac{3}{2}(e_d i_d + e_q i_q) = P_{ac} $$
The dynamics of the DC bus voltage \( V_{dc} \) across the capacitor \( C_{dc} \) can be described by:
$$ C_{dc} \frac{dV_{dc}}{dt} = I_{in} – I_{out} = \frac{P_{bat}}{V_{dc}} – \frac{P_{ac}}{V_{dc}} $$
where \( P_{bat} \) is the power from the battery-side DC-DC converter. This equation highlights that to maintain a constant \( V_{dc} \), the active power injected into the grid \( P_{ac} \) must be controlled to balance the input power \( P_{bat} \). Any mismatch causes the DC capacitor to charge or discharge, leading to voltage fluctuations. The outer voltage controller’s role is to generate the active power reference \( P_{ref} \) (or equivalently, the d-axis current reference \( i_d^* \)) to achieve this balance robustly.
Inner Loop Design: Model Predictive Power Control (MPDPC)
The inner control loop is responsible for fast, accurate tracking of the active and reactive power references generated by the outer loop. I choose Model Predictive Power Control for this task due to its excellent dynamic performance, direct handling of system constraints (like voltage limits), and intuitive design. Unlike current control, MPDPC directly operates on the power quantities, which aligns perfectly with the overall control objective for a grid tied inverter. The core idea is to use a discrete-time model of the system to predict the future behavior of active power \( p \) and reactive power \( q \) for all possible voltage vectors the inverter can apply, and then select the one that minimizes a cost function.
The instantaneous three-phase power can be calculated in the stationary αβ frame after applying Clarke’s transformation to measured grid voltages \( e_{abc} \) and currents \( i_{abc} \):
$$ \begin{aligned}
p &= e_{\alpha} i_{\alpha} + e_{\beta} i_{\beta} \\
q &= e_{\beta} i_{\alpha} – e_{\alpha} i_{\beta}
\end{aligned} $$
To derive the prediction model, the derivatives of power are needed. Differentiating the above equations and substituting the model of the grid tied inverter in the αβ frame \( (L_s di_{\alpha\beta}/dt = e_{\alpha\beta} – R_s i_{\alpha\beta} – u_{\alpha\beta}) \) and the derivatives of balanced grid voltages \( (de_{\alpha}/dt = -\omega e_{\beta}, de_{\beta}/dt = \omega e_{\alpha}) \), we obtain:
$$ \begin{aligned}
\frac{dp}{dt} &= \frac{1}{L_s} (e_{\alpha}^2 + e_{\beta}^2 – e_{\alpha}u_{\alpha} – e_{\beta}u_{\beta} – R_s(e_{\alpha}i_{\alpha}+e_{\beta}i_{\beta})) + \omega(e_{\alpha}i_{\beta} – e_{\beta}i_{\alpha}) \\
\frac{dq}{dt} &= \frac{1}{L_s} (e_{\alpha}u_{\beta} – e_{\beta}u_{\alpha} + R_s(e_{\alpha}i_{\beta} – e_{\beta}i_{\alpha})) + \omega(e_{\alpha}i_{\beta} – e_{\beta}i_{\alpha})
\end{aligned} $$
For digital implementation, these continuous-time derivatives must be discretized. Using a forward Euler approximation with a sampling period \( T_s \), the power increments are:
$$ \begin{aligned}
\Delta p(k) &= \frac{dp}{dt}\bigg|_{k} \cdot T_s \\
\Delta q(k) &= \frac{dq}{dt}\bigg|_{k} \cdot T_s
\end{aligned} $$
Therefore, the predicted power at the next sampling instant \( (k+1) \) is:
$$ \begin{aligned}
p(k+1) &= p(k) + \Delta p(k) \\
q(k+1) &= q(k) + \Delta q(k)
\end{aligned} $$
In a three-phase two-level grid tied inverter, there are eight possible switching states (six active vectors and two zero vectors). For each candidate voltage vector \( u_{\alpha\beta}(k) \), the predicted powers \( p(k+1) \) and \( q(k+1) \) are calculated. The optimal vector is selected by minimizing a cost function \( J \), which typically penalizes the error between predicted and reference powers:
$$ J = [p(k+1) – p_{ref}]^2 + [q(k+1) – q_{ref}]^2 $$
Here, \( p_{ref} \) is provided by the outer voltage controller, and \( q_{ref} \) is usually set to zero for unity power factor operation. This direct power control method inherently accounts for the system’s nonlinearities and coupling, providing very fast transient response without the need for modulator stages like PWM. The computational burden is manageable given modern microprocessors and the limited number of voltage vectors to evaluate.
Outer Loop Design: First-Order Linear Active Disturbance Rejection Control (LADRC)
The outer voltage loop is the cornerstone for maintaining DC bus stability against disturbances. I propose a first-order Linear Active Disturbance Rejection Controller for this purpose. LADRC is a powerful control technique that treats the aggregate effect of model uncertainties, parameter variations, and external disturbances as a “total disturbance,” which is then estimated and compensated in real-time. This approach significantly reduces the controller’s dependence on a precise mathematical model of the plant, making it highly suitable for a complex system like a grid tied inverter. The first-order version is chosen over higher-order ADRC for its simplicity, ease of parameter tuning, and practicality for engineering implementation.
The controlled plant for the outer loop is the relationship between the active power reference \( p_{ref} \) (control input) and the DC bus voltage \( V_{dc} \) (output). From the power balance equation, a simplified dynamic model can be derived. Assuming the inner MPDPC loop is ideally fast, it can track \( p_{ref} \) instantaneously, so \( P_{ac} \approx p_{ref} \). The DC bus dynamics are then:
$$ C_{dc} V_{dc} \frac{dV_{dc}}{dt} = P_{bat} – p_{ref} $$
For control design, it’s often convenient to use the square of the DC voltage \( y = V_{dc}^2 \) as the output. This yields a linear relationship with power. The derivative is \( \dot{y} = 2V_{dc} \dot{V}_{dc} \). Substituting, we get:
$$ \frac{C_{dc}}{2} \frac{dy}{dt} = P_{bat} – p_{ref} $$
Rearranging:
$$ \frac{dy}{dt} = \frac{2}{C_{dc}} P_{bat} – \frac{2}{C_{dc}} p_{ref} $$
The term \( \frac{2}{C_{dc}} P_{bat} \) can be viewed as an external disturbance \( d(t) \), as it originates from the upstream converter or load changes. The control input is \( u = p_{ref} \). Therefore, the plant can be expressed as a first-order system with a generalized disturbance \( f(t) \):
$$ \dot{y} = b u + f $$
$$ \text{where } b = -\frac{2}{C_{dc}}, \quad f = d(t) + \Delta $$
Here, \( \Delta \) represents any other unmodeled dynamics or disturbances. A first-order LADRC for this system consists of two main components: a Linear Extended State Observer (LESO) and a Linear State Error Feedback (LSEF) law.
1. Linear Extended State Observer (LESO):
The LESO expands the system state to include an additional state \( x_2 \) that represents the total disturbance \( f \). Define \( x_1 = y \) and \( x_2 = f \). The augmented state-space model is:
$$ \begin{aligned}
\dot{x}_1 &= x_2 + b u \\
\dot{x}_2 &= \dot{f} = h \quad (\text{assumed unknown but bounded})
\end{aligned} $$
A second-order LESO is constructed to estimate both \( x_1 \) and \( x_2 \):
$$ \begin{aligned}
\dot{z}_1 &= \beta_1 (y – z_1) + z_2 + b_0 u \\
\dot{z}_2 &= \beta_2 (y – z_1)
\end{aligned} $$
Here, \( z_1 \) and \( z_2 \) are estimates of \( x_1 \) (output) and \( x_2 \) (total disturbance), respectively. \( b_0 \) is a rough estimate of the control gain \( b \), which is easier to obtain than an exact value. \( \beta_1 \) and \( \beta_2 \) are observer gains. These gains can be parameterized by a single parameter, the observer bandwidth \( \omega_o \), using pole placement techniques to place both observer poles at \( -\omega_o \):
$$ \beta_1 = 2\omega_o, \quad \beta_2 = \omega_o^2 $$
This bandwidth parameterization greatly simplifies tuning. The LESO dynamically tracks both the output and the total disturbance, providing \( z_2 \) as an estimate of \( f \).
2. Linear State Error Feedback (LSEF) and Disturbance Rejection:
With the disturbance estimate \( z_2 \) available, the control law is designed to actively cancel it and achieve the desired tracking. The LSEF for a first-order system is a simple proportional control on the tracking error. The control law is:
$$ u = \frac{1}{b_0} [ K_p (r – z_1) – z_2 ] $$
where \( r \) is the reference signal for \( y \) (i.e., \( V_{dc,ref}^2 \)), and \( K_p \) is the proportional gain. Substituting this \( u \) into the plant equation \( \dot{y} \approx b u + z_2 \) (assuming perfect estimation \( z_2 \approx f \)) yields the closed-loop dynamics:
$$ \dot{y} = \frac{b}{b_0} K_p (r – z_1) – \frac{b}{b_0} z_2 + z_2 \approx K_p (r – y) \quad \text{if } b \approx b_0 $$
Thus, the disturbance is canceled, and the system is reduced to a simple first-order tracking system \( \dot{y} = K_p (r – y) \). The controller bandwidth \( \omega_c \) is defined by \( K_p = \omega_c \). The tuning parameters for the entire first-order LADRC are therefore \( \omega_c \), \( \omega_o \), and \( b_0 \). A common rule of thumb is \( \omega_o = (2 \sim 5) \omega_c \) to ensure the observer is faster than the controller. This elegant tuning method, known as the “bandwidth parameterization,” makes LADRC highly practical for the grid tied inverter application.
The complete block diagram of the proposed LADRC outer loop combined with the MPDPC inner loop for the grid tied inverter is conceptualized as follows: The DC bus voltage \( V_{dc} \) is measured, squared, and compared to the squared reference. The error is processed by the LADRC, which outputs the active power reference \( p_{ref} \). This, along with \( q_{ref}=0 \), is fed to the MPDPC block. The MPDPC uses the measured grid voltages and currents to compute the optimal inverter switching state for the next sampling period, thereby driving the grid tied inverter.
Simulation Analysis and Comparative Study
To validate the performance of the proposed LADRC+MPDPC control strategy for the grid tied inverter, I conducted comprehensive simulation studies in the MATLAB/Simulink environment. The system parameters used for simulation are summarized in Table 1.
| Parameter | Symbol | Value |
|---|---|---|
| Grid Voltage (RMS, line-to-neutral) | \( E_{grid} \) | 311 V |
| Grid Frequency | \( f_g \) | 50 Hz |
| DC Bus Capacitance | \( C_{dc} \) | 4 mF |
| DC Bus Voltage (Nominal) | \( V_{dc,ref} \) | 700 V |
| Filter Inductance | \( L_s \) | 1 mH |
| Filter Resistance | \( R_s \) | 0.1 Ω |
| Switching / Sampling Frequency | \( f_s \) | 10 kHz |
Three control strategies were implemented and compared:
- Conventional PI Dual-Loop (PI-PI): Outer voltage PI and inner dq-current PI with decoupling.
- PI + MPDPC (PI-MPDPC): Outer voltage PI controller with inner MPDPC loop.
- Proposed LADRC + MPDPC (LADRC-MPDPC): Outer first-order LADRC with inner MPDPC loop.
The controller parameters for each strategy, tuned for a fair comparison, are listed in Table 2.
| Control Strategy | Outer Loop Parameters | Inner Loop Parameters |
|---|---|---|
| PI-PI | \( K_{p,v} = 0.8, K_{i,v} = 40 \) | \( K_{p,i} = 15, K_{i,i} = 1000 \) |
| PI-MPDPC | \( K_{p,v} = 0.8, K_{i,v} = 40 \) | MPDPC (Cost function \( J \)) |
| LADRC-MPDPC | \( \omega_c = 100 \, \text{rad/s}, \omega_o = 500 \, \text{rad/s}, b_0 = -0.0005 \) | MPDPC (Cost function \( J \)) |
Three distinct test scenarios were designed to evaluate transient performance, disturbance rejection, and robustness.
Scenario 1: Step Change in DC Voltage Reference. This test evaluates the tracking performance and transient response. Initially, \( V_{dc,ref} = 700 \, \text{V} \). At \( t = 0.3 \, \text{s} \), it steps up to 730 V. At \( t = 0.6 \, \text{s} \), it steps down to 670 V. The performance metrics are overshoot/undershoot and settling time. The results are summarized in Table 3 and described below.
| Control Strategy | Rise Time (ms) | Overshoot (%) | Settling Time (ms, to within 1%) |
|---|---|---|---|
| PI-PI | ~85 | 4.5% | ~120 |
| PI-MPDPC | ~35 | < 0.5% | ~60 |
| LADRC-MPDPC | ~25 | < 0.2% | ~30 |
The LADRC-MPDPC strategy demonstrated the fastest response with virtually no overshoot. The MPDPC inner loop inherently provides swift power tracking, while the LADRC outer loop effectively manages the voltage dynamics without aggressive gains that cause overshoot. The traditional PI-PI control showed significant overshoot and the slowest response due to the cascaded structure and limited bandwidth.
Scenario 2: Grid Voltage Sag (Disturbance Rejection). The grid tied inverter must maintain DC bus stability during grid faults. A 30% balanced voltage sag was applied at \( t = 0.5 \, \text{s} \) for a duration of 0.2 s. The key metric is the maximum deviation of \( V_{dc} \) from its reference and the recovery time. Table 4 presents the results.
| Control Strategy | Max Voltage Dip | Recovery Time (ms) |
|---|---|---|
| PI-PI | ~12 V (1.7%) | ~150 |
| PI-MPDPC | ~6 V (0.86%) | ~80 |
| LADRC-MPDPC | ~3 V (0.43%) | ~40 |
The proposed LADRC-MPDPC control significantly outperformed the others. The LESO quickly estimated the disturbance caused by the sudden change in grid conditions (affecting power transfer), and the control law compensated for it promptly. This showcases the enhanced low-voltage ride-through (LVRT) capability of the grid tied inverter with the proposed controller.
Scenario 3: Ramp Disturbance on the DC Bus. To test robustness against slow-varying disturbances, a ramp disturbance with a slope equivalent to 300 W/s was injected into the DC bus power balance equation at \( t = 0.4 \, \text{s} \). This could emulate a slowly changing load or source power. The control objective is to minimize the steady-state deviation during the ramp and reject it. The integral of absolute error (IAE) during the disturbance period was calculated as a performance index, as shown in Table 5.
| Control Strategy | IAE (V·s) | Max Instantaneous Error (V) |
|---|---|---|
| PI-PI | 2.85 | 3.1 |
| PI-MPDPC | 1.12 | 1.4 |
| LADRC-MPDPC | 0.41 | 0.7 |
The LADRC-based controller excelled again. Its disturbance estimation and cancellation mechanism effectively nullified the effect of the ramp, keeping the DC voltage tightly regulated. The PI controllers, lacking such an estimation mechanism, exhibited larger and persistent errors.
To further illustrate the dynamic response, the closed-loop characteristic equation for the LADRC-controlled voltage loop can be approximated. With perfect disturbance estimation, the transfer function from reference \( r \) to output \( y \) is:
$$ \frac{Y(s)}{R(s)} = \frac{\omega_c}{s + \omega_c} $$
This simple first-order behavior explains the smooth, non-oscillatory response observed in the simulations. In contrast, the PI-based outer loop, when combined with the higher-order plant dynamics, often results in a more complex closed-loop system prone to overshoot.
Conclusion
This article has presented a comprehensive study on improving the DC bus voltage control for a grid tied inverter operating within a V2G system. The inherent limitations of conventional PI-based control under nonlinearities and multi-source disturbances were identified. To overcome these challenges, an advanced dual-loop control strategy was proposed, integrating a Model Predictive Power Control inner loop and a first-order Linear Active Disturbance Rejection Control outer loop. The MPDPC provides direct, fast, and precise control of the grid-injected power, while the LADRC offers robust voltage regulation by actively estimating and rejecting total disturbances, including those from the grid side and the DC side.
The theoretical foundations for both control techniques were detailed, including mathematical derivations of the grid tied inverter model, the MPDPC prediction algorithm, and the LADRC observer and control law. The parameter tuning for LADRC was simplified using the bandwidth parameterization method, enhancing its practicality for engineering applications. A thorough simulation-based comparative analysis was conducted, evaluating the proposed LADRC+MPDPC strategy against conventional PI dual-loop and PI+MPDPC strategies under three critical scenarios: reference step changes, grid voltage sags, and ramp disturbances. The results consistently demonstrated the superiority of the proposed method. It achieved the fastest transient response with minimal overshoot, the smallest voltage deviation during grid sags, and the strongest rejection of slow-varying disturbances. This translates to a more stable and reliable operation of the grid tied inverter, ensuring higher power quality injection into the grid and better support for grid services through V2G. Future work may involve experimental validation on a hardware prototype, extension to unbalanced grid conditions, and exploration of adaptive tuning for the LADRC parameters to further optimize performance across a wider operating range of the grid tied inverter.