With the rapid advancement of power electronics, three-phase inverters controlled by pulse width modulation (PWM) have become integral in applications such as AC drive systems, electric vehicles, and marine vessels. These systems often face challenges related to PWM noise peaks in the output line voltage, which can lead to acoustic noise in motors and electromagnetic interference. Traditional fixed-carrier-frequency PWM methods concentrate high-peak noise at the carrier frequency and its harmonics, necessitating techniques like random PWM (RPWM) to disperse this noise across a broader frequency band. While RPWM methods have been extensively studied for two-level inverters, their application to multilevel inverters, particularly cascaded H-bridge (CHB) topologies, remains limited. Asymmetric CHB inverters, with voltage ratios like 1:1:1:3, offer advantages such as reduced component count and lower output voltage total harmonic distortion (THD) compared to symmetric counterparts. However, they suffer from power imbalance among low-voltage H-bridge units and high PWM noise peaks. This paper addresses these issues by proposing a power-balanced hybrid random PWM (PB-HRPWM) method that integrates step-wave modulation, in-phase disposition (IPD) carrier stacking, random frequency modulation, and power balancing through pulse logic operations. The method aims to reduce line voltage THD, lower PWM noise peaks, and ensure power equilibrium in low-voltage H-bridge units. Simulations and experiments validate the effectiveness of the proposed approach, demonstrating superior performance over conventional PWM techniques.
The asymmetric CHB three-phase inverter topology under study consists of phases A, B, and C, each comprising a high-voltage H-bridge unit (e.g., AH) and low-voltage H-bridge units (e.g., AL1, AL2, AL3) connected in series. The DC voltage ratios are set to 1:1:1:3, with low-voltage units at E and the high-voltage unit at 3E. This configuration enables the phase voltage to generate 13 levels (0, ±E, ±2E, …, ±6E) and the line voltage to produce 25 levels (0, ±E, ±2E, …, ±12E), enhancing waveform quality and reducing harmonic distortion. The proposed PB-HRPWM method leverages this topology to optimize performance. Key components include modulation waves for high-voltage and low-voltage units, random carriers for low-voltage units, and pulse logic operations for power balancing. The high-voltage unit employs step-wave modulation, switching at fundamental frequency to minimize losses, while the low-voltage units use IPD-based random carriers to disperse noise. Power imbalance among low-voltage units is mitigated by cyclically distributing pulses over 1.5 times the fundamental period, ensuring equal average output power. This integration of techniques results in a robust modulation strategy suitable for high-power applications.
The PB-HRPWM method operates in four main steps. First, the modulation wave for the high-voltage H-bridge unit, denoted as \( v_{ah} \), is compared with reference levels (e.g., ±3E) to generate driving pulses for the high-voltage unit and the modulation wave for the low-voltage units, \( v_{al} \). For modulation indices \( m \in [0, 0.5] \), \( v_{ah} = 0 \), and for \( m \in (0.5, 1] \), it is defined as \( v_{ah} = 6mE \sin(\omega t) \). The low-voltage modulation wave \( v_{al} \) is derived accordingly, ensuring proper level generation. Second, random triangular carriers with frequencies varying between \( f_{c0} – \Delta f \) and \( f_{c0} + \Delta f \) are compared with \( v_{al} \) to produce random pulses for the low-voltage units. The carrier frequency \( f_c \) is given by:
$$ f_c = f_{c0} + R_n \Delta f $$
where \( f_{c0} \) is the center frequency, \( \Delta f \) is the random bandwidth, and \( R_n \in [-1, 1] \) is a random number generated using algorithms like Logistic or Markov chain. Third, pulse logic operations distribute these random pulses to the low-voltage H-bridge units (AL1, AL2, AL3) over intervals of 0.5 times the fundamental period \( T_{ah} \). The logic operations, as shown in Equations (1) to (3), ensure that each unit experiences a balanced mix of voltage levels, promoting power equilibrium. For instance, the driving pulses for AL1 are computed as:
$$ S_{a11} = X_{a11} L_1 + X_{a31} L_3 + X_{a21} L_5 $$
$$ S_{a12} = \overline{S_{a11}} $$
$$ S_{a13} = X_{a23} L_2 + X_{a13} L_4 + X_{a33} L_6 $$
$$ S_{a14} = \overline{S_{a13}} $$
Similar equations apply for AL2 and AL3, cyclically shifting the pulses. Finally, the driving pulses control the inverter switches, producing the output voltages. The phase voltage \( u_{an} \) is the sum of high-voltage and low-voltage unit outputs:
$$ u_{an} = u_{ah} + u_{al} $$
$$ u_{al} = u_{a1} + u_{a2} + u_{a3} $$
This approach decouples power balancing from modulation wave or carrier reconstruction, simplifying digital implementation in processors like DSPs or FPGAs.
To analyze power distribution, the average output power of each low-voltage H-bridge unit is derived. The average voltage \( \overline{u_{al}} \) in a carrier period equals the instantaneous value of \( v_{al} \) when the carrier frequency is much higher than the output frequency. For \( m \in (0.5, 1] \), \( v_{al} \) is segmented into basic voltages (e.g., \( v_{11}, v_{12}, v_{13} \) in interval I and \( v_{21}, v_{22}, v_{23} \) in interval II). The phase current \( i_a = I_a \sin(\omega t – \phi) \) is used to compute the average power \( P_{Aji} \) for each basic voltage. Calculations show that \( P_{A11} = P_{A21} \), \( P_{A12} = P_{A22} \), and \( P_{A13} = P_{A23} \), ensuring that over 1.5 fundamental periods, the total average powers for AL1, AL2, and AL3 are equal:
$$ P_{AL1} = P_{A11} + P_{A22} + P_{A13} $$
$$ P_{AL2} = P_{A12} + P_{A23} + P_{A11} $$
$$ P_{AL3} = P_{A13} + P_{A21} + P_{A12} $$
$$ P_{AL1} = P_{AL2} = P_{AL3} $$
This confirms the power balancing capability of the PB-HRPWM method across varying modulation indices.
Simulations were conducted in MATLAB/Simulink to evaluate the proposed method. The parameters are summarized in Table 1, comparing PB-HRPWM with existing methods like PC-RPWM, PS-RPWM, PS-HPWM, and POD-HPWM. The average switching frequency \( f_{av} \) is maintained at 6 kHz for fair comparison. For the asymmetric CHB three-phase inverter, low-voltage units have DC sources of 12 V, and the high-voltage unit has 36 V. Random carrier frequencies for PB-HRPWM range from 3 to 9 kHz (\( f_{c0} = 6 \) kHz, \( \Delta f = 3 \) kHz), while fixed carriers are used for non-random methods.
| Parameter | Value |
|---|---|
| DC Voltage (1H) | 72 V/HU |
| DC Voltage (4H) – Low | 12 V/LH |
| DC Voltage (4H) – High | 36 V/HH |
| Carrier Frequency (PS-HPWM) | 1 kHz (fixed, \( f_{av} = 6 \) kHz) |
| Carrier Frequency (PC-RPWM, PS-RPWM) | 1.5–4.5 kHz (random, \( f_{c0} = 3 \) kHz, \( \Delta f = 1.5 \) kHz, \( f_{av} = 6 \) kHz) |
| Carrier Frequency (POD-HPWM) | 6 kHz (fixed, \( f_{av} = 6 \) kHz) |
| Carrier Frequency (PB-HRPWM) | 3–9 kHz (random, \( f_{c0} = 6 \) kHz, \( \Delta f = 3 \) kHz, \( f_{av} = 6 \) kHz) |
| Output Frequency | 50 Hz |
| Load (R, L) | 10 Ω, 3 mH (star-connected) |
Line voltage waveforms and THD were analyzed for modulation indices \( m = 0.3, 0.6, \) and 0.9. Under PB-HRPWM, the line voltage \( u_{ab} \) exhibits 9, 15, and 21 levels for these indices, with THD values of 17.42%, 9.08%, and 6.21%, respectively. The power distribution among low-voltage units is balanced, as shown in Table 2, where average powers for AL1, AL2, and AL3 are nearly identical across modulation indices. For example, at \( m = 0.6 \), \( P_{AL1} = 37.83 \) W, \( P_{AL2} = 37.84 \) W, and \( P_{AL3} = 37.83 \) W.
| Modulation Index (m) | P_{AL1} (W) | P_{AL2} (W) | P_{AL3} (W) |
|---|---|---|---|
| 0.3 | 23.09 | 23.09 | 23.10 |
| 0.6 | 37.83 | 37.84 | 37.83 |
| 0.9 | 85.49 | 85.48 | 85.49 |
PWM noise performance was evaluated by measuring the first and second noise peaks in frequency bands of 3–9 kHz and 9–15 kHz. For PB-HRPWM, at \( m = 0.6 \), the first peak is –11.16 dBV and the second is –13.06 dBV, indicating effective noise dispersion. Comparative analysis with other methods, as shown in Table 3, reveals that PB-HRPWM consistently achieves lower noise peaks and THD. For instance, at \( m = 0.6 \), PC-RPWM and PS-RPWM have higher THD (1.212% and 1.211%, respectively) compared to PB-HRPWM (0.094%). Similarly, fixed-carrier methods like PS-HPWM and POD-HPWM exhibit concentrated noise at multiples of 6 kHz, whereas random methods disperse noise across the spectrum.
| Method | m | THD (%) | 1st Noise Peak (dBV) | 2nd Noise Peak (dBV) |
|---|---|---|---|---|
| PC-RPWM | 0.3 | 1.978 | -8.50 | -9.20 |
| 0.6 | 1.212 | -9.10 | -10.50 | |
| 0.9 | 0.804 | -8.80 | -10.80 | |
| PS-RPWM | 0.3 | 1.989 | -8.60 | -9.30 |
| 0.6 | 1.211 | -9.00 | -10.40 | |
| 0.9 | 0.806 | -8.70 | -10.70 | |
| PS-HPWM | 0.3 | 0.298 | -5.20 | -6.10 |
| 0.6 | 0.156 | -5.50 | -6.50 | |
| 0.9 | 0.110 | -5.80 | -6.80 | |
| POD-HPWM | 0.3 | 0.314 | -5.40 | -6.30 |
| 0.6 | 0.167 | -5.60 | -6.60 | |
| 0.9 | 0.108 | -5.90 | -6.90 | |
| PB-HRPWM | 0.3 | 0.181 | -11.03 | -11.52 |
| 0.6 | 0.094 | -11.16 | -13.06 | |
| 0.9 | 0.067 | -10.05 | -13.08 |
Experimental validation was performed on prototype inverters with parameters matching the simulations. The line voltage waveforms and spectra for PB-HRPWM at \( m = 0.3, 0.6, \) and 0.9 confirm the simulation results, showing multi-level outputs and dispersed noise. The measured THD values, as listed in Table 4, are lower for PB-HRPWM compared to other methods. For example, at \( m = 0.6 \), PB-HRPWM achieves a THD of 0.094%, while PC-RPWM and PS-RPWM yield 1.212% and 1.211%, respectively. Noise peak measurements also demonstrate the superiority of PB-HRPWM, with the first peak at –10.78 dBV and the second at –12.04 dBV for \( m = 0.6 \). Power balance experiments, illustrated by output voltage, current, and power waveforms for AL1, AL2, and AL3, show nearly identical average powers (e.g., 35.56 W each at \( m = 0.6 \)), validating the power balancing feature.
| Method | m | THD (%) | 1st Noise Peak (dBV) | 2nd Noise Peak (dBV) |
|---|---|---|---|---|
| PC-RPWM | 0.3 | 1.978 | -8.45 | -9.15 |
| 0.6 | 1.212 | -9.05 | -10.45 | |
| 0.9 | 0.804 | -8.75 | -10.75 | |
| PS-RPWM | 0.3 | 1.989 | -8.55 | -9.25 |
| 0.6 | 1.211 | -8.95 | -10.35 | |
| 0.9 | 0.806 | -8.65 | -10.65 | |
| PS-HPWM | 0.3 | 0.298 | -5.15 | -6.05 |
| 0.6 | 0.156 | -5.45 | -6.45 | |
| 0.9 | 0.110 | -5.75 | -6.75 | |
| POD-HPWM | 0.3 | 0.314 | -5.35 | -6.25 |
| 0.6 | 0.167 | -5.55 | -6.55 | |
| 0.9 | 0.108 | -5.85 | -6.85 | |
| PB-HRPWM | 0.3 | 0.181 | -10.06 | -10.58 |
| 0.6 | 0.094 | -10.78 | -12.04 | |
| 0.9 | 0.067 | -11.15 | -11.98 |
In conclusion, the proposed PB-HRPWM method effectively addresses the challenges of PWM noise and power imbalance in asymmetric CHB three-phase inverters. By integrating step-wave modulation, IPD carrier stacking, random frequency modulation, and pulse-based power balancing, it achieves lower line voltage THD, reduced PWM noise peaks, and equitable power distribution among low-voltage H-bridge units. The method’s digital implementation is simplified by decoupling power balancing from complex carrier reconstruction, making it suitable for real-time control in high-performance systems. Simulations and experiments consistently demonstrate its superiority over conventional PWM techniques, highlighting its potential for applications in electric vehicles, industrial drives, and renewable energy systems. Future work could explore extensions to other multilevel topologies and optimization of random algorithms for enhanced performance.