In recent years, the rapid development of distributed photovoltaic systems, particularly in residential rooftop applications, has highlighted the importance of efficient and cost-effective grid-connected inverters. As a key component in these systems, solar inverters must balance performance, size, and reliability. Non-isolated topologies for solar inverters have gained significant attention due to their advantages of low cost, compact size, and high efficiency. However, the absence of galvanic isolation in such solar inverters introduces challenges, including leakage currents and DC injection into the grid, which can compromise safety and power quality. This article presents a novel non-isolated single-phase half-bridge solar inverter based on an active neutral-point clamped (ANPC) three-level topology, designed to inherently suppress leakage currents and eliminate DC components without additional circuitry. Through detailed analysis and simulation, we demonstrate the effectiveness of this approach for modern solar inverters in low-power distributed systems.
The growing adoption of solar energy has driven innovation in power electronics, with solar inverters playing a pivotal role in converting DC power from photovoltaic panels to AC power for grid integration. Traditional non-isolated solar inverters, such as full-bridge configurations, are widely used but suffer from inherent issues like DC offset and common-mode currents. These problems arise due to switching dead times and parasitic capacitances, leading to potential safety hazards and grid instability. In contrast, half-bridge topologies offer a natural solution for DC component suppression, as the output current always passes through a DC-blocking capacitor. However, in single-phase systems, half-bridge solar inverters face voltage imbalance across the DC-link capacitors, which can induce common-mode currents. Our work addresses this by proposing a modified ANPC three-level half-bridge solar inverter that integrates auxiliary circuits for capacitor voltage balancing, thereby mitigating both leakage currents and DC injection. This advancement contributes to the development of safer and more reliable solar inverters for residential applications.
To understand the core issues, we first analyze the DC component and common-mode current in solar inverters. In a typical single-phase full-bridge solar inverter, as shown in Figure 1, the switching dead time during transitions between switch pairs (e.g., S1-S4 to S2-S3) causes current to flow through body diodes, generating a DC offset. This DC component can distort grid voltage, increase transformer saturation risks, and violate grid codes. The average output voltage over a switching period can be expressed as:
$$ V_{dc,offset} = \frac{1}{T_s} \int_0^{T_s} (V_{an} – V_{bn}) \, dt $$
where \( V_{an} \) and \( V_{bn} \) are the phase voltages, and \( T_s \) is the switching period. If not suppressed, this offset accumulates, leading to significant DC injection. In contrast, half-bridge solar inverters, as depicted in Figure 2, inherently block DC components because the output is connected to the midpoint of two series DC-link capacitors. The output voltage \( V_{out} \) is given by:
$$ V_{out} = V_{C1} – V_{C2} $$
where \( V_{C1} \) and \( V_{C2} \) are the voltages across capacitors C1 and C2. Since the capacitors block DC, the average output voltage remains zero, eliminating DC injection. However, in single-phase operation, the capacitors experience uneven charging and discharging due to the pulsating load current, causing voltage imbalance. This imbalance affects common-mode behavior. The common-mode voltage \( V_{cm} \) and differential-mode voltage \( V_{dm} \) are defined as:
$$ V_{cm} = \frac{V_{1N} + V_{2N}}{2} $$
$$ V_{dm} = V_{1N} – V_{2N} = V_{12} $$
where \( V_{1N} \) and \( V_{2N} \) are voltages at nodes 1 and 2 relative to the neutral point N. The total common-mode voltage \( V_{tcm} \) is:
$$ V_{tcm} = V_{cm} + V_{dm} $$
For a half-bridge solar inverter, if the capacitor voltages are balanced (\( V_{C1} = V_{C2} = V_{dc}/2 \)), then \( V_{tcm} \) remains constant, resulting in zero common-mode current. But in practice, imbalance occurs, leading to varying \( V_{cm} \) and leakage currents through parasitic capacitances. Table 1 summarizes the comparison between full-bridge and half-bridge solar inverters regarding DC and common-mode issues.
| Topology | DC Component | Common-Mode Current | Complexity |
|---|---|---|---|
| Full-Bridge Solar Inverter | High (due to dead time) | Moderate (requires suppression techniques) | Moderate |
| Half-Bridge Solar Inverter | Low (inherent blocking) | High (if capacitors unbalanced) | Low |
| Proposed ANPC Solar Inverter | None (inherent blocking) | None (with voltage balancing) | Moderate |
To address these challenges, we propose a novel ANPC three-level half-bridge solar inverter. This topology builds on the traditional ANPC structure by adding two auxiliary capacitors and four diodes to ensure voltage balance across the DC-link capacitors. The circuit diagram is shown below, illustrating how the auxiliary components integrate into the power stage. This design not only suppresses leakage currents but also eliminates DC injection, making it ideal for modern solar inverters in grid-tied applications.
The proposed solar inverter consists of six switches (S1 to S6) with anti-parallel diodes, two DC-link capacitors (C1 and C2), two auxiliary capacitors (Cb1 and Cb2), and four auxiliary diodes (VDa to VDd). The key innovation lies in the decoupled control of the main and auxiliary circuits. The main circuit, formed by the upper and lower arms, handles power conversion, while the auxiliary circuit manages capacitor voltage balancing. This separation simplifies control and enhances reliability. The switching strategy involves high-frequency operation for S1, S2, S4, and S5, with complementary gate signals, as shown in Figure 5. The duty cycles are adjusted to regulate output current while maintaining capacitor balance.
We now delve into the working principles of this solar inverter. The operation is divided into two modes based on the direction of grid current: current flowing out of the inverter (positive half-cycle) and current flowing into the inverter (negative half-cycle). For brevity, we focus on the positive half-cycle, where the upper arm acts as the main circuit and the lower arm as the auxiliary circuit. The modes are as follows:
Mode 1: Switches S1 and S3 are on, connecting the positive terminal of C1 to the grid via the filter inductor. The output voltage \( V_{out} \) is positive, and C1 discharges to supply power. The voltage across C1 decreases, while C2 remains idle. To compensate, the auxiliary circuit activates: when S2 is on during freewheeling, diode VDd conducts, allowing Cb2 to charge C2 through the path Cb2 → S2 → C2 → VDd. This raises \( V_{C2} \) and lowers \( V_{Cb2} \). Conversely, when S1 is on, diode VDc conducts, enabling the DC source to recharge Cb2 via VDC → VDc → Cb2 → S1, restoring \( V_{Cb2} \). The equations for capacitor dynamics are:
$$ \frac{dV_{C1}}{dt} = -\frac{i_{grid}}{C1}, \quad \frac{dV_{C2}}{dt} = \frac{i_{charge}}{C2} $$
$$ i_{charge} = \frac{V_{Cb2} – V_{C2}}{R_{path}} $$
where \( i_{grid} \) is the grid current, and \( R_{path} \) represents the resistance in the charging path. Similarly, if \( V_{C2} \) exceeds the nominal value, switches S4 and S5 alternate to discharge C2 into Cb1 and then into the DC source, balancing voltages. This cyclic process ensures that \( V_{C1} \) and \( V_{C2} \) remain equal, minimizing common-mode voltage variations. The common-mode voltage for this solar inverter can be derived as:
$$ V_{cm} = \frac{V_{C1} + V_{C2}}{2} + \frac{V_{aux}}{2} $$
where \( V_{aux} \) is the auxiliary circuit contribution. With balanced capacitors, \( V_{cm} \) is constant, leading to zero leakage current. Moreover, the DC component is inherently blocked by the series capacitors, as proven by integrating the output voltage over a cycle:
$$ \int_0^{T} V_{out} \, dt = \int_0^{T} (V_{C1} – V_{C2}) \, dt = 0 $$
assuming \( V_{C1} = V_{C2} \) on average. This makes the proposed solar inverter highly effective for grid integration.
To validate the performance, we conducted simulation studies using parameters typical for residential solar inverters. The setup includes a DC input voltage of 800 V, DC-link capacitors C1 = C2 = 100 nF, auxiliary capacitors Cb1 = Cb2 = 100 μF, filter inductance L = 1 mH, and switching frequency f = 20 kHz. The duty cycles for S1 and S4 are set at 20%, and for S2 and S5 at 80%, with initial capacitor voltages at 400 V each. The simulations compare the proposed solar inverter with a conventional half-bridge solar inverter lacking voltage balancing. Key results are summarized in Table 2, highlighting improvements in voltage balance and common-mode suppression.
| Parameter | Conventional Half-Bridge Solar Inverter | Proposed ANPC Solar Inverter |
|---|---|---|
| DC-Link Capacitor Voltage Imbalance | High (±20 V variation) | Low (±2 V variation) |
| Common-Mode Current RMS | 0.5 A | 0.01 A |
| DC Injection into Grid | 0.1% of rated current | Negligible (<0.01%) |
| Switching Losses | High (due to voltage stress) | Low (balanced stress) |
| Efficiency | 94% | 97% |
The simulation waveforms demonstrate that without balancing, capacitor voltages diverge significantly during the grid cycle, as shown in Figure 7a, where \( V_{C1} \) drops and \( V_{C2} \) rises. In contrast, with the auxiliary circuit, both voltages stabilize around 400 V, as in Figure 7b. This balance ensures a constant common-mode voltage, calculated as:
$$ V_{cm} = \frac{400 + 400}{2} = 400 \, \text{V} $$
leading to minimal leakage current. Additionally, the auxiliary capacitor voltages, \( V_{Cb1} \) and \( V_{Cb2} \), remain steady at approximately 400 V, as depicted in Figure 8, confirming effective charge replenishment. The output current waveform is sinusoidal with low total harmonic distortion (THD below 3%), meeting grid standards for solar inverters. These results affirm that the proposed solar inverter topology successfully mitigates both leakage currents and DC components, enhancing safety and performance.
Further analysis explores the advantages of this solar inverter over existing topologies. The ANPC structure reduces voltage stress on switches to half of the DC-link voltage, allowing for lower-rated devices and cost savings. For instance, the voltage across each switch is:
$$ V_{sw} = \frac{V_{dc}}{2} = 400 \, \text{V} $$
compared to full-bridge solar inverters where switches withstand the full \( V_{dc} \). This also lowers conduction losses, as expressed by:
$$ P_{cond} = I_{rms}^2 \cdot R_{ds(on)} $$
where \( I_{rms} \) is the RMS current and \( R_{ds(on)} \) is the on-state resistance. The balanced switching loss distribution among devices improves thermal management, extending the lifespan of solar inverters. Moreover, the decoupled control strategy simplifies implementation, as the auxiliary circuit operates independently based on capacitor voltage feedback. This contrasts with complex modulation schemes required in other non-isolated solar inverters, such as HERIC or H5 topologies. Table 3 provides a comparative overview of key solar inverter topologies.
| Topology | Leakage Current Suppression | DC Component Suppression | Switch Count | Control Complexity |
|---|---|---|---|---|
| Full-Bridge Solar Inverter | Requires extra filters | Poor (needs sensing) | 4 | High |
| HERIC Solar Inverter | Good (with AC bypass) | Moderate | 6 | Moderate |
| H5 Solar Inverter | Good (with DC decoupling) | Moderate | 5 | Moderate |
| Proposed ANPC Solar Inverter | Excellent (inherent) | Excellent (inherent) | 6 | Low (decoupled) |
The proposed solar inverter also aligns with grid code requirements, such as IEEE 1547 and IEC 62109, which limit DC injection to less than 0.5% of rated current. By design, our solar inverter achieves near-zero DC output, making it compliant without additional hardware. Furthermore, the topology’s scalability allows for adaptation to higher power levels, relevant for commercial solar inverters. Future work could integrate maximum power point tracking (MPPT) algorithms and reactive power control, expanding the functionality of solar inverters in smart grids.
In conclusion, this article presents a novel single-phase half-bridge solar inverter based on an ANPC three-level topology, effectively suppressing leakage currents and eliminating DC injection. The integration of auxiliary capacitors and diodes ensures voltage balance across DC-link capacitors, addressing a key limitation of traditional half-bridge solar inverters. Simulation results validate the design, showing stable capacitor voltages, minimal common-mode currents, and high efficiency. Compared to existing solar inverters, this topology offers lower switch stress, simplified control, and inherent safety features, making it a promising solution for residential and low-power distributed photovoltaic systems. As solar energy adoption grows, advancements in solar inverter technology like this will play a crucial role in enhancing grid stability and system reliability. We recommend further experimental validation and optimization for widespread deployment of such solar inverters in real-world applications.