I focus my research on non-isolated single-phase common-ground solar inverters for photovoltaic grid-connected systems. As renewable energy continues to expand, solar inverters have become central to converting direct-current photovoltaic energy into alternating-current power suitable for the grid. In my view, the most important design conflict in modern solar inverters is the tension between high efficiency, low cost, compact volume, and safety. Transformerless solar inverters remove the isolation transformer, so they offer smaller size, higher integration, lower cost, and higher conversion efficiency. However, because there is no galvanic isolation between the photovoltaic array and the grid, the common-mode leakage current becomes a critical problem. This leakage current can cause electromagnetic interference, output current distortion, overheating, and safety risks for operators and equipment. My work therefore concentrates on common-ground solar inverters, where the negative terminal of the photovoltaic array is directly connected to the neutral point of the grid. In such solar inverters, the common-mode voltage is theoretically clamped to zero, so the leakage current path through the photovoltaic parasitic capacitance is strongly suppressed.
I begin with the physical origin of leakage current in solar inverters. A photovoltaic module is not only a source of electrical energy; it also has a structural capacitance to the ground because of its glass, frame, mounting structure, and surrounding environment. This parasitic capacitance is usually in the range of tens to hundreds of nanofarads per kilowatt, and it can increase significantly under humid or dusty conditions. When the solar inverters switch at high frequency, the common-mode voltage across this capacitance changes rapidly, and a common-mode current is generated. If the photovoltaic negative terminal is not tied to the grid neutral, this current can circulate through the parasitic capacitance, the photovoltaic array, the solar inverters, and the grid. The result is leakage current, which is one of the most important constraints in transformerless solar inverters.
To analyze this behavior quantitatively, I use the common-mode equivalent circuit. Let the voltage from the active terminals to the negative bus be represented by two terminal voltages. The common-mode voltage and differential-mode voltage are defined as follows:
$$ U_{cm}=\frac{U_{AN}+U_{BN}}{2} $$
$$ U_{dm}=U_{AN}-U_{BN} $$
By rearranging these expressions, I obtain the terminal voltages in terms of common-mode and differential-mode quantities:
$$ U_{AN}=U_{cm}+\frac{U_{dm}}{2} $$
$$ U_{BN}=U_{cm}-\frac{U_{dm}}{2} $$
When the filter inductors are not perfectly symmetric, the effective common-mode voltage seen by the parasitic capacitance is not simply the average of the two terminal voltages. A more complete expression can be written as:
$$ U_{ccm}=\frac{U_{AN}+U_{BN}}{2}+\frac{(U_{AN}-U_{BN})(L_2-L_1)}{2(L_1+L_2)} $$
The leakage current through the photovoltaic parasitic capacitance is then determined by the time derivative of this effective common-mode voltage:
$$ i_{cm}=C_{pv}\frac{dU_{ccm}}{dt} $$
This equation is the foundation of my leakage-current analysis. If the parasitic capacitance cannot be removed, then the only practical way to reduce leakage current is to keep the effective common-mode voltage constant or, even better, force it to zero. For symmetric filter inductors, the expression simplifies to:
$$ U_{ccm}=\frac{U_{AN}+U_{BN}}{2} $$
In common-ground solar inverters, the negative terminal of the photovoltaic array is directly connected to the grid neutral point. Therefore, one terminal voltage is zero, and the effective common-mode voltage becomes zero. This is the fundamental reason why common-ground solar inverters have an inherent advantage in leakage-current suppression. I summarize the leakage-current limits that guide my design in the following table.
| Leakage current detection value | Required action time |
|---|---|
| 30 mA | 0.3 s |
| 60 mA | 0.15 s |
| 100 mA | 0.04 s |
I classify existing non-isolated solar inverters into three broad families: full-bridge topologies, half-bridge topologies, and common-ground topologies. Each family has a different method for handling leakage current. Full-bridge solar inverters are widely used because of their symmetric structure and high DC voltage utilization. However, a basic full-bridge solar inverter under unipolar modulation generates a high-frequency common-mode voltage that varies among several levels. Under bipolar modulation, the common-mode voltage can remain at half of the DC-link voltage, but the output voltage has only two levels, so the harmonic content is high and the filter becomes large. Many improved full-bridge solar inverters, such as AC-decoupling and DC-decoupling structures, add auxiliary switches or clamping branches to hold the common-mode voltage constant during freewheeling. These solar inverters reduce leakage current, but they do not eliminate it completely because parasitic switch capacitances and bus voltage fluctuations still disturb the common-mode voltage.
For a basic full-bridge solar inverter under unipolar modulation, I can summarize the common-mode voltage in the main modes. During the positive active mode, the common-mode voltage is:
$$ U_{ccm}=0.5U_{dc} $$
During the positive freewheeling mode, it becomes:
$$ U_{ccm}=U_{dc} $$
During the negative active mode, it returns to:
$$ U_{ccm}=0.5U_{dc} $$
During the negative freewheeling mode, it becomes:
$$ U_{ccm}=0 $$
These transitions create a high-frequency common-mode voltage and therefore a high-frequency leakage current. Under bipolar modulation, the common-mode voltage remains:
$$ U_{ccm}=0.5U_{dc} $$
This condition is better for leakage current, but the output waveform has only two levels, which increases total harmonic distortion and filter size. In my assessment, full-bridge solar inverters can suppress leakage current only through careful clamping and modulation, but they cannot provide the same theoretical guarantee as common-ground solar inverters.
Half-bridge solar inverters have a different advantage. Because the grid neutral is connected to the midpoint of the DC bus, the common-mode voltage is naturally fixed. For a conventional half-bridge solar inverter, the common-mode voltage is:
$$ U_{ccm}=U_{dc}/2 $$
This value is constant, so the leakage current is inherently low. However, half-bridge solar inverters have a low voltage gain, and the output voltage is limited by the DC-link voltage. Improved NPC and T-type half-bridge solar inverters can produce three levels and reduce switching stress, but they still require a relatively high DC input and do not provide wide-range voltage regulation. Therefore, half-bridge solar inverters are attractive for medium and high DC voltage systems, but they are less suitable for low-voltage distributed photovoltaic systems where wide input voltage variation and boost capability are needed.
The comparison of the three families can be summarized as follows.
| Topology family | Leakage current behavior | Voltage gain | Output levels | Typical limitation |
|---|---|---|---|---|
| Full-bridge solar inverters | Depends on modulation and clamping | Usually no boost | Two or three | High-frequency common-mode voltage |
| Half-bridge solar inverters | Naturally constant common-mode voltage | No boost | Two or three | Low gain and high DC input requirement |
| Common-ground solar inverters | Theoretically zero leakage current | Can be designed with boost or buck-boost | Three or more | Requires careful capacitor and switch design |
Because of this comparison, I chose common-ground solar inverters as the foundation of my research. I designed two different common-ground solar inverters for different application requirements. The first is a three-level common-ground solar inverter with buck-boost capability. The second is a five-level common-ground solar inverter with a switched-capacitor network. Both solar inverters connect the photovoltaic negative terminal directly to the grid neutral point, so the common-mode voltage is zero in theory. I also developed control strategies to handle wide input voltage variation, capacitor voltage balancing, and harmonic suppression.
My first proposed solar inverter is a three-level common-ground photovoltaic inverter with buck-boost capability. The main motivation is that photovoltaic arrays have a wide output voltage range because of temperature, irradiance, and partial shading. A solar inverter must therefore be able to step up or step down the voltage to meet the grid requirement and to support maximum power point tracking. I introduced a switching-boost-buck module composed of one inductor and one capacitor. This module allows the solar inverter to operate in both buck and boost modes, depending on the photovoltaic input voltage. The common-ground structure ensures that the photovoltaic negative terminal and the grid neutral point are directly connected, which eliminates the common-mode leakage current path. The topology is compact, symmetric, and simple to control. The inductor also provides soft charging for the capacitor, which reduces current stress on the capacitor and switches.
The operating modes of my three-level common-ground solar inverter can be described in six intervals. During the positive half cycle, the first mode charges the input inductor while the capacitor discharges to the grid through the output inductor. The second mode transfers the input inductor energy to the capacitor while the output inductor continues to supply the grid. The third mode is a freewheeling interval. The negative half cycle is symmetric. I summarize the mode behavior in the following table.
| Mode | Active devices | Main energy transfer | Output behavior |
|---|---|---|---|
| Mode I | Input switch, output switch | PV charges input inductor, capacitor feeds grid | Positive output |
| Mode II | Boost switch, diode, output switch | Input inductor charges capacitor, output inductor feeds grid | Positive output |
| Mode III | Boost switch, output switch | Output inductor freewheels | Positive freewheeling |
| Mode IV | Input switch, lower output switch | PV charges input inductor, capacitor feeds grid | Negative output |
| Mode V | Boost switch, diode, lower output switch | Input inductor charges capacitor, output inductor feeds grid | Negative output |
| Mode VI | Boost switch, lower output switch | Output inductor freewheels | Negative freewheeling |
The input inductor current in discontinuous conduction mode is described by the following equations. During the charging interval, I have:
$$ i_{L1}(t)=\frac{v_{in}}{L_1}(t-t_0) $$
During the discharging interval, the current decreases as:
$$ i_{L1}(t)=\frac{-V_{Cin}}{L_1}(t-t_1) $$
At the end of the discharge interval, the current reaches zero:
$$ i_{L1}(t)=0 $$
The current ripple of the input inductor is approximately:
$$ \Delta i_{L1}=\frac{d_1 v_{in}}{L_1 f_s} $$
For a given output equivalent resistance and duty cycle, the critical inductance can be selected as:
$$ L_1=\frac{R(1-d_1)^2}{2f_s} $$
The output inductor current ripple is determined by the capacitor voltage and the output-side duty cycle:
$$ \Delta i_{L2}=\frac{d_2 V_{Cin}}{L_2 f_s} $$
The capacitor voltage ripple in my design is an important consideration because the intermediate capacitor is not infinite. I use the following expression to estimate it:
$$ \Delta V_{Cin}(t)=\frac{d(t)i_g(t)}{C_{in}f_s} $$
The duty cycle varies with the grid voltage and the input voltage:
$$ d(t)=\frac{|v_g(t)|}{|v_g(t)|+v_{in}} $$
Combining these expressions gives the capacitor ripple as:
$$ \Delta V_{Cin}(t)=\frac{|v_g(t)|}{|v_g(t)|+v_{in}}\frac{|i_g(t)|}{C_{in}f_s} $$
This equation shows that the capacitor ripple is inversely proportional to capacitance and switching frequency. In my design, I limited the maximum voltage ripple to about five percent. The control unit uses a proportional-resonant controller because the grid current reference is sinusoidal. The transfer function is:
$$ G_{PR}(s)=K_P+\frac{K_R s}{s^2+\omega^2} $$
I selected the proportional gain and resonant gain according to the desired dynamic response and steady-state accuracy. The modulation circuit compares the sinusoidal reference with a triangular carrier and generates the gate signals for the buck-boost module and the output switches. The control logic is simple, and the common-ground connection keeps the common-mode voltage at zero.
I also performed a detailed loss analysis for this three-level common-ground solar inverter. The conduction loss of a semiconductor device is determined by its on-state resistance:
$$ V_{ds}(t)=i_{ds}(t)R_{ds} $$
The duty cycles of the input-side and output-side switches are approximately:
$$ d_{Sin1,2,3}(t)=m|\sin(\omega t)|, \quad d_{S1}(t)=1-m|\sin(\omega t)| $$
Using these duty cycles, the conduction losses of the main switches can be estimated as follows:
$$ P_{S2,3}=P_{Sin1}=\frac{2I_m^2R_{ds}}{3\pi} $$
$$ P_{S1}=\frac{(3\pi-2)I_m^2R_{ds}}{12\pi} $$
$$ P_{S1′}=P_{S4}=\frac{I_m^2R_{ds}}{2} $$
$$ P_{D1}=\frac{(3\pi-2)I_m^2R_D}{6\pi} $$
The total semiconductor conduction loss is:
$$ P_{S-con}=4P_{S2,3}+P_{S1}+P_{S1′}+P_{D1} $$
For the inductors, the conduction loss includes a DC component and an AC ripple component:
$$ P_{ON[L]}=I_{L-dc}^2R_{L-dc}+\frac{I_m^2}{2}R_{L-ac} $$
The switching loss is approximated by the overlap of voltage and current during turn-on and turn-off:
$$ P_{S[S]}=f_s I_D V_{ds}(t_r+t_f) $$
The magnetic core loss is related to the flux density swing and the switching frequency:
$$ \Delta B=\frac{\mu_L N_L I_L}{l_{gap}} $$
$$ P_{IND}=a\Delta B^b f^c $$
Finally, the capacitor loss is determined by the equivalent series resistance:
$$ P_C=\frac{1}{T}\int_0^T i_C^2(t)dt \cdot ESR $$
I then built a simulation model of the three-level common-ground solar inverter. The key simulation parameters are listed in the following table.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Output power | 300 W | Output inductor | 2 mH |
| Switching frequency | 20 kHz | Input capacitor | 220 microfarad |
| Line frequency | 50 Hz | Output capacitor | 1.5 microfarad |
| Input inductor | 100 microhenry | Load resistance | 100 ohm |
The simulation results show that the input inductor operates in discontinuous conduction mode, and its current has a symmetric envelope in the positive and negative half cycles. The capacitor voltage ripple remains within a few volts, which confirms the soft-charging behavior of the intermediate capacitor. The output voltage and current are sinusoidal and well balanced. The total harmonic distortion of the output voltage is about 1.39 percent. I also tested a load step from 100 ohm to 130 ohm. The output current adjusted quickly and entered a new steady state without oscillation. When the input voltage stepped from 75 V to 100 V, the output current again recovered quickly. These results confirm that the control strategy has good robustness.
My second proposed solar inverter is a five-level common-ground photovoltaic inverter with a switched-capacitor network. I designed this topology to improve output power quality while keeping the common-ground advantage. The topology combines a boost stage with a switched-capacitor network. The boost stage raises the photovoltaic voltage to the required grid gain range. The switched-capacitor network contains two capacitors and several switches. By changing the series and parallel connection of the two capacitors, the solar inverter generates five output levels. This reduces the harmonic content of the output voltage and decreases the size of the output filter. The topology also has a self-balancing capability for the two capacitors. The negative terminal of the photovoltaic array is directly connected to the grid neutral point, so the common-mode voltage is zero in theory, and the leakage current is essentially eliminated.
The five-level common-ground solar inverter has six main modes. The switch states and the ideal output voltage are summarized in the following table.
| Mode | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | Output voltage |
|---|---|---|---|---|---|---|---|---|---|
| M1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | V_Cin |
| M2 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | V_Cin/2 |
| M3 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| M4 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| M5 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | -V_Cin/2 |
| M6 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | -V_Cin |
In an ideal analysis, the output voltage levels are:
$$ v_g \in \left\{-V_{Cin}, -\frac{V_{Cin}}{2}, 0, \frac{V_{Cin}}{2}, V_{Cin}\right\} $$
In a practical circuit, the device voltage drops modify these levels slightly. For example, in the first mode, when the output current is positive, the output voltage is approximately:
$$ v_g = V_{Cin} – V_{ON-S} $$
When the output current is negative, the freewheeling path changes, and the output voltage becomes:
$$ v_g = V_{Cin} + 2V_{ON-VD} $$
Similar corrections apply to the other modes. The important point is that the two capacitors C1 and C2 are driven so that their voltages remain balanced. The switches that connect the capacitors in parallel and in series are controlled in a complementary manner. Therefore, the capacitor voltages tend to be equal, and the output levels remain symmetrical. This self-balancing property reduces the need for complex external balancing circuits.
For this five-level common-ground solar inverter, I developed a feedforward space vector modulation strategy. Conventional space vector modulation assumes that the capacitor voltages are exactly equal to half of the DC-link voltage. In reality, the capacitor voltages fluctuate, and this fluctuation can distort the output voltage if it is not compensated. My modulation strategy has two objectives. First, it provides a five-level stepped output voltage. Second, it decouples the output voltage from the fluctuating capacitor voltage. The reference voltage is defined as:
$$ v_{g-ref}(t)=d(t)V_{Cin} $$
The duty cycle is sinusoidal:
$$ d(t)=A_m\sin(\omega t) $$
For two adjacent space vectors, the duty cycles can be calculated from the reference voltage and the vector voltages:
$$ \begin{bmatrix} d_M(t) \\ d_N(t) \end{bmatrix} = \begin{bmatrix} V_M & V_N \\ 1 & 1 \end{bmatrix}^{-1} \begin{bmatrix} v_{g-ref}(t) \\ 1 \end{bmatrix} $$
For example, when the reference voltage is in the highest region, the duty cycles of the first and second modes are obtained from:
$$ \begin{bmatrix} d_1(t) \\ d_2(t) \end{bmatrix} = \begin{bmatrix} V_{Cin} & V_{Cin}/2 \\ 1 & 1 \end{bmatrix}^{-1} \begin{bmatrix} v_{g-ref}(t) \\ 1 \end{bmatrix} $$
From this calculation, the duty cycles of the individual switches can be expressed in terms of the capacitor voltage and the DC-link voltage. The following table summarizes the duty cycles in different operating regions.
| Region | d_S1 | d_S2 | d_S4 |
|---|---|---|---|
| R1 | 1 | 0 | (V_C(d(t)+? ))/V_Cin |
| R2a | 1 | 1 | V_C(d(t)+1)/V_Cin |
| R2b | (V_Cin – V_C + V_C d(t))/(V_Cin – V_C) | 0 | (V_Cin – V_C + V_C d(t))/(V_Cin – V_C) |
| R3a | 1 | 1 | V_Cin(d(t)-1)/(2V_C) |
| R3b | V_Cin(d(t)+1)/(V_Cin – V_C) | 1 | V_Cin(d(t)+1)/(V_Cin – V_C) |
| R4 | V_C(d(t)-1)/V_Cin + 1 | 1 | V_C(d(t)-1)/V_Cin + 1 |
I note that the exact duty-cycle expressions depend on the selected redundant vector and the measured capacitor voltage. The key idea is that the modulation law continuously senses the capacitor voltage and adjusts the duty cycle so that the output voltage remains a clean five-level waveform. The region selection is based on the reference voltage and the measured capacitor voltage. When the reference voltage is in the positive high region, the controller selects the appropriate vector pair. When the reference voltage is near zero, it selects the freewheeling vectors. The output current sign is also used to choose the redundant vector that minimizes harmonic distortion and switching loss. This feedforward space vector modulation allows the solar inverter to maintain good output quality even when the capacitor voltages are not perfectly constant.
I also derived the voltage gain of the five-level common-ground solar inverter. Using volt-second balance on the input inductor and the energy balance between the input and output, the gain can be approximated as:
$$ G=\frac{V_g}{V_{Cin}}=\frac{1+\sqrt{1+2A_m R/(L_1 f_s)}}{2} $$
This expression shows that the gain increases with the modulation coefficient and the load resistance. In my design, I limited the maximum gain to about six to keep a safe margin. The gain curve confirms that the solar inverter can boost a low photovoltaic voltage to the grid voltage range while maintaining a five-level output. The boost stage also helps the solar inverter track the maximum power point of the photovoltaic array. I used a maximum power point tracking controller to generate the input voltage reference. A phase-locked loop provides the grid phase, and a proportional-integral controller regulates the DC-link voltage. The current loop uses a proportional-resonant controller to track the sinusoidal grid current reference. The transfer functions are:
$$ G_{PI}(s)=K_p+\frac{K_i}{s} $$
$$ G_{PR}(s)=K_p+\frac{2K_R s}{s^2+\omega_g^2} $$
The control structure is straightforward. The maximum power point tracking block produces the input voltage reference. The PI controller compares this reference with the measured photovoltaic voltage and generates the output current amplitude. The phase-locked loop generates the phase reference. The current controller then produces the modulation signal, and the feedforward space vector modulation block generates the gate signals. Because the common-ground connection clamps the common-mode voltage to zero, no additional leakage-current controller is required.
I also analyzed the losses of the five-level common-ground solar inverter. The switching loss includes the overlap loss and the gate-drive loss:
$$ P_{S-S1,4-8}=f_s\left(\int i_d u_{ds}dt+\int i_d u_{ds}dt\right)+f_s Q_G U_{gate} $$
The conduction losses of the high-frequency switches and the line-frequency switches can be approximated as:
$$ P_{C-S1,4-8}=\frac{2I_m^2R_{ds}}{3\pi} $$
$$ P_{C-S2,3}=\frac{I_m^2R_{ds}}{4}-\frac{2I_m^2R_{ds}}{3\pi} $$
The total conduction loss is:
$$ P_{C-t}=6P_{C-S1,4-8}+2P_{C-S2,3} $$
The inductor conduction loss is:
$$ P_{C-L}=I_{L-dc}^2R_{L-dc}+0.5I_{f-ac}^2R_{L-ac} $$
I compared the proposed five-level common-ground solar inverter with several existing multilevel solar inverters. The comparison considers the number of switches, diodes, capacitors, DC sources, boost capability, common-mode current, and reactive power capability. The following table summarizes the comparison.
| Topology | Switches | Diodes | Capacitors | DC sources | Boost | Common-mode current | Reactive power |
|---|---|---|---|---|---|---|---|
| NPC | 8 | 20 | 4 | 1 | No | Low | No |
| H-bridge cascade | 7 | 12 | 0 | 2 | No | High | No |
| Diode-clamped | 8 | 14 | 7 | 2 | Yes | High | No |
| Flying capacitor | 8 | 1 | 3 | 1 | No | Low | No |
| Common-ground five-level | 8 | 1 | 3 | 1 | Yes | Zero | Yes |
The comparison shows that my proposed five-level common-ground solar inverter achieves a good balance between device count and functionality. It has one diode, three capacitors, and eight switches. It provides boost capability, zero common-mode current, and reactive power support. In contrast, some existing solar inverters require many more diodes or capacitors, and some cannot provide reactive power. This makes my proposed topology suitable for low-voltage distributed photovoltaic systems, where wide input voltage range and high output quality are important.
I validated the five-level common-ground solar inverter through simulation. The simulation parameters are listed below.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Output power | 300 W | Output inductor | 2 mH |
| Switching frequency | 20 kHz | Input capacitor | 220 microfarad |
| Line frequency | 50 Hz | Switched capacitors | 220 microfarad |
| Input inductor | 220 microhenry | Load resistance | 100 ohm |
The simulation waveforms show that the two switched capacitors have nearly equal voltages. Their voltage ripple is small and periodic, which confirms the self-balancing ability of the network. The unfiltered output voltage is a clean five-level stepped waveform. The output current is sinusoidal and symmetric. The total harmonic distortion of the output current is about 2.52 percent. I also calculated the efficiency under different output voltages and output powers. The efficiency remains above 96.1 percent over a wide output voltage range, and it is above 96.5 percent for output power between 650 W and 1.3 kW. These results indicate that the five-level common-ground solar inverter has both high power quality and high efficiency.
After the simulation studies, I built experimental prototypes for both solar inverters. The experimental platform includes a programmable DC power supply, the main inverter circuit, an LC filter, a digital signal processor, gate-drive circuits, and sampling circuits. For the three-level common-ground solar inverter, I built a 300 W prototype. The main experimental parameters are listed in the following table.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Output power | 300 W | Output inductor | 2 mH |
| Switching frequency | 20 kHz | Input capacitor | 220 microfarad |
| Line frequency | 50 Hz | Output capacitor | 1.5 microfarad |
| Input inductor | 100 microhenry | Load | 50 ohm, 30 mH |
The experimental results for the three-level common-ground solar inverter are consistent with my analysis. When the input voltage steps from 60 V to 100 V, the grid current responds quickly and remains stable. The proportional-resonant controller provides good tracking and disturbance rejection. I also tested a transition from full active power to full reactive power. Before the current reference change, the solar inverter injects about 300 W of active power. After the change, it injects about 150 VAR of reactive power. The current total harmonic distortion remains below 3.7 percent during the whole process. The input inductor current is symmetric in the positive and negative half cycles, and the drive signal of the input switch is a sinusoidal pulse-width modulation signal. When the load changes from 100 ohm to 150 ohm and back to 100 ohm, the output current peak changes according to the power balance and then settles in a short time. The leakage current is measured to be only about 4 mA under different loads. This value is far below the relevant grid-code limit for transformerless solar inverters. The efficiency of this prototype is above 94.2 percent over the tested power range, with a peak efficiency of about 97.9 percent.
For the five-level common-ground solar inverter, I built a 1 kW experimental prototype. The main experimental parameters are listed below.
| Parameter | Value | Parameter | Value |
|---|---|---|---|
| Input voltage | 60 to 100 V | Input inductor | 70 microhenry |
| Output voltage | 120 to 240 V AC | Filter inductor | 2 mH |
| Switching frequency | 20 kHz | Switches | TO-220 power MOSFETs |
| Line frequency | 50 Hz | Diodes | Fast recovery diodes |
| Capacitor C1 | 250 microfarad, 450 V | Capacitor C2 | 250 microfarad, 450 V |
The experimental results for the five-level common-ground solar inverter confirm the expected behavior. The input inductor current is symmetric in the positive and negative half cycles, and the main switch is driven by a sinusoidal pulse-width modulation signal. The two switched capacitors have almost identical voltages, with measured values around 100 V and 101.5 V. The unfiltered output voltage is a standard five-level stepped waveform with good symmetry and no visible distortion. I also compared the leakage current of my proposed solar inverter with two conventional transformerless solar inverters. The conventional full-bridge-based solar inverters show leakage current peaks of about 350 mA and 70 mA in simulation, while my proposed common-ground solar inverter keeps the common-mode voltage at zero and shows only a very small residual leakage current in both steady-state and dynamic tests. This is a direct consequence of the common-ground structure.
I also tested the dynamic performance of the five-level common-ground solar inverter. When the input voltage steps from 60 V to 100 V and back from 100 V to 60 V, the output current remains stable and sinusoidal. The total harmonic distortion of the output current is below 2.56 percent during the whole test. The solar inverter successfully performs both boost and inversion functions. I further tested reactive power injection. The prototype operates stably at a power factor of -0.9 and +0.9, which means it can provide reactive power support to the grid. The measured output current total harmonic distortion is about 1.89 percent, and the output voltage total harmonic distortion is about 2.52 percent. These values satisfy the relevant power-quality requirements. The peak efficiency of this prototype is about 97.4 percent.
From my research, I conclude that common-ground solar inverters are a strong solution for non-isolated single-phase photovoltaic grid-connected systems. By connecting the photovoltaic negative terminal directly to the grid neutral point, the common-mode voltage is theoretically forced to zero, and the leakage current path through the parasitic capacitance is eliminated. This is a fundamental advantage over full-bridge and half-bridge solar inverters, which can only reduce or clamp the common-mode voltage. My first proposed three-level common-ground solar inverter provides buck-boost capability, wide input voltage operation, symmetric operation, soft charging of the intermediate capacitor, and a simple control structure. My second proposed five-level common-ground solar inverter provides a switched-capacitor network, five-level output voltage, self-balancing capacitor voltages, reduced harmonic content, reduced filter size, and reactive power capability. Both solar inverters achieve high efficiency and low leakage current, and both are validated by simulation and experiment.
I also identify several directions for future improvement. For the three-level common-ground solar inverter, the intermediate capacitor voltage still has a small ripple because the capacitance cannot be infinite. Long-term operation may affect device lifetime. Future work can optimize the energy transfer control to reduce this ripple and further improve output power quality. For the five-level common-ground solar inverter, the number of active devices is relatively high. Future work can optimize device selection and thermal design to reduce losses and improve reliability. Both solar inverters use capacitors as intermediate energy-storage elements, so capacitor selection should consider reliability, high-temperature tolerance, humidity tolerance, and lifetime. Proper capacitor choice is essential for practical solar inverters. I believe that common-ground solar inverters will continue to play an important role in distributed photovoltaic systems, especially where high efficiency, low leakage current, and wide input voltage range are required.