In this thesis, I present a systematic study on a single-stage non-isolated five-level step-up photovoltaic inverter without leakage current. The proposed topology integrates a boost converter with a diode-clamped five-level inverter, achieving high voltage gain, continuous input current, low total harmonic distortion, and inherent common-mode voltage suppression. I analyze the operating principles, modulation strategies, steady-state characteristics, power losses, and grid-connected control methods. A novel constant-duty PWM modulation scheme is developed to ensure continuous conduction mode operation. I also design a maximum power point tracking direct power control strategy for grid-connected operation. Finally, I build a laboratory prototype based on a TMS320F28335 digital signal processor to validate the theoretical analysis. The experimental results confirm the effectiveness of the proposed inverter in terms of voltage gain, leakage current suppression, output waveform quality, and dynamic performance.
1. Introduction
With the rapid growth of global energy demand and the increasing environmental concerns, solar energy has become one of the most attractive renewable energy sources. Photovoltaic (PV) systems are widely deployed in residential, commercial, and utility-scale applications. Among the key components of a PV system, the inverter plays a crucial role in converting DC power from the PV panels into high-quality AC power for grid connection or local loads. In recent years, multilevel inverters have drawn considerable attention because they offer lower output harmonic distortion, reduced voltage stress on switching devices, and improved electromagnetic compatibility compared to conventional two-level inverters.
However, traditional non-isolated inverters suffer from two major drawbacks. First, the absence of galvanic isolation leads to high-frequency common-mode voltages between the PV array and the grid, which generate leakage currents through the parasitic capacitance of the PV panels. These leakage currents can cause safety hazards, grid current distortion, and additional power losses. Second, conventional full-bridge or half-bridge inverters are inherently buck-type converters; the peak AC output voltage cannot exceed the DC input voltage. Since the output voltage of a single PV panel is usually low, a front-end DC-DC boost converter is typically required, increasing the system size, cost, and control complexity.
To solve these problems, I propose a single-stage non-isolated five-level step-up photovoltaic inverter without leakage current. The proposed topology connects the negative terminal of the DC input source directly to the neutral point of the AC output, which short-circuits the parasitic capacitance and thus eliminates the leakage current path. In addition, the inverter combines a boost stage with a diode-clamped five-level output stage, achieving a high voltage gain in a single power conversion stage. The output voltage can be stepped up to a desired level without an extra DC-DC converter, making the system more compact and efficient.
The remainder of this thesis is organized as follows. In Section 2, I present the topology derivation and working principle of the proposed inverter. Section 3 introduces an improved modulation strategy to achieve continuous input current. Section 4 discusses the grid-connected control strategy with maximum power point tracking direct power control. Section 5 describes the hardware design and experimental verification. Finally, Section 6 concludes the thesis and outlines future work.
2. Topology and Operating Principle of the Proposed Inverter
2.1 Topology Derivation
The proposed single-stage non-isolated five-level step-up photovoltaic inverter is shown in the following schematic. The main circuit consists of one DC input source \( U_{in} \), one boost inductor \( L_{in} \), two diodes \( D_1, D_2 \), seven power switches \( S_1, S_2, S_3, S_4, S_5, S_6, S_7 \), two storage capacitors \( C_1, C_2 \), an LCL filter, and the grid/load. The inductor \( L_{in} \) together with \( S_1, S_2, S_3 \) forms a boost DC-DC converter that charges \( C_1 \) and \( C_2 \). The diode-clamped circuit composed of \( S_4, S_5, S_6, S_7, D_1, D_2 \) and the two capacitors provides a five-level output voltage \( u_{AB} \).
I derive this topology from the common-ground three-level boost inverter proposed in the literature. By replacing the storage capacitor and the right leg with a diode-clamped multilevel circuit and moving the neutral point of the diode-clamped part to the negative-terminal common ground, I obtain the proposed structure. The key advantage is that the negative pole of the PV source is directly connected to the neutral point of the AC side, which theoretically eliminates the common-mode leakage current.
2.2 SPWM Modulation and Operating Modes
Initially, I use the conventional sinusoidal pulse width modulation (SPWM) method. The modulation signals consist of a sinusoidal reference \( V_{ref} \) and two triangle carriers \( V_{tri1} \) and \( V_{tri2} \). The switching states of the seven power switches are summarized in Table 2.1.
| Mode | \( U_{AB} \) | \( S_1 \) | \( S_2 \) | \( S_3 \) | \( S_4 \) | \( S_5 \) | \( S_6 \) | \( S_7 \) |
|---|---|---|---|---|---|---|---|---|
| Positive half-cycle 1 | \( +U_{C1}+U_{C2} \) | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| Positive half-cycle 2,5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive half-cycle 3,6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive half-cycle 4 | \( +U_{C2} \) | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Negative half-cycle 7 | \( -U_{C1}-U_{C2} \) | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
| Negative half-cycle 8,11 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative half-cycle 9,12 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative half-cycle 10 | \( -U_{C1} \) | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
Under this modulation, the inverter operates in discontinuous conduction mode (DCM). Figure 2.5 in the original thesis illustrates the equivalent circuits for twelve operating modes. During mode 1, \( S_1,S_3,S_4,S_6 \) are on, the input source charges \( L_{in} \) through \( S_1 \), while \( C_1 \) and \( C_2 \) together supply the load through \( S_3,S_4,S_6 \), yielding \( u_{AB}=+U_{C1}+U_{C2} \). In mode 2, the inductor current decreases as the input source and \( L_{in} \) charge the capacitors through \( S_2,S_3 \), while the load is freewheeling through \( S_3,S_5,S_7 \), giving \( u_{AB}=0 \). Mode 4 produces \( u_{AB}=+U_{C2} \) when only \( C_2 \) discharges through \( S_3,S_4,D_1 \). The negative half-cycle modes are complementary.
2.3 Steady-State Analysis in DCM
When the converter operates in DCM, the inductor current increase during the on-time \( t_{on} \) is given by
$$
\Delta I_{s-DCM} = \frac{U_{in}}{L_{in}} t_{on}
$$
and the decrease during the off-time \( t_{off} \) is
$$
\Delta I_{x-DCM} = \frac{2U_{C1}-U_{in}}{L_{in}} t_{off}
$$
assuming \( U_{C1}=U_{C2} \). Equating these two quantities gives
$$
\frac{U_{in}}{2U_{C1}-U_{in}} = \frac{t_{off}}{t_{on}}
$$
Using the rule-sampling method, the duty cycle is expressed as \( t_{on} = m T_s |\sin(\omega t)| \), where \( m \) is the modulation index. The average input inductor current over a half-cycle is
$$
i_{Lin,av} = \frac{U_{in} m^2}{4 L_{in} f_s} \cdot \frac{1}{1-\frac{U_{in}}{U_{C1}}}
$$
Neglecting power losses, the voltage gain \( G = U_o/U_{in} \) in DCM can be derived as
$$
G = \frac{m}{1-\frac{U_{in}}{2U_{C1}}} = \frac{m}{1-\frac{U_{in}}{U_o}}
$$
More precisely, considering the output power \( P_o \) and the inductor parameters, I obtain
$$
G = \frac{m^2 U_{in}}{4 P_o L_{in} f_s} + m
$$
The voltage gain versus modulation index and output power is plotted in the thesis. It shows that \( G \) increases with \( m \) but decreases with \( P_o \).
2.4 Voltage and Current Stresses
The maximum voltage stresses of the power switches and diodes are:
$$
U_{S1,max}=U_{S2,max}=U_{S3,max}=U_{S5,max}=U_{S7,max}=U_{C1}+U_{C2}=2U_{C1}
$$
$$
U_{S4,max}=U_{S6,max}=U_{C1}
$$
$$
U_{D1,max}=U_{D2,max}=U_{C1}
$$
The current stresses are:
$$
I_{S1,max}=I_{Lin,max}=I_{in,max}
$$
$$
I_{S4,max}=I_{S5,max}=I_{S6,max}=I_{S7,max}=I_{om}
$$
$$
I_{S2,max}=I_{S3,max}=I_{Lin,max}
$$
$$
I_{D1,max}=I_{D2,max}=I_{om}
$$
where \( I_{om} \) is the amplitude of the output current.
2.5 Loss Analysis in DCM
I analyze the power losses in DCM considering switch conduction losses, switching losses, diode losses, and magnetic losses. For the \( N \)-th switching cycle, the switching loss of a MOSFET is approximated by
$$
P_{SW}(N) = f_s \left[ U_{ds}(N) I_{ds}(N) (t_{cr}+t_{vf}+t_{cf}+t_{vr}) \right] / 2
$$
where \( t_{cr}, t_{cf} \) are current rise/fall times and \( t_{vr}, t_{vf} \) are voltage rise/fall times. The conduction losses of the switches are expressed using the on-resistance \( R_{DS} \), for example, for \( S_1 \) in the positive half-cycle:
$$
P_{S1}^+(N) = I_{S1}^2(N) R_{DS} D^+(N)
$$
where \( D^+(N) = m \sin(2\pi f_o N T_s) \). Similarly, the body-diode losses and the two diodes \( D_1,D_2 \) are calculated. The magnetic losses consist of core loss and copper loss. The core loss is modeled by the Steinmetz equation:
$$
P_{core} = k f_s^{\eta} \hat{B}^{\lambda}
$$
with \( k=0.85,\eta=1.85,\lambda=3 \). The copper losses are
$$
P_{Cu-in} = I_{Lin}^2 R_{cu-in}, \quad P_{Cu-o}=I_o^2 R_{cu-o}
$$
Figure 2.8 in the original thesis shows the theoretical loss distribution at different power levels. The dominant losses are the switch switching losses and the inductor losses.
2.6 Common-Mode Leakage Current Analysis
For a non-isolated grid-connected PV system, the common-mode voltage is
$$
u_{cm} = \frac{1}{2}(u_{AN}+u_{BN}) + \frac{1}{2}u_g
$$
and the leakage current is
$$
i_{cm} = C_{pv} \frac{du_{cm}}{dt}
$$
In the proposed inverter, the negative terminal of the PV source is directly connected to the neutral point of the AC side. Therefore, the parasitic capacitance \( C_{pv} \) is short-circuited, and the common-mode voltage is constant. Consequently, no leakage current flows. This structural advantage makes the inverter highly suitable for transformerless PV systems.
3. Improved Modulation Strategy for Continuous Input Current
3.1 Constant-Duty PWM Modulation
The conventional SPWM modulation forces the input inductor to operate in DCM, resulting in a high peak current and increased input current ripple. To overcome this issue, I propose an improved modulation strategy called constant-duty PWM modulation. As shown in the modulation diagram, a constant DC reference \( V_{dc-ref} \) is added and compared with the carrier to generate the gate signal for \( S_1 \). The other switches maintain their original SPWM signals. Thus, \( S_1 \) operates with a fixed duty cycle \( D \), while the output stage is still modulated by a sinusoidal reference \( V_{ref} \).
Table 3.1 summarizes the switching states under this improved modulation.
| Mode | \( U_{AB} \) | \( S_1 \) | \( S_2 \) | \( S_3 \) | \( S_4 \) | \( S_5 \) | \( S_6 \) | \( S_7 \) |
|---|---|---|---|---|---|---|---|---|
| Positive 1 | \( +U_{C1}+U_{C2} \) | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| Positive 2,4,6,8 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive 3,7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Positive 5 | \( +U_{C2} \) | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Negative 9 | \( -U_{C1}-U_{C2} \) | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
| Negative 10,12,14,16 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative 11,15 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| Negative 13 | \( -U_{C1} \) | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
In this improved scheme, the input inductor current is always continuous. During the freewheeling intervals, \( S_1 \) remains on so that the input source continues to charge the inductor. This ensures that \( i_{Lin} \) never drops to zero, and the converter operates in continuous conduction mode (CCM).
3.2 CCM Operating Modes
There are sixteen operating modes in one switching cycle under the improved modulation. The main waveforms are shown in the original thesis. I analyzed all modes and found that the boost stage (input source \( U_{in} \), inductor \( L_{in} \), switches \( S_1,S_2,S_3 \), capacitors \( C_1,C_2 \)) operates like a conventional boost converter. In the high-frequency average sense, the capacitor voltages satisfy
$$
U_{C1} = U_{C2} = \frac{U_{in}}{1-D}
$$
where \( D \) is the duty cycle of \( S_1 \). The output voltage of the inverter is given by
$$
u_o = m (U_{C1}+U_{C2}) = m \cdot \frac{2U_{in}}{1-D}
$$
Therefore, the voltage gain in CCM is
$$
G = \frac{U_o}{U_{in}} = \frac{2m}{1-D}
$$
Here \( U_o \) is the peak output voltage. If we use the RMS value, the expression is adjusted accordingly. Figure 3.4 in the original thesis plots \( G \) as a function of \( m \) and \( D \).
3.3 Simulation Comparison between DCM and CCM
To verify the theoretical analysis, I built simulation models in MATLAB/Simulink. The simulation parameters are listed in Table 3.2.
| Parameter | DCM | CCM |
|---|---|---|
| Input voltage \( U_{in} \) (V) | 40–60 | 40–60 |
| Output voltage \( u_o \) (V RMS) | 110 | 110 |
| Output power \( P_o \) (W) | 600 | 600 |
| Switching frequency \( f_s \) (kHz) | 20 | 20 |
| Inductor \( L_{in} \) (mH) | 0.2 | 4 |
| Storage capacitors \( C_1,C_2 \) (μF) | 220 | 220 |
| Filter inductor \( L_o \) (mH) | 4 | 4 |
| Filter capacitor \( C_f \) (μF) | 5 | 5 |
The simulation results are shown in Figure 3.5. In DCM, the input current \( i_{Lin} \) is discontinuous with high spikes, and the capacitor voltage \( U_{C1} \) has a relatively large ripple. In CCM, the input current is smooth and continuous, and the capacitor voltage ripple is much smaller. The output voltage is 110 V AC in both modes. The THD of the output voltage is 0.68% in DCM and 0.51% in CCM, both meeting grid requirements.
3.4 Performance Comparison with Other Converters
I compare the proposed inverter with several similar inverter topologies reported in the literature. The comparison considers the number of active switches, diodes, passive components, voltage gain capability, input current continuity, leakage current level, and efficiency. The results are summarized in Table 3.3.
| Converter | Switches | Diodes | Inductors | Capacitors | Voltage Gain | Input Current | Leakage Current | Efficiency |
|---|---|---|---|---|---|---|---|---|
| Ref. [15] | 8 | 1 | 0 | 2 | >1 | Discontinuous | High | — |
| Ref. [49] | 7 | 2 | 0 | 0 | <1 | Discontinuous | High | — |
| Ref. [50] | 9 | 1 | 0 | 2 | >1 | Discontinuous | Low | 98% |
| Ref. [51] | 10 | 0 | 1 | 1 | >1 | Continuous | High | — |
| Ref. [52] | 9 | 2 | 1 | 3 | <1 | Continuous | High | 98% |
| Ref. [53] | 8 | 8 | 1 | 0 | >1 | Continuous | High | 93.2% |
| Ref. [54] | 9 | 1 | 1 | 2 | >1 | Discontinuous | High | 98.4% |
| Ref. [55] | 12 | 0 | 0 | 4 | <1 | Continuous | High | 99.1% |
| Ref. [56] | 12 | 0 | 0 | 3 | <1 | Continuous | High | — |
| Proposed | 7 | 2 | 1 | 2 | >1 | Continuous | Low | 95.5% |
It is clear that the proposed inverter uses fewer active switches (only 7) and has a continuous input current, voltage-boosting capability, and very low leakage current. This makes it a competitive candidate for single-phase transformerless PV applications.
4. Grid-Connected Control with Maximum Power Point Tracking Direct Power Control
4.1 Control Strategies for Grid-Connected Inverters
I first studied several common control methods for single-phase grid-connected solar inverters. The single current-loop control compares the grid current with a reference current generated by an external source. However, this method does not ensure phase alignment with the grid voltage. The dual-loop control (voltage outer loop and current inner loop) uses a phase-locked loop (PLL) to synchronize the reference current with the grid voltage. It provides high-quality output current and unity power factor operation, but it cannot regulate reactive power independently.
The direct power control (DPC) method calculates the active power \( P \) and reactive power \( Q \) from the grid voltage and current, then compares them with the reference values. The errors are processed by PI controllers to generate the amplitude and phase of the reference current. The DPC method allows independent control of active and reactive power, making it more flexible for grid support.
The instantaneous active and reactive power in a single-phase system can be expressed by constructing virtual orthogonal voltages and currents:
$$
P = \frac{1}{2}\left( u_g i_g + u_\beta i_\beta \right)
$$
$$
Q = \frac{1}{2}\left( u_\beta i_g – u_g i_\beta \right)
$$
where \( u_\beta \) and \( i_\beta \) are obtained by delaying the measured grid voltage and current by a quarter of the fundamental period. The reference current is then calculated as
$$
i_g^* = I_{gm}^* \cos(\omega t + \theta^*)
$$
with
$$
I_{pm}^* = \frac{2P^*}{U_{gm}}, \quad I_{qm}^* = \frac{2Q^*}{U_{gm}}, \quad I_{gm}^* = \sqrt{I_{pm}^{*2}+I_{qm}^{*2}}, \quad \theta^* = \tan^{-1}\left(\frac{I_{qm}^*}{I_{pm}^*}\right)
$$
where \( U_{gm} \) is the amplitude of the grid voltage.
4.2 Maximum Power Point Tracking Algorithms
To maximize the output power of the PV panels, a maximum power point tracking (MPPT) algorithm is required. I compared three common algorithms: constant voltage tracking, perturb and observe (P&O), and incremental conductance (INC). Constant voltage tracking is simple but sensitive to temperature variations. The P&O method is widely used but causes oscillations around the maximum power point. The INC method compares the incremental conductance \( dI/dV \) with the instantaneous conductance \( -I/V \). It offers faster response and better accuracy. The decision rules are:
- If \( dI_{pv}/dV_{pv} > -I_{pv}/V_{pv} \), increase the reference voltage.
- If \( dI_{pv}/dV_{pv} < -I_{pv}/V_{pv} \), decrease the reference voltage.
- If \( dI_{pv}/dV_{pv} = -I_{pv}/V_{pv} \), maintain the reference voltage.
I selected the INC method because of its high stability and fast tracking speed.
4.3 Combined Control Strategy and Simulation
I combined the direct power control with the INC-based MPPT to form a unified grid-connected control strategy. The MPPT block outputs the maximum power reference \( P^* \), and the reactive power reference \( Q^* \) can be set independently. The overall control block diagram is shown in the original thesis. I built a simulation model in MATLAB/Simulink using the proposed inverter. The initial conditions were: irradiance \( S=1000~\mathrm{W/m^2} \), temperature \( T=25^\circ\mathrm{C} \), PV maximum power \( P_{mpp}=500~\mathrm{W} \), MPP voltage \( V_{mpp}=100~\mathrm{V} \), MPP current \( I_{mpp}=5~\mathrm{A} \), open-circuit voltage \( V_{oc}=140~\mathrm{V} \), short-circuit current \( I_{sc}=7~\mathrm{A} \).
Simulation results at the initial condition are shown in Fig. 4.11. The PV voltage settles at 100 V, current at 5 A, and power at 500 W after about 0.2 s. The grid voltage and grid current are in phase, and the THD of the grid current is 3.62%, satisfying the grid connection standard.
I also tested dynamic responses under different environmental changes. When the irradiance steps from 1000 to 600 W/m² at 0.5 s and the reactive power reference \( Q^* \) steps from 0 to 200 Var, the MPPT succeeds in tracking the new maximum power point, and the output current phase changes accordingly, demonstrating reactive power capability. Similarly, when temperature changes from 25°C to 100°C, the system dynamically tracks the reduced maximum power. The proposed control strategy maintains good performance in all tested cases.
5. Hardware Design and Experimental Verification
5.1 Main Circuit Parameter Design
For the CCM operation, the input inductor \( L_{in} \) is designed based on the desired current ripple. The average input current is
$$
I_{Lin,avg} = \frac{P_o}{U_{in}}
$$
Let \( \gamma \) be the ripple coefficient. The inductance is calculated as
$$
L_{in} = \frac{U_{in} D T_s}{\gamma \cdot \frac{P_o}{U_{in}}}
$$
Using \( U_{in}=100~\mathrm{V} \), \( D=0.5 \), \( T_s=50~\mu\mathrm{s} \), \( P_o=450~\mathrm{W} \), and \( \gamma=0.3 \), I obtain \( L_{in} \approx 3.7~\mathrm{mH} \). I selected 4 mH.
The storage capacitors are chosen to limit the voltage ripple. The capacitance can be estimated by
$$
C \ge \frac{U_C}{R_C \Delta U_C f_s}
$$
I selected two capacitors of 220 μF each, with a rated voltage of 450 V, to provide sufficient energy storage and low voltage ripple.
The power switches and diodes are selected based on their voltage and current stresses. The maximum voltage stress is 250 V across \( S_1 \), and the maximum current stress is about 10.3 A for \( S_1 \). I chose the MOSFET IRFP460PBF (500 V, 20 A, \( R_{DS(on)}=0.27~\Omega \)) and the fast-recovery diode QRT3006P (600 V, 30 A).
The LCL filter comprises the inverter-side inductor \( L_{f1} \), the filter capacitor \( C_f \), and the grid-side inductor \( L_{f2} \). The design procedure yields \( L_{f1}=4~\mathrm{mH} \), \( C_f=5~\mu\mathrm{F} \), and \( L_{f2}=5~\mathrm{mH} \). The resonance frequency is
$$
f_r = \frac{1}{2\pi} \sqrt{\frac{L_{f1}+L_{f2}}{L_{f1}L_{f2}C_f}} \approx 1.6~\mathrm{kHz}
$$
which is well below the switching frequency of 20 kHz.
5.2 Control Circuit Design
I used the digital signal processor TMS320F28335 as the control core. This is a 32-bit floating-point DSP with a maximum clock frequency of 150 MHz, separate 12-bit ADCs, and multiple EPWM modules. The PWM signals are generated with a carrier frequency of 20 kHz.
The driver circuit uses the isolated gate driver IC NSI6602A. Each chip provides two isolated PWM outputs with adjustable dead time. The low-voltage side is powered by 3.3 V from the DSP, while the high-voltage side uses isolated 15 V supplies from DC-DC modules B1515S-1W. The dead-time resistor is set to 10 kΩ, giving a dead time of 100 ns. The driver circuit successfully amplifies the 3.3 V PWM signals from the DSP to 15 V driving signals.
The voltage sampling circuit uses a differential amplifier DIO2362LSO8 with a voltage divider. For a range of ±400 V, the output voltage is
$$
V_{ADC} = \frac{V_{in}}{300} + 1.65
$$
which maps ±400 V to 0–3.3 V. The current sampling circuit uses the Hall-effect current sensor CC6903SO, whose output is
$$
V_{ADC} = \frac{I_{AC}}{7.58} + 1.65
$$
for a range of ±10 A.
I designed a complete control board integrating the DSP, driver circuits, voltage/current sampling circuits, and isolation modules. The prototype is shown in the thesis. The experimental setup includes a DC power supply, the power board, the control board, an oscilloscope, and a resistive load.
5.3 Experimental Results
The experimental parameters are listed in Table 5.4.
| Parameter | Value |
|---|---|
| Input voltage \( U_{in} \) | 80–120 V |
| Output voltage \( U_g \) | 110 V/50 Hz |
| Output power \( P_o \) | 450 W |
| Switching frequency \( f_s \) | 20 kHz |
| Input inductor \( L_{in} \) | 4 mH |
| Storage capacitors \( C_1,C_2 \) | 220 μF |
| Filter inductors \( L_{f1},L_{f2} \) | 4 mH, 5 mH |
| Filter capacitor \( C_f \) | 5 μF |
Figure 5.19 shows the input voltage, output voltage, and output current waveforms. The output voltage is regulated at 110 V AC, and the output current is about 4 A, corresponding to 440 W. The waveforms are clean and stable.
The bridge voltage \( u_{AB} \) is shown in Fig. 5.20. It clearly exhibits five levels: \( +2U_C \), \( +U_C \), 0, \( -U_C \), \( -2U_C \). The peak voltage is about 240 V, consistent with the theoretical capacitor voltage \( U_C \approx 120~\mathrm{V} \).
The gate signal of \( S_1 \) and the input inductor current are shown in Fig. 5.21. The gate signal has a constant duty cycle, and the inductor current is continuous with no zero crossings. The average input current is about 4.5 A, and the ripple is small. This confirms the CCM operation of the improved modulation strategy.
Figure 5.22 shows the common-mode voltage and leakage current waveforms. Both are approximately zero, verifying that the proposed topology inherently suppresses leakage current. This is a significant improvement for transformerless solar inverters.
The voltage stresses of the seven switches are shown in Fig. 5.23. Switches \( S_1,S_2,S_3,S_5,S_7 \) withstand about 240 V, while \( S_4 \) and \( S_6 \) withstand about 120 V. These values match the theoretical analysis, confirming the proper design.
I also tested the dynamic response to reference current steps. When the reference current changes from 2.9 A to 4.09 A and vice versa, the grid current follows quickly with minimal overshoot, as shown in Fig. 5.24. This demonstrates the effectiveness of the control strategy.
Moreover, I verified the reactive power capability by operating the inverter at non-unity power factor. The current was observed leading or lagging the grid voltage, as shown in Fig. 5.25. This confirms the smooth control of active and reactive power.
Finally, I measured the efficiency of the proposed inverter at different output power levels. The efficiency curve is shown in Fig. 5.26. The maximum efficiency is about 95.5% at 500 W, and the efficiency remains above 90% from 100 W to 500 W. Slight deviations from the theoretical values are caused by parasitic resistances and non-idealities of the components.
6. Conclusion and Future Work
6.1 Conclusion
In this thesis, I have proposed and investigated a single-stage non-isolated five-level step-up photovoltaic inverter without leakage current. The key contributions are as follows:
- I derived a new topology that integrates a boost converter with a diode-clamped five-level inverter. The negative terminal of the input DC source is connected directly to the AC neutral point, which eliminates the common-mode leakage current.
- I analyzed the operating principles under conventional SPWM modulation and derived the voltage gain, voltage/current stresses, and loss distribution.
- I introduced an improved constant-duty PWM modulation strategy that makes the input inductor current continuous and the converter operate in CCM. This reduces input current stress, improves the power quality, and simplifies the voltage gain expression.
- I designed a direct power control scheme combined with incremental conductance MPPT for grid-connected operation. Simulation results verified the dynamic performance under varying irradiance, temperature, and reactive power reference.
- I built a 450 W prototype using a TMS320F28335 DSP. Experimental results confirmed the five-level output, continuous input current, low leakage current, appropriate voltage stresses, fast dynamic response, and high efficiency up to 95.5%.
6.2 Future Work
There are still some issues to be addressed in future research. First, the MPPT control was only verified by simulation; I will replace the DC power supply with an actual PV panel to validate the entire system in real operating conditions. Second, I will further compare the improved modulation with the traditional SPWM in terms of loss distribution and thermal performance experimentally. Third, the proposed inverter can be extended to higher-level topologies such as seven-level or nine-level configurations. Fourth, advanced modulation techniques such as model predictive control could be implemented to improve the dynamic performance further.
Overall, the proposed single-stage non-isolated five-level step-up solar inverter without leakage current is a promising solution for low-cost, high-efficiency, and reliable photovoltaic systems.